/*
 * Copyright (c) 2024 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/dt-bindings/pwm/ra_pwm.h>

/ {
	soc {
		sram0: memory@1ffe0000 {
			compatible = "mmio-sram";
			reg = <0x1ffe0000 DT_SIZE_K(640)>;
		};

		ioport8: gpio@40040100 {
			compatible = "renesas,ra-gpio-ioport";
			reg = <0x40040100 0x20>;
			port = <8>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <16>;
			status = "disabled";
		};

		ioport9: gpio@40040120 {
			compatible = "renesas,ra-gpio-ioport";
			reg = <0x40040120 0x20>;
			port = <9>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <16>;
			status = "disabled";
		};

		ioporta: gpio@40040140 {
			compatible = "renesas,ra-gpio-ioport";
			reg = <0x40040140 0x20>;
			port = <10>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <16>;
			status = "disabled";
		};

		ioportb: gpio@40040160 {
			compatible = "renesas,ra-gpio-ioport";
			reg = <0x40040160 0x20>;
			port = <11>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <16>;
			status = "disabled";
		};

		sci5: sci5@400700a0 {
			compatible = "renesas,ra-sci";
			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
			interrupt-names = "rxi", "txi", "tei", "eri";
			reg = <0x400700a0 0x20>;
			clocks = <&pclka MSTPB 26>;
			status = "disabled";
			uart {
				compatible = "renesas,ra-sci-uart";
				channel = <5>;
				status = "disabled";
			};
		};

		sci6: sci6@400700c0 {
			compatible = "renesas,ra-sci";
			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
			interrupt-names = "rxi", "txi", "tei", "eri";
			reg = <0x400700c0 0x20>;
			clocks = <&pclka MSTPB 25>;
			status = "disabled";
			uart {
				compatible = "renesas,ra-sci-uart";
				channel = <6>;
				status = "disabled";
			};
		};

		sci7: sci7@400700e0 {
			compatible = "renesas,ra-sci";
			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
			interrupt-names = "rxi", "txi", "tei", "eri";
			reg = <0x400700e0 0x20>;
			clocks = <&pclka MSTPB 24>;
			status = "disabled";
			uart {
				compatible = "renesas,ra-sci-uart";
				channel = <7>;
				status = "disabled";
			};
		};

		iic2: iic2@40053200 {
			compatible = "renesas,ra-iic";
			channel = <2>;
			reg = <0x40053200 0x100>;
			status = "disabled";
		};

		usbhs: usbhs@40060000 {
			compatible = "renesas,ra-usb";
			reg = <0x40060000 0x2000>;
			interrupts = <54 12>, <55 12>, <56 12>;
			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
			num-bidir-endpoints = <10>;
			phys = <&usbhs_phy>;
			status = "disabled";
			udc {
				compatible = "renesas,ra-udc";
				status = "disabled";
			};
		};

		adc@4005c000 {
			channel-count = <13>;
			channel-available-mask = <0x1f00ff>;
		};

		adc@4005c200 {
			channel-count = <11>;
			channel-available-mask = <0xf00ef>;
		};

		pwm13: pwm13@40078d00 {
			compatible = "renesas,ra-pwm";
			divider = <RA_PWM_SOURCE_DIV_1>;
			channel = <RA_PWM_CHANNEL_13>;
			clocks = <&pclkd MSTPD 6>;
			reg = <0x40078d00 0x100>;
			#pwm-cells = <3>;
			status = "disabled";
		};
	};

	clocks: clocks {
		#address-cells = <1>;
		#size-cells = <1>;

		xtal: clock-main-osc {
			compatible = "renesas,ra-cgc-external-clock";
			clock-frequency = <DT_FREQ_M(24)>;
			#clock-cells = <0>;
			status = "disabled";
		};

		hoco: clock-hoco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(20)>;
			#clock-cells = <0>;
		};

		moco: clock-moco {
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(8)>;
			#clock-cells = <0>;
		};

		loco: clock-loco {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};

		subclk: clock-subclk {
			compatible = "renesas,ra-cgc-subclk";
			clock-frequency = <32768>;
			#clock-cells = <0>;
			status = "disabled";
		};

		pll: pll {
			compatible = "renesas,ra-cgc-pll";
			#clock-cells = <0>;

			/* PLL */
			clocks = <&xtal>;
			div = <2>;
			mul = <20 0>;
			status = "disabled";
		};

		pclkblock: pclkblock@4001e01c {
			compatible = "renesas,ra-cgc-pclk-block";
			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
			      <0x40047008 4>;
			reg-names = "MSTPA", "MSTPB","MSTPC",
				    "MSTPD";
			#clock-cells = <0>;
			clocks = <&pll>;
			status = "okay";

			iclk: iclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclka: pclka {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkb: pclkb {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkc: pclkc {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			pclkd: pclkd {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				#clock-cells = <2>;
				status = "okay";
			};

			bclk: bclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <2>;
				bclkout: bclkout {
					compatible = "renesas,ra-cgc-busclk";
					clk-out-div = <2>;
					sdclk = <1>;
					#clock-cells = <0>;
				};
				#clock-cells = <2>;
				status = "okay";
			};

			uclk: uclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <5>;
				#clock-cells = <2>;
				status = "okay";
			};

			fclk: fclk {
				compatible = "renesas,ra-cgc-pclk";
				div = <4>;
				#clock-cells = <2>;
				status = "okay";
			};

			clkout: clkout {
				compatible = "renesas,ra-cgc-pclk";
				#clock-cells = <2>;
				status = "disabled";
			};
		};
	};

	usbhs_phy: usbhs-phy {
		compatible = "renesas,ra-usbphyc";
		#phy-cells = <0>;
	};
};

&ioport0 {
	port-irqs = <&port_irq6 &port_irq7 &port_irq8
	&port_irq9 &port_irq10 &port_irq11
	&port_irq12 &port_irq13 &port_irq14>;
	port-irq-names = "port-irq6",
			 "port-irq7",
			 "port-irq8",
			 "port-irq9",
			 "port-irq10",
			 "port-irq11",
			 "port-irq12",
			 "port-irq13",
			 "port-irq14";
	port-irq6-pins = <0>;
	port-irq7-pins = <1>;
	port-irq8-pins = <2>;
	port-irq9-pins = <4>;
	port-irq10-pins = <5>;
	port-irq11-pins = <6>;
	port-irq12-pins = <8>;
	port-irq13-pins = <9 15>;
	port-irq14-pins = <10>;
};

&ioport1 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2
	&port_irq3 &port_irq4>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2",
			 "port-irq3",
			 "port-irq4";
	port-irq0-pins = <5>;
	port-irq1-pins = <1 4>;
	port-irq2-pins = <0>;
	port-irq3-pins = <10>;
	port-irq4-pins = <11>;
};

&ioport2 {
	port-irqs = <&port_irq0 &port_irq1 &port_irq2
	&port_irq3>;
	port-irq-names = "port-irq0",
			 "port-irq1",
			 "port-irq2",
			 "port-irq3";
	port-irq0-pins = <6>;
	port-irq1-pins = <5>;
	port-irq2-pins = <3 13>;
	port-irq3-pins = <2 12>;
};

&ioport3 {
	port-irqs = <&port_irq5 &port_irq6
	&port_irq8 &port_irq9>;
	port-irq-names = "port-irq5",
			 "port-irq6",
			 "port-irq8",
			 "port-irq9";
	port-irq5-pins = <2>;
	port-irq6-pins = <1>;
	port-irq8-pins = <5>;
	port-irq9-pins = <4>;
};

&ioport4 {
	port-irqs = <&port_irq0 &port_irq4 &port_irq5
	&port_irq6 &port_irq7 &port_irq8
	&port_irq9>;
	port-irq-names = "port-irq0",
			 "port-irq4",
			 "port-irq5",
			 "port-irq6",
			 "port-irq7",
			 "port-irq8",
			 "port-irq9";
	port-irq0-pins = <0>;
	port-irq4-pins = <2 11>;
	port-irq5-pins = <1 10>;
	port-irq6-pins = <9>;
	port-irq7-pins = <8>;
	port-irq8-pins = <15>;
	port-irq9-pins = <14>;
};

&ioport5 {
	port-irqs = <&port_irq11 &port_irq12 &port_irq14
	&port_irq15>;
	port-irq-names = "port-irq11",
			 "port-irq12",
			 "port-irq14",
			 "port-irq15";
	port-irq11-pins = <1>;
	port-irq12-pins = <2>;
	port-irq14-pins = <5 12>;
	port-irq15-pins = <6 11>;
};

&ioport7 {
	port-irqs = <&port_irq7 &port_irq8 &port_irq10
	&port_irq11>;
	port-irq-names = "port-irq7",
			 "port-irq8",
			 "port-irq10",
			 "port-irq11";
	port-irq7-pins = <6>;
	port-irq8-pins = <7>;
	port-irq10-pins = <9>;
	port-irq11-pins = <8>;
};