1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/delete-node/ &adc1;
12
13/ {
14	soc {
15		sram0: memory@20000000 {
16			compatible = "mmio-sram";
17			reg = <0x20000000 DT_SIZE_K(256)>;
18		};
19
20		ioport6: gpio@400800c0 {
21			compatible = "renesas,ra-gpio-ioport";
22			reg = <0x400800c0 0x20>;
23			port = <6>;
24			gpio-controller;
25			#gpio-cells = <2>;
26			ngpios = <16>;
27			status = "disabled";
28		};
29
30		ioport7: gpio@400800e0 {
31			compatible = "renesas,ra-gpio-ioport";
32			reg = <0x400800e0 0x20>;
33			port = <7>;
34			gpio-controller;
35			#gpio-cells = <2>;
36			ngpios = <16>;
37			status = "disabled";
38		};
39
40		sci1: sci1@40118100 {
41			compatible = "renesas,ra-sci";
42			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
43			interrupt-names = "rxi", "txi", "tei", "eri";
44			reg = <0x40118100 0x100>;
45			clocks = <&pclka MSTPB 30>;
46			status = "disabled";
47			uart {
48				compatible = "renesas,ra-sci-uart";
49				channel = <1>;
50				status = "disabled";
51			};
52		};
53
54		sci2: sci2@40118200 {
55			compatible = "renesas,ra-sci";
56			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
57			interrupt-names = "rxi", "txi", "tei", "eri";
58			reg = <0x40118200 0x100>;
59			clocks = <&pclka MSTPB 29>;
60			status = "disabled";
61			uart {
62				compatible = "renesas,ra-sci-uart";
63				channel = <2>;
64				status = "disabled";
65			};
66		};
67
68		sci3: sci3@40118300 {
69			compatible = "renesas,ra-sci";
70			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
71			interrupt-names = "rxi", "txi", "tei", "eri";
72			reg = <0x40118300 0x100>;
73			clocks = <&pclka MSTPB 28>;
74			status = "disabled";
75			uart {
76				compatible = "renesas,ra-sci-uart";
77				channel = <3>;
78				status = "disabled";
79			};
80		};
81
82		sci4: sci4@40118400 {
83			compatible = "renesas,ra-sci";
84			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
85			interrupt-names = "rxi", "txi", "tei", "eri";
86			reg = <0x40118400 0x100>;
87			clocks = <&pclka MSTPB 27>;
88			status = "disabled";
89			uart {
90				compatible = "renesas,ra-sci-uart";
91				channel = <4>;
92				status = "disabled";
93			};
94		};
95
96		adc@40170000 {
97			channel-count = <11>;
98			channel-available-mask = <0x31ff>;
99		};
100
101		pwm6: pwm6@40169600 {
102			compatible = "renesas,ra-pwm";
103			divider = <RA_PWM_SOURCE_DIV_1>;
104			channel = <RA_PWM_CHANNEL_6>;
105			clocks = <&pclkd MSTPE 25>;
106			reg = <0x40169600 0x100>;
107			#pwm-cells = <3>;
108			status = "disabled";
109		};
110
111		pwm7: pwm7@40169700 {
112			compatible = "renesas,ra-pwm";
113			divider = <RA_PWM_SOURCE_DIV_1>;
114			channel = <RA_PWM_CHANNEL_7>;
115			clocks = <&pclkd MSTPE 24>;
116			reg = <0x40169700 0x100>;
117			#pwm-cells = <3>;
118			status = "disabled";
119		};
120	};
121
122	clocks: clocks {
123		#address-cells = <1>;
124		#size-cells = <1>;
125
126		xtal: clock-main-osc {
127			compatible = "renesas,ra-cgc-external-clock";
128			clock-frequency = <DT_FREQ_M(20)>;
129			#clock-cells = <0>;
130			status = "disabled";
131		};
132
133		hoco: clock-hoco {
134			compatible = "fixed-clock";
135			clock-frequency = <DT_FREQ_M(20)>;
136			#clock-cells = <0>;
137		};
138
139		moco: clock-moco {
140			compatible = "fixed-clock";
141			clock-frequency = <DT_FREQ_M(8)>;
142			#clock-cells = <0>;
143		};
144
145		loco: clock-loco {
146			compatible = "fixed-clock";
147			clock-frequency = <32768>;
148			#clock-cells = <0>;
149		};
150
151		subclk: clock-subclk {
152			compatible = "renesas,ra-cgc-subclk";
153			clock-frequency = <32768>;
154			#clock-cells = <0>;
155			status = "disabled";
156		};
157
158		pll: pll {
159			compatible = "renesas,ra-cgc-pll";
160			#clock-cells = <0>;
161
162			/* PLL */
163			clocks = <&hoco>;
164			div = <2>;
165			mul = <20 0>;
166			status = "disabled";
167		};
168
169		pll2: pll2 {
170			compatible = "renesas,ra-cgc-pll";
171			#clock-cells = <0>;
172
173			/* PLL2 */
174			div = <2>;
175			mul = <20 0>;
176			status = "disabled";
177		};
178
179		pclkblock: pclkblock@40084000 {
180			compatible = "renesas,ra-cgc-pclk-block";
181			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
182			      <0x4008400c 4>, <0x40084010 4>;
183			reg-names = "MSTPA", "MSTPB","MSTPC",
184				    "MSTPD", "MSTPE";
185			#clock-cells = <0>;
186			clocks = <&pll>;
187			status = "okay";
188
189			iclk: iclk {
190				compatible = "renesas,ra-cgc-pclk";
191				div = <1>;
192				#clock-cells = <2>;
193				status = "okay";
194			};
195
196			pclka: pclka {
197				compatible = "renesas,ra-cgc-pclk";
198				div = <2>;
199				#clock-cells = <2>;
200				status = "okay";
201			};
202
203			pclkb: pclkb {
204				compatible = "renesas,ra-cgc-pclk";
205				div = <4>;
206				#clock-cells = <2>;
207				status = "okay";
208			};
209
210			pclkc: pclkc {
211				compatible = "renesas,ra-cgc-pclk";
212				div = <4>;
213				#clock-cells = <2>;
214				status = "okay";
215			};
216
217			pclkd: pclkd {
218				compatible = "renesas,ra-cgc-pclk";
219				div = <2>;
220				#clock-cells = <2>;
221				status = "okay";
222			};
223
224			fclk: fclk {
225				compatible = "renesas,ra-cgc-pclk";
226				div = <4>;
227				#clock-cells = <2>;
228				status = "okay";
229			};
230
231			uclk: uclk {
232				compatible = "renesas,ra-cgc-pclk";
233				#clock-cells = <2>;
234				status = "disabled";
235			};
236
237			clkout: clkout {
238				compatible = "renesas,ra-cgc-pclk";
239				#clock-cells = <2>;
240				status = "disabled";
241			};
242		};
243	};
244};
245
246&ioport0 {
247	port-irqs = <&port_irq6 &port_irq7 &port_irq8
248	&port_irq9 &port_irq10 &port_irq11
249	&port_irq12 &port_irq13>;
250	port-irq-names = "port-irq6",
251			 "port-irq7",
252			 "port-irq8",
253			 "port-irq9",
254			 "port-irq10",
255			 "port-irq11",
256			 "port-irq12",
257			 "port-irq13";
258	port-irq6-pins = <0>;
259	port-irq7-pins = <1>;
260	port-irq8-pins = <2>;
261	port-irq9-pins = <4>;
262	port-irq10-pins = <5>;
263	port-irq11-pins = <6>;
264	port-irq12-pins = <8>;
265	port-irq13-pins = <15>;
266};
267
268&ioport1 {
269	port-irqs = <&port_irq0 &port_irq1 &port_irq2
270	&port_irq3 &port_irq4>;
271	port-irq-names = "port-irq0",
272			 "port-irq1",
273			 "port-irq2",
274			 "port-irq3",
275			 "port-irq4";
276	port-irq0-pins = <5>;
277	port-irq1-pins = <1 4>;
278	port-irq2-pins = <0>;
279	port-irq3-pins = <10>;
280	port-irq4-pins = <11>;
281};
282
283&ioport2 {
284	port-irqs = <&port_irq0 &port_irq1 &port_irq2
285	&port_irq3>;
286	port-irq-names = "port-irq0",
287			 "port-irq1",
288			 "port-irq2",
289			 "port-irq3";
290	port-irq0-pins = <6>;
291	port-irq1-pins = <5>;
292	port-irq2-pins = <13>;
293	port-irq3-pins = <12>;
294};
295
296&ioport3 {
297	port-irqs = <&port_irq5 &port_irq6
298	&port_irq8 &port_irq9>;
299	port-irq-names = "port-irq5",
300			 "port-irq6",
301			 "port-irq8",
302			 "port-irq9";
303	port-irq5-pins = <2>;
304	port-irq6-pins = <1>;
305	port-irq8-pins = <5>;
306	port-irq9-pins = <4>;
307};
308
309&ioport4 {
310	port-irqs = <&port_irq0 &port_irq4 &port_irq5
311	&port_irq6 &port_irq7 &port_irq8
312	&port_irq9 &port_irq14 &port_irq15>;
313	port-irq-names = "port-irq0",
314			 "port-irq4",
315			 "port-irq5",
316			 "port-irq6",
317			 "port-irq7",
318			 "port-irq8",
319			 "port-irq9",
320			 "port-irq14",
321			 "port-irq15";
322	port-irq0-pins = <0>;
323	port-irq4-pins = <2 11>;
324	port-irq5-pins = <1 10>;
325	port-irq6-pins = <9>;
326	port-irq7-pins = <8>;
327	port-irq8-pins = <15>;
328	port-irq9-pins = <14>;
329	port-irq14-pins = <3>;
330	port-irq15-pins = <4>;
331};
332
333&ioport5 {
334	port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
335	port-irq-names = "port-irq11",
336			 "port-irq12",
337			 "port-irq14";
338	port-irq11-pins = <1>;
339	port-irq12-pins = <2>;
340	port-irq14-pins = <5>;
341};
342
343&ioport7 {
344	port-irqs = <&port_irq11>;
345	port-irq-names = "port-irq11";
346	port-irq11-pins = <8>;
347};
348