Searched full:pllq (Results 1 – 21 of 21) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f7-pll-clock.yaml | 13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
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| D | st,stm32f2-pll-clock.yaml | 13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
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| D | st,stm32g4-pll-clock.yaml | 15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48MCLK (for USB, RNG)
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| D | st,stm32f4-pll-clock.yaml | 15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
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| D | st,stm32g0-pll-clock.yaml | 15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
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| D | st,stm32u0-pll-clock.yaml | 15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
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| D | st,stm32wba-pll-clock.yaml | 17 f(PLL_Q) = f(VCO clock) / PLLQ
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| D | st,stm32wb-pll-clock.yaml | 18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
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| D | st,stm32l4-pll-clock.yaml | 18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
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| D | st,stm32u5-pll-clock.yaml | 17 f(PLL_Q) = f(VCO clock) / PLLQ
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_common.h | 25 #define pllq(v) z_pllq(v) macro
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| D | clock_stm32f2_f4_f7.c | 112 pllq(STM32_PLL_Q_DIVISOR)); in config_pll_sysclock()
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| D | clock_stm32_ll_common.c | 607 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR)); in set_up_plls()
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| /Zephyr-latest/boards/renesas/mck_ra8t1/ |
| D | mck_ra8t1.dts | 70 pllq {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_sdmmc.c | 84 TC_PRINT("SDMMC sourced by PLLQ at "); in ZTEST()
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| /Zephyr-latest/dts/arm/renesas/ra/ra8/ |
| D | r7fa8m1xh.dtsi | 64 pllq: pllq { label
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| D | r7fa8t1xh.dtsi | 62 pllq: pllq { label
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| D | r7fa8d1xh.dtsi | 94 pllq: pllq { label
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| /Zephyr-latest/boards/renesas/ek_ra8d1/ |
| D | ek_ra8d1.dts | 105 pllq {
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| /Zephyr-latest/boards/makerbase/mks_canable_v20/doc/ |
| D | index.rst | 82 The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency.
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| /Zephyr-latest/boards/renesas/ek_ra8m1/ |
| D | ek_ra8m1.dts | 142 pllq {
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