Home
last modified time | relevance | path

Searched +full:33 +full:mhz (Results 1 – 25 of 54) sorted by relevance

123

/Zephyr-latest/soc/espressif/common/
DKconfig.spiram87 bool "20MHz clock speed"
91 bool "26MHz clock speed"
95 bool "40MHz clock speed"
98 bool "80MHz clock speed"
102 bool "120MHz clock speed"
157 range 0 33
165 range 0 33
177 range 0 33
185 range 0 33
197 range 0 33
[all …]
/Zephyr-latest/soc/nuvoton/npcx/
DKconfig51 bool "SPI flash max clock rate of 20 MHz"
54 bool "SPI flash max clock rate of 25 MHz"
57 bool "SPI flash max clock rate of 33 MHz"
61 bool "SPI flash max clock rate of 40 MHz"
64 bool "SPI flash max clock rate of 50 MHz"
71 default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay40 /* Baud rate on each pin is 1MHz */
53 doca = [40 8A 00 00 29 19 A5 33];
54 pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31];
55 ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32];
/Zephyr-latest/doc/hardware/peripherals/
Despi.rst14 lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
77 array[0]: PID[47:33] MIPI manufacturer ID.
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
/Zephyr-latest/boards/arduino/nano_33_iot/doc/
Dindex.rst3 Arduino Nano 33 IOT
9 The Arduino Nano 33 IOT is a small form factor development board with USB,
14 :alt: Arduino Nano 33 IOT
19 - ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz
78 The SAMD21 MCU is configured to use the 8 MHz internal oscillator
79 with the on-chip PLL generating the 48 MHz system clock. The internal
112 The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The
129 #. Connect the Nano 33 IOT to your host computer using USB
168 https://store.arduino.cc/arduino-nano-33-iot
/Zephyr-latest/dts/bindings/sensor/
Dti,fdc2x1x.yaml46 The internal clock oscillates at around 43360 KHz (43.36 MHz)
48 Recommended external clock source frequency is 40000 KHz (40 MHz).
97 1 = 1MHz
98 4 = 3.3MHz
99 5 = 10MHz
100 7 = 33MHz
234 0.01MHz and 8.75MHz
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
236 and 10MHz
240 0.01MHz and 10MHz
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml94 111 40_OHM — 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_saml2x.c22 * the CPU clock will be configured to 48 MHz, and run via DFLL48M.
26 * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
28 * GCLK Gen 2 -> USB @ 48 MHz
29 * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
34 /* by default, OSC16M will be enabled at 4 MHz, and the CPU will in gclk_reset()
119 * Fgclk_dfll48m_ref max is 33 kHz in dfll48m_init()
140 /* if the target frequency is 48 MHz, then the calibration value can be used to in dfll48m_init()
174 /* use a 16 MHz -> 31.25 kHz reference... 48e6 / 31,250 = 1,536 in dfll48m_init()
176 * 16 MHz source directly in dfll48m_init()
198 /* PL2, >= 2.7v, 48MHz = 2 wait states */ in flash_waitstates_init()
/Zephyr-latest/drivers/audio/
Dtlv320dac310x.h33 #define DAC_PROC_CLK_FREQ_MAX 49152000 /* 49.152 MHz */
41 #define DAC_MOD_CLK_FREQ_MIN 2800000 /* 2.8 MHz */
42 #define DAC_MOD_CLK_FREQ_MAX 6200000 /* 6.2 MHz */
96 #define HP_OUT_POP_RM_ADDR (struct reg_addr){1, 33}
/Zephyr-latest/boards/pine64/pinetime_devkit0/
Dpinetime_devkit0.dts95 mipi-max-frequency = <8000000>; /* 8MHz */
108 porch-param = [0c 0c 00 33 33];
197 spi-max-frequency = <8000000>; /* 8MHz */
/Zephyr-latest/include/zephyr/sd/
Dsd_spec.h56 SD_ERASE_BLOCK_END = 33,
373 HS_MAX_DTR = MHZ(50),
379 UHS_SDR12_MAX_DTR = MHZ(25),
380 UHS_SDR25_MAX_DTR = MHZ(50),
381 UHS_SDR50_MAX_DTR = MHZ(100),
382 UHS_SDR104_MAX_DTR = MHZ(208),
383 UHS_DDR50_MAX_DTR = MHZ(50),
432 SD_CLOCK_25MHZ = MHZ(25),
433 SD_CLOCK_50MHZ = MHZ(50),
434 SD_CLOCK_100MHZ = MHZ(100),
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx7.dtsi105 interrupts = <33 3>;
122 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
123 core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
124 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
125 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
126 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
Dnpcx9.dtsi107 interrupts = <33 3>;
153 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
154 core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
155 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
156 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
157 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
158 apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
Dnpcx4.dtsi109 interrupts = <33 3>;
153 clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */
154 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
155 apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */
156 apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */
157 apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */
158 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */
/Zephyr-latest/boards/st/nucleo_h503rb/doc/
Dindex.rst36 - 24 MHz HSE crystal oscillator
49 RISC core. They operate at a frequency of up to 250 MHz.
64 - Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
66 - External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE
76 - 1x operational amplifier (7 MHz bandwidth)
172 240 MHz, driven by an 24 MHz high-speed external clock.
185 VBAT can be provided via the left ST Morpho connector's pin 33.
/Zephyr-latest/dts/arm/atmel/
Dsamd5x.dtsi124 interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
321 * 16 MHz max, source clock must not exceed 100 MHz.
324 * -> 48 MHz GCLK(2) / 4 = 12 MHz
343 * 16 MHz max, source clock must not exceed 100 MHz.
346 * -> 48 MHz GCLK(2) / 4 = 12 MHz
/Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/doc/
Dindex.rst14 dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application
15 processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations,
62 33. Arduino Uno R3 compatible ICSP header (J5)1
109 the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
/Zephyr-latest/boards/st/nucleo_h533re/doc/
Dindex.rst46 They operate at a frequency of up to 250 MHz.
51 - 375 DMPIS/MHz (Dhrystone 2.1)
75 - 24 MHz crystal oscillator (HSE)
77 - Internal 64 MHz (HSI) trimmable by software
79 - Internal 4 MHz oscillator (CSI), trimmable by software
80 - Internal 48 MHz (HSI48) with recovery system
220 240MHz, driven by an 24MHz high-speed external clock.
233 VBAT can be provided via the left ST Morpho connector's pin 33.
/Zephyr-latest/boards/st/nucleo_h563zi/doc/
Dindex.rst46 They operate at a frequency of up to 250 MHz.
51 - 375 DMPIS/MHz (Dhrystone 2.1)
68 - 25 MHz crystal oscillator (HSE)
70 - Internal 64 MHz (HSI) trimmable by software
72 - Internal 4 MHz oscillator (CSI), trimmable by software
73 - Internal 48 MHz (HSI48) with recovery system
234 240MHz, driven by 8MHz external clock provided from the STLINK-V3EC.
247 VBAT can be provided via the left ST Morpho connector's pin 33.
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c36 * HW count resolution is 48 MHz.
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
53 #define HIBTIMER_MS_TO_CNT(x) ((uint32_t)(x) * 33U)
191 uint16_t period_max; /* monitor values in units of 48MHz (20.8 ns) */
655 * PLL domain: 32 KHz clock input for PLL to produce 96 MHz and 48 MHz clocks
921 return MHZ(48); in get_turbo_clock()
927 return MHZ(96); in get_turbo_clock()
930 return MHZ(48); in get_turbo_clock()
941 * PLL domain supplies 96 MHz, 48 MHz, and other high speed clocks to all
943 * is derived from the 48 MHz produced by the PLL.
[all …]
/Zephyr-latest/samples/boards/microchip/mec15xxevb_assy6853/power_management/src/
Dpower_mgmt.c62 * JP75 32-33 closed
343 /* Trigger Light Sleep 1 state. 48MHz PLL stays on */ in test_pwr_mgmt_singlethread()
355 /* Trigger Deep Sleep 1 state. 48MHz PLL off */ in test_pwr_mgmt_singlethread()
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt1010.dtsi172 interrupts = <33 3>;
290 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
298 /* The maximum input frequency into the SAI mclk input is 300MHz
/Zephyr-latest/boards/cypress/cy8ckit_062_ble/doc/
Dindex.rst13 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm
69 33. U.FL connector for external antenna (J17)1
122 the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the

123