1.. zephyr:board:: nucleo_h533re 2 3Overview 4******** 5 6The Nucleo H533RE board is designed as an affordable development platform for 7STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H533RET6 8microcontroller with TrustZone |reg|. 9Here are some highlights of the Nucleo H533RE board: 10 11- STM32H533RE microcontroller featuring 512 kbytes of Flash memory and 272 Kbytes of 12 SRAM in LQFP64 package 13 14- Board connectors: 15 16 - USB Type-C |trade| Sink device FS 17 - ST Zio expansion connector including Arduino Uno V3 connectivity (CN5, CN6, CN8, CN9) 18 - ST morpho extension connector (CN7, CN10) 19 20- Flexible board power supply: 21 22 - 5V_USB_STLK from ST-Link USB connector 23 - VIN (7 - 12V, 0.8) supplied via pin header CN6 pin 8 or CN7 pin 24 24 - ESV on the ST morpho connector CN7 Pin 6 (5V, O.5A) 25 - VBUS_STLK from a USB charger via the ST-LINK USB connector 26 - VBUSC from the USB user connector (5V, 0.5A) 27 - 3V3_EXT supplied via a pin header CN6 pin 4 or CN7 pin 16 (3.3V, 1.3A) 28 29- On-board ST-LINK/V3EC debugger/programmer 30 31 - mass storage 32 - Virtual COM port 33 - debug port 34 35- One user LED shared with ARDUINO |reg| Uno V3 36- Two push-buttons: USER and RESET 37- 32.768 kHz crystal oscillator 38 39More information about the board can be found at the `NUCLEO_H533RE website`_. 40 41Hardware 42******** 43 44The STM32H533xx devices are high-performance microcontrollers from the STM32H5 45Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. 46They operate at a frequency of up to 250 MHz. 47 48- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. 49- Performance benchmark: 50 51 - 375 DMPIS/MHz (Dhrystone 2.1) 52 53- Security 54 55 - Arm |reg| TrustZone |reg| with Armv8-M mainline security extension 56 - Up to eight configurable SAU regions 57 - TrustZone |reg| aware and securable peripherals 58 - Flexible life cycle scheme with secure debug authentication 59 - SESIP3 and PSA Level 3 certified assurance target 60 - Preconfigured immutable root of trust (ST-iROT) 61 - SFI (secure firmware installation) 62 - Root of trust thanks to unique boot entry and secure hide protection area (HDP) 63 - Secure data storage with hardware unique key (HUK) 64 - Secure firmware upgrade support with TF-M 65 - Two AES coprocessors including one with DPA resistance 66 - Public key accelerator, DPA resistant 67 - On-the-fly decryption of Octo-SPI external memories 68 - HASH hardware accelerator 69 - True random number generator, NIST SP800-90B compliant 70 - 96-bit unique ID 71 - Active tampers 72 73- Clock management: 74 75 - 24 MHz crystal oscillator (HSE) 76 - 32 kHz crystal oscillator for RTC (LSE) 77 - Internal 64 MHz (HSI) trimmable by software 78 - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) 79 - Internal 4 MHz oscillator (CSI), trimmable by software 80 - Internal 48 MHz (HSI48) with recovery system 81 - 3 PLLs for system clock, USB, audio, ADC 82 83- Power management 84 85 - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry 86 - Embedded SMPS step-down converter 87 88- RTC with HW calendar, alarms and calibration 89- Up to 112 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V 90- Up to 16 timers and 2 watchdogs 91 92 - 8x 16-bit 93 - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input 94 - 2x 16-bit low-power 16-bit timers (available in Stop mode) 95 - 2x watchdogs 96 - 2x SysTick timer 97 98- Memories 99 100 - Up to 512 Kbytes Flash, 2 banks read-while-write 101 - 1 Kbyte OTP (one-time programmable) 102 - 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC) 103 - 2 Kbytes of backup SRAM available in the lowest power modes 104 - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories 105 - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats 106 - 1x SD/SDIO/MMC interfaces 107 108- Rich analog peripherals (independent supply) 109 110 - 2x 12-bit ADC with up to 5 MSPS in 12-bit 111 - 1x 12-bit DAC with 2 channels 112 - 1x Digital temperature sensor 113 - Voltage reference buffer 114 115- 34x communication interfaces 116 117 - 1x USB Type-C / USB power-delivery controller 118 - 1x USB 2.0 full-speed host and device (crystal-less) 119 - 3x I2C FM+ interfaces (SMBus/PMBus) 120 - 2x I3C interface 121 - 6x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) 122 - 1x LP UART 123 - 4x SPIs including 3 muxed with full-duplex I2S 124 - 4x additional SPI from 4x USART when configured in Synchronous mode 125 - 2x FDCAN 126 - 1x SDMMC interface 127 - 2x 16 channel DMA controllers 128 - 1x 8- to 14- bit camera interface 129 - 1x HDMI-CEC 130 - 1x 16-bit parallel slave synchronous-interface 131 132- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| 133 134More information about STM32H533RE can be found here: 135 136- `STM32H533re on www.st.com`_ 137- `STM32H533 reference manual`_ 138 139Supported Features 140================== 141 142The Zephyr nucleo_h533re board configuration supports the following hardware features: 143 144+-----------+------------+-------------------------------------+ 145| Interface | Controller | Driver/Component | 146+===========+============+=====================================+ 147| CLOCK | on-chip | reset and clock control | 148+-----------+------------+-------------------------------------+ 149| GPIO | on-chip | gpio | 150+-----------+------------+-------------------------------------+ 151| NVIC | on-chip | nested vector interrupt controller | 152+-----------+------------+-------------------------------------+ 153| PINMUX | on-chip | pinmux | 154+-----------+------------+-------------------------------------+ 155| PWM | on-chip | PWM | 156+-----------+------------+-------------------------------------+ 157| RNG | on-chip | True Random number generator | 158+-----------+------------+-------------------------------------+ 159| RTC | on-chip | Real Time Clock | 160+-----------+------------+-------------------------------------+ 161| BKP SRAM | on-chip | Backup SRAM | 162+-----------+------------+-------------------------------------+ 163| UART | on-chip | serial port-polling; | 164| | | serial port-interrupt | 165+-----------+------------+-------------------------------------+ 166| WATCHDOG | on-chip | independent watchdog | 167+-----------+------------+-------------------------------------+ 168| ADC | on-chip | ADC Controller | 169+-----------+------------+-------------------------------------+ 170| USB | on-chip | USB full-speed host/device bus | 171+-----------+------------+-------------------------------------+ 172| SPI | on-chip | spi | 173+-----------+------------+-------------------------------------+ 174 175Other hardware features are not yet supported on this Zephyr port. 176 177The default configuration can be found in the defconfig and dts files: 178 179- Secure target: 180 181 - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re_defconfig` 182 - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re.dts` 183 184Zephyr board options 185==================== 186 187The STM32H533 is a SoC with Cortex-M33 architecture. Zephyr provides support 188for building for Secure firmware. 189 190The BOARD options are summarized below: 191 192+----------------------+-----------------------------------------------+ 193| BOARD | Description | 194+======================+===============================================+ 195| nucleo_h533re | For building Secure firmware | 196+----------------------+-----------------------------------------------+ 197 198Connections and IOs 199=================== 200 201Nucleo H533RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, 202input/output, pull-up, etc. 203 204For more details please refer to `STM32H5 Nucleo-64 board User Manual`_. 205 206Default Zephyr Peripheral Mapping: 207---------------------------------- 208 209- ADC1 channel 0 input: PA0 210- USART1 TX/RX : PB14/PB15 (Arduino USART1) 211- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9 212- UART2 TX/RX : PA2/PA3 (VCP) 213- USER_PB : PC13 214 215System Clock 216------------ 217 218Nucleo H533RE System Clock could be driven by internal or external oscillator, 219as well as main PLL clock. By default System clock is driven by PLL clock at 220240MHz, driven by an 24MHz high-speed external clock. 221 222Serial Port 223----------- 224 225Nucleo H533RE board has up to 4 USARTs, 2 UARTs, and one LPUART. The Zephyr console output is assigned 226to USART2. Default settings are 115200 8N1. 227 228Backup SRAM 229----------- 230 231In order to test backup SRAM, you may want to disconnect VBAT from VDD_MCU. 232You can do it by removing ``SB38`` jumper on the back side of the board. 233VBAT can be provided via the left ST Morpho connector's pin 33. 234 235Programming and Debugging 236************************* 237 238Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface. 239This probe allows to flash the board using various tools. 240 241Applications for the ``nucleo_h533re`` board can be built and 242flashed in the usual way (see :ref:`build_an_application` and 243:ref:`application_run` for more details). 244 245OpenOCD Support 246=============== 247 248For now, openocd support for stm32h5 is not available on upstream OpenOCD. 249You can check `OpenOCD official Github mirror`_. 250In order to use it though, you should clone from the cutomized 251`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines. 252Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in 253:zephyr_file:`boards/st/nucleo_h533re/board.cmake` to point the build 254to the paths of the OpenOCD binary and its scripts, before 255including the common openocd.board.cmake file: 256 257 .. code-block:: none 258 259 set(OPENOCD "<path_to_openocd_repo>/src/openocd" CACHE FILEPATH "" FORCE) 260 set(OPENOCD_DEFAULT_PATH <path_to_opneocd_repo>/tcl) 261 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) 262 263Flashing 264======== 265 266The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, 267so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required. 268 269Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using 270the ``--runner`` (or ``-r``) option: 271 272.. code-block:: console 273 274 $ west flash --runner openocd 275 $ west flash --runner pyocd 276 $ west flash --runner jlink 277 278For pyOCD, additional target information needs to be installed 279which can be done by executing the following commands: 280 281.. code-block:: console 282 283 $ pyocd pack --update 284 $ pyocd pack --install stm32h5 285 286Flashing an application to Nucleo H533RE 287---------------------------------------- 288 289Connect the Nucleo H533RE to your host computer using the USB port. 290Then build and flash an application. Here is an example for the 291:zephyr:code-sample:`hello_world` application. 292 293Run a serial host program to connect with your Nucleo board: 294 295.. code-block:: console 296 297 $ minicom -D /dev/ttyACM0 298 299Then build and flash the application. 300 301.. zephyr-app-commands:: 302 :zephyr-app: samples/hello_world 303 :board: nucleo_h533re 304 :goals: build flash 305 306You should see the following message on the console: 307 308.. code-block:: console 309 310 Hello World! nucleo_h533re 311 312Debugging 313========= 314 315You can debug an application in the usual way. Here is an example for the 316:zephyr:code-sample:`blinky` application. 317 318.. zephyr-app-commands:: 319 :zephyr-app: samples/basic/blinky 320 :board: nucleo_h533re 321 :goals: debug 322 323.. _NUCLEO_H533RE website: 324 https://www.st.com/en/evaluation-tools/nucleo-h533re 325 326.. _STM32H5 Nucleo-64 board User Manual: 327 https://www.st.com/resource/en/user_manual/um3121-stm32h5-nucleo64-board-mb1814-stmicroelectronics.pdf 328 329.. _STM32H533RE on www.st.com: 330 https://www.st.com/en/microcontrollers-microprocessors/stm32h533re 331 332.. _STM32H533 reference manual: 333 https://www.st.com/resource/en/reference_manual/rm0481-stm32h533-stm32h563-stm32h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf 334 335.. _STM32CubeProgrammer: 336 https://www.st.com/en/development-tools/stm32cubeprog.html 337 338.. _OpenOCD official Github mirror: 339 https://github.com/openocd-org/openocd/ 340 341.. _STMicroelectronics OpenOCD Github: 342 https://github.com/STMicroelectronics/OpenOCD/tree/openocd-cubeide-r6 343
