1/*
2 * Copyright (c) 2021 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* NPCX7 series pinmux mapping table */
8#include "npcx7/npcx7-alts-map.dtsi"
9/* NPCX7 series mapping table between MIWU wui bits and source device */
10#include "npcx7/npcx7-miwus-wui-map.dtsi"
11/* NPCX7 series mapping table between MIWU groups and interrupts */
12#include "npcx7/npcx7-miwus-int-map.dtsi"
13/* NPCX7 series eSPI VW mapping table */
14#include "npcx7/npcx7-espi-vws-map.dtsi"
15/* NPCX7 series low-voltage io controls mapping table */
16#include "npcx7/npcx7-lvol-ctrl-map.dtsi"
17
18/* Device tree declarations of npcx soc family */
19#include "npcx.dtsi"
20
21/ {
22	cpus {
23		cpu0: cpu@0 {
24			cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
25		};
26
27		power-states {
28			suspend_to_idle0: suspend-to-idle0 {
29				compatible = "zephyr,power-state";
30				power-state-name = "suspend-to-idle";
31				substate-id = <0>;
32				min-residency-us = <1000>;
33			};
34
35			suspend_to_idle1: suspend-to-idle1 {
36				compatible = "zephyr,power-state";
37				power-state-name = "suspend-to-idle";
38				substate-id = <1>;
39				min-residency-us = <201000>;
40			};
41		};
42	};
43
44	def-io-conf-list {
45		pinmux = <&alt0_gpio_no_spip
46			   &alt0_gpio_no_fpip
47			   &alt1_no_pwrgd
48			   &alta_no_peci_en
49			   &altd_npsl_in1_sl
50			   &altd_npsl_in2_sl
51			   &altd_psl_in3_sl
52			   &altd_psl_in4_sl
53			   &alt7_no_ksi0_sl
54			   &alt7_no_ksi1_sl
55			   &alt7_no_ksi2_sl
56			   &alt7_no_ksi3_sl
57			   &alt7_no_ksi4_sl
58			   &alt7_no_ksi5_sl
59			   &alt7_no_ksi6_sl
60			   &alt7_no_ksi7_sl
61			   &alt8_no_kso00_sl
62			   &alt8_no_kso01_sl
63			   &alt8_no_kso02_sl
64			   &alt8_no_kso03_sl
65			   &alt8_no_kso04_sl
66			   &alt8_no_kso05_sl
67			   &alt8_no_kso06_sl
68			   &alt8_no_kso07_sl
69			   &alt9_no_kso08_sl
70			   &alt9_no_kso09_sl
71			   &alt9_no_kso10_sl
72			   &alt9_no_kso11_sl
73			   &alt9_no_kso12_sl
74			   &alt9_no_kso13_sl
75			   &alt9_no_kso14_sl
76			   &alt9_no_kso15_sl
77			   &alta_no_kso16_sl
78			   &alta_no_kso17_sl>;
79	};
80
81	soc {
82		compatible = "nuvoton,npcx7", "nuvoton,npcx", "simple-bus";
83
84		bbram: bb-ram@400af000 {
85			compatible = "nuvoton,npcx-bbram";
86			reg = <0x400af000 0x80
87			       0x400af100 0x1>;
88			reg-names = "memory", "status";
89		};
90
91		/* Specific soc devices in npcx7 series */
92		itims: timer@400bc000 {
93			compatible = "nuvoton,npcx-itim-timer";
94			reg = <0x400bc000 0x2000
95			       0x400be000 0x2000>;
96			reg-names = "evt_itim", "sys_itim";
97			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3
98				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
99			interrupts = <46 1>; /* Event timer interrupt */
100		};
101
102		uart1: serial@400c4000 {
103			compatible = "nuvoton,npcx-uart";
104			reg = <0x400C4000 0x2000>;
105			interrupts = <33 3>;
106			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
107			uart-rx = <&wui_cr_sin1>;
108			status = "disabled";
109		};
110
111		uart2: serial@400c6000 {
112			compatible = "nuvoton,npcx-uart";
113			reg = <0x400C6000 0x2000>;
114			interrupts = <32 3>;
115			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>;
116			uart-rx = <&wui_cr_sin2>;
117			status = "disabled";
118		};
119
120		/* Default clock and power settings in npcx9 series */
121		pcc: clock-controller@4000d000 {
122			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
123			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
124			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
125			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
126			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
127			ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */
128			pwdwn-ctl-val = <0xfb /* No FIU_PD */
129					 0xff
130					 0x1f /* No GDMA_PD */
131					 0xff
132					 0xfa
133					 0x7f /* No ESPI_PD */
134					 0xe7>;
135		};
136
137		/* Wake-up input source mapping for GPIOs in npcx7 series */
138		gpio0: gpio@40081000 {
139			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
140				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
141
142			lvol-maps = <&lvol_io00 &lvol_none &lvol_none &lvol_none
143				     &lvol_none &lvol_none &lvol_none &lvol_none>;
144		};
145
146		gpio1: gpio@40083000 {
147			wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
148				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
149
150			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
151				     &lvol_none &lvol_none &lvol_none &lvol_none>;
152		};
153
154		gpio2: gpio@40085000 {
155			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
156				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
157
158			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
159				     &lvol_none &lvol_none &lvol_none &lvol_none>;
160		};
161
162		gpio3: gpio@40087000 {
163			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
164				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
165
166			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
167				     &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>;
168		};
169
170		gpio4: gpio@40089000 {
171			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
172				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
173
174			lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none
175				     &lvol_none &lvol_none &lvol_none &lvol_none>;
176		};
177
178		gpio5: gpio@4008b000 {
179			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
180				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
181
182			lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
183				     &lvol_none &lvol_none &lvol_none &lvol_none>;
184		};
185
186		gpio6: gpio@4008d000 {
187			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
188				    &wui_io64 &wui_none &wui_none &wui_io67>;
189
190			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
191				     &lvol_io64 &lvol_none &lvol_none &lvol_none>;
192		};
193
194		gpio7: gpio@4008f000 {
195			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
196				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
197
198			lvol-maps = <&lvol_none &lvol_none &lvol_io72 &lvol_io73
199				     &lvol_io74 &lvol_io75 &lvol_none &lvol_none>;
200		};
201
202		gpio8: gpio@40091000 {
203			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
204				    &wui_none &wui_none &wui_io86 &wui_io87>;
205
206			lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_none
207				     &lvol_none &lvol_none &lvol_io86 &lvol_io87>;
208		};
209
210		gpio9: gpio@40093000 {
211			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
212				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
213
214			lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
215				     &lvol_none &lvol_none &lvol_none &lvol_none>;
216		};
217
218		gpioa: gpio@40095000 {
219			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
220				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
221
222			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
223				     &lvol_none &lvol_none &lvol_none &lvol_none>;
224		};
225
226		gpiob: gpio@40097000 {
227			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
228				    &wui_iob4 &wui_iob5 &wui_none &wui_iob7>;
229
230			lvol-maps = <&lvol_none &lvol_none &lvol_iob2 &lvol_iob3
231				     &lvol_iob4 &lvol_iob5 &lvol_none &lvol_none>;
232		};
233
234		gpioc: gpio@40099000 {
235			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
236				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
237
238			lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none
239				     &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>;
240		};
241
242		gpiod: gpio@4009b000 {
243			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
244				    &wui_iod4 &wui_iod5 &wui_none &wui_iod7>;
245
246			lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_none &lvol_none
247				     &lvol_none &lvol_none &lvol_none &lvol_none>;
248		};
249
250		gpioe: gpio@4009d000 {
251			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
252				    &wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
253
254			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_ioe3
255				     &lvol_ioe4 &lvol_none &lvol_none &lvol_none>;
256		};
257
258		gpiof: gpio@4009f000 {
259			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
260				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
261
262			lvol-maps = <&lvol_none &lvol_none &lvol_iof2 &lvol_iof3
263				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
264		};
265
266		/* ADC0 comparator configuration in npcx7 series */
267		adc0: adc@400d1000 {
268			channel-count = <10>;
269			threshold-count = <3>;
270		};
271
272		/* FIU0 configuration in npcx7 series */
273		qspi_fiu0: quadspi@40020000 {
274			clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
275		};
276
277		shi0: shi@4000f000 {
278			compatible = "nuvoton,npcx-shi";
279			reg = <0x4000f000 0x120>;
280			interrupts = <18 1>;
281			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
282			status = "disabled";
283			buffer-rx-size = <128>;
284			buffer-tx-size = <128>;
285			shi-cs-wui =<&wui_io53>;
286		};
287
288		espi0: espi@4000a000 {
289			rx-plsize = <64>;
290			tx-plsize = <16>;
291		};
292
293		rctl: reset-controller@400c3100 {
294			compatible = "nuvoton,npcx-rst";
295			reg = <0x400c3100 0x10>;
296			#reset-cells = <1>;
297			status = "disabled";
298		};
299	};
300
301	soc-id {
302		chip-id = <0x07>;
303		revision-reg = <0x00007FFC 1>;
304	};
305
306	booter-variant {
307		hif-type-auto;
308	};
309};
310