1# Nuvoton Cortex-M4 Embedded Controller
2
3# Copyright (c) 2020 Nuvoton Technology Corporation.
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_FAMILY_NPCX
7
8menuconfig NPCX_HEADER
9	bool "The output binary with NPCX binary header"
10	help
11	  On NPCX series chip, the NPCX ROM code loads firmware image from flash
12	  to RAM by the firmware binary header setting. Enable this to invoke
13	  the 'ecst' which generates the NPCX firmware header.
14
15if NPCX_HEADER
16
17config NPCX_IMAGE_OUTPUT_BIN
18	bool "Build npcx binary in BIN format"
19	default y
20	help
21	  Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
22	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
23
24config NPCX_IMAGE_OUTPUT_HEX
25	bool "Build npcx binary in HEX format"
26	depends on NPCX_IMAGE_OUTPUT_BIN
27	help
28	  Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
29	  This is generated from the npcx BIN image.
30	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
31
32config NPCX_HEADER_CHIP
33	string
34	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
35	default "npcx7m7" if SOC_NPCX7M7FC
36	default "npcx9m3" if SOC_NPCX9M3F
37	default "npcx9m6" if SOC_NPCX9M6F
38	default "npcx9m7" if SOC_NPCX9M7F || SOC_NPCX9M7FB
39	default "npcx9mfp" if SOC_NPCX9MFP
40	default "npcx4m3" if SOC_NPCX4M3F
41	default "npcx4m8" if SOC_NPCX4M8F
42
43choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
44	prompt "Clock rate to use for SPI flash"
45	default NPCX_HEADER_SPI_MAX_CLOCK_20
46	help
47	  This selects the max clock rate that will be used for loading firmware
48	  binary from flash to RAM.
49
50config NPCX_HEADER_SPI_MAX_CLOCK_20
51	bool "SPI flash max clock rate of 20 MHz"
52
53config NPCX_HEADER_SPI_MAX_CLOCK_25
54	bool "SPI flash max clock rate of 25 MHz"
55
56config NPCX_HEADER_SPI_MAX_CLOCK_33
57	bool "SPI flash max clock rate of 33 MHz"
58	depends on !SOC_SERIES_NPCX9
59
60config NPCX_HEADER_SPI_MAX_CLOCK_40
61	bool "SPI flash max clock rate of 40 MHz"
62
63config NPCX_HEADER_SPI_MAX_CLOCK_50
64	bool "SPI flash max clock rate of 50 MHz"
65endchoice
66
67config NPCX_HEADER_SPI_MAX_CLOCK
68	int
69	default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
70	default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
71	default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
72	default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
73	default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
74
75choice NPCX_HEADER_SPI_READ_MODE_CHOICE
76	prompt "Reading mode used by the SPI flash"
77	default NPCX_HEADER_SPI_READ_MODE_NORMAL
78	help
79	  This sets the reading mode that can be used by the SPI flash.
80	  Reading modes supported are normal, fast, dual, and quad.
81
82config NPCX_HEADER_SPI_READ_MODE_NORMAL
83	bool "SPI flash operates with normal reading mode"
84
85config NPCX_HEADER_SPI_READ_MODE_FAST
86	bool "SPI flash operates with fast reading mode"
87
88config NPCX_HEADER_SPI_READ_MODE_DUAL
89	bool "SPI flash operates with dual reading mode"
90
91config NPCX_HEADER_SPI_READ_MODE_QUAD
92	bool "SPI flash operates with quad reading mode"
93endchoice
94
95config NPCX_HEADER_SPI_READ_MODE
96	string
97	default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
98	default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
99	default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
100	default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
101
102choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
103	prompt "Core clock to SPI flash clock ratio"
104	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
105	help
106	  This sets the clock ratio (core clock / SPI clock)
107
108config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
109	bool "NPCX SPI clock ratio 1"
110	help
111	  The SPI flash clock has the same frequency as the core clock.
112
113config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
114	bool "NPCX SPI clock ratio 2"
115	help
116	  The core clock frequency is twice the flash clock frequency.
117endchoice
118
119config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
120	int
121	default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
122	default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
123
124config NPCX_HEADER_ENABLE_HEADER_CRC
125	bool "Header crc check"
126	help
127	  When enabled, the header will be verified at boot using a crc
128	  checksum.
129
130config NPCX_HEADER_ENABLE_FIRMWARE_CRC
131	bool "Firmware image crc check"
132	help
133	  When enabled, the firmware image will be verified at boot using a
134	  crc checksum.
135
136choice NPCX_HEADER_FLASH_SIZE_CHOICE
137	prompt "Flash size"
138	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
139						  SOC_SERIES_NPCX9
140	default NPCX_HEADER_FLASH_SIZE_16M
141	help
142	  This sets the SPI flash size.
143
144config NPCX_HEADER_FLASH_SIZE_0P5M_1M
145	bool "SPI flash size 0.5M or 1M Bytes"
146	help
147	  The SPI flash size is 0.5M or 1M Bytes.
148
149config NPCX_HEADER_FLASH_SIZE_2M
150	bool "SPI flash size 2M Bytes"
151	help
152	  The SPI flash size is 2M Bytes.
153
154config NPCX_HEADER_FLASH_SIZE_4M
155	bool "SPI flash size 4M Bytes"
156	help
157	  The SPI flash size is 4M Bytes.
158
159config NPCX_HEADER_FLASH_SIZE_8M
160	bool "SPI flash size 8M Bytes"
161	help
162	  The SPI flash size is 8M Bytes.
163
164config NPCX_HEADER_FLASH_SIZE_16M
165	bool "SPI flash size 16M Bytes"
166	help
167	  The SPI flash size is 16M Bytes.
168endchoice
169
170config NPCX_HEADER_FLASH_SIZE
171	int
172	default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
173	default 2 if NPCX_HEADER_FLASH_SIZE_2M
174	default 4 if NPCX_HEADER_FLASH_SIZE_4M
175	default 8 if NPCX_HEADER_FLASH_SIZE_8M
176	default 16 if NPCX_HEADER_FLASH_SIZE_16M
177
178endif # NPCX_HEADER
179
180config NPCX_PM_TRACE
181	bool "Trace System Power Management in NPCX family"
182	depends on PM
183	help
184	  Internal config to enable runtime power management traces.
185
186endif # SOC_FAMILY_NPCX
187
188# Select SoC Part No. and configuration options
189rsource "*/Kconfig"
190