1/*
2 * Copyright (c) 2021 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* NPCX9 series pinmux mapping table */
8#include "npcx9/npcx9-alts-map.dtsi"
9/* NPCX9 series mapping table between MIWU wui bits and source device */
10#include "npcx9/npcx9-miwus-wui-map.dtsi"
11/* NPCX9 series mapping table between MIWU groups and interrupts */
12#include "npcx9/npcx9-miwus-int-map.dtsi"
13/* NPCX9 series eSPI VW mapping table */
14#include "npcx9/npcx9-espi-vws-map.dtsi"
15/* NPCX9 series low-voltage io controls mapping table */
16#include "npcx9/npcx9-lvol-ctrl-map.dtsi"
17
18/* Device tree declarations of npcx soc family */
19#include "npcx.dtsi"
20
21/ {
22	cpus {
23		cpu0: cpu@0 {
24			cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
25		};
26
27		power-states {
28			suspend_to_idle0: suspend-to-idle0 {
29				compatible = "zephyr,power-state";
30				power-state-name = "suspend-to-idle";
31				substate-id = <0>;
32				min-residency-us = <1000>;
33			};
34
35			suspend_to_idle1: suspend-to-idle1 {
36				compatible = "zephyr,power-state";
37				power-state-name = "suspend-to-idle";
38				substate-id = <1>;
39				min-residency-us = <201000>;
40			};
41		};
42	};
43
44	def-io-conf-list {
45		pinmux = <&alt0_gpio_no_spip
46			   &alt0_gpio_no_fpip
47			   &alt1_no_pwrgd
48			   &alta_no_peci_en
49			   &altd_npsl_in1_sl
50			   &altd_npsl_in2_sl
51			   &altd_psl_in3_sl
52			   &altd_psl_in4_sl
53			   &alt7_no_ksi0_sl
54			   &alt7_no_ksi1_sl
55			   &alt7_no_ksi2_sl
56			   &alt7_no_ksi3_sl
57			   &alt7_no_ksi4_sl
58			   &alt7_no_ksi5_sl
59			   &alt7_no_ksi6_sl
60			   &alt7_no_ksi7_sl
61			   &alt8_no_kso00_sl
62			   &alt8_no_kso01_sl
63			   &alt8_no_kso02_sl
64			   &alt8_no_kso03_sl
65			   &alt8_no_kso04_sl
66			   &alt8_no_kso05_sl
67			   &alt8_no_kso06_sl
68			   &alt8_no_kso07_sl
69			   &alt9_no_kso08_sl
70			   &alt9_no_kso09_sl
71			   &alt9_no_kso10_sl
72			   &alt9_no_kso11_sl
73			   &alt9_no_kso12_sl
74			   &alt9_no_kso13_sl
75			   &alt9_no_kso14_sl
76			   &alt9_no_kso15_sl
77			   &alta_no_kso16_sl
78			   &alta_no_kso17_sl
79			   &altg_psl_gpo_sl>;
80	};
81
82	soc {
83		compatible = "nuvoton,npcx9", "nuvoton,npcx", "simple-bus";
84
85		bbram: bb-ram@400af000 {
86			compatible = "nuvoton,npcx-bbram";
87			reg = <0x400af000 0x80
88			       0x400af100 0x1>;
89			reg-names = "memory", "status";
90		};
91
92		/* Specific soc devices in npcx9 series */
93		itims: timer@400b0000 {
94			compatible = "nuvoton,npcx-itim-timer";
95			reg = <0x400b0000 0x2000
96			       0x400be000 0x2000>;
97			reg-names = "evt_itim", "sys_itim";
98			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
99				  &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
100			interrupts = <28 1>; /* Event timer interrupt */
101		};
102
103		uart1: serial@400e0000 {
104			compatible = "nuvoton,npcx-uart";
105			/* Index 0: UART1 register, Index 1: MDMA1 register */
106			reg = <0x400E0000 0x2000 0x40011100 0x100>;
107			interrupts = <33 3>;
108			/* Index 0: UART1 clock, Index 1: MDMA1 clock */
109			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4
110				  &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>;
111			uart-rx = <&wui_cr_sin1>;
112			status = "disabled";
113		};
114
115		uart2: serial@400e2000 {
116			compatible = "nuvoton,npcx-uart";
117			/* Index 0: UART2 register, Index 1: MDMA2 register */
118			reg = <0x400E2000 0x2000 0x40011200 0x100>;
119			interrupts = <32 3>;
120			/* Index 0: UART2 clock, Index 1: MDMA2 clock */
121			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6
122				  &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 1>;
123			uart-rx = <&wui_cr_sin2>;
124			status = "disabled";
125		};
126
127		uart3: serial@400e4000 {
128			compatible = "nuvoton,npcx-uart";
129			/* Index 0: UART3 register, Index 1: MDMA3 register */
130			reg = <0x400E4000 0x2000 0x40011300 0x100>;
131			interrupts = <38 3>;
132			/* Index 0: UART3 clock, Index 1: MDMA3 clock */
133			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4
134				  &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>;
135			uart-rx = <&wui_cr_sin3>;
136			status = "disabled";
137		};
138
139		uart4: serial@400e6000 {
140			compatible = "nuvoton,npcx-uart";
141			/* Index 0: UART4 register, Index 1: MDMA4 register */
142			reg = <0x400E6000 0x2000 0x40011400 0x100>;
143			interrupts = <39 3>;
144			/* Index 0: UART4 clock, Index 1: MDMA4 clock */
145			clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3
146				  &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>;
147			uart-rx = <&wui_cr_sin4>;
148			status = "disabled";
149		};
150
151		/* Default clock and power settings in npcx9 series */
152		pcc: clock-controller@4000d000 {
153			clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
154			core-prescaler = <6>; /* CORE_CLK runs at 15MHz */
155			apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
156			apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
157			apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
158			apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */
159			ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */
160			pwdwn-ctl-val = <0xfb /* No FIU_PD */
161					 0xff
162					 0x1f /* No GDMA_PD */
163					 0xff
164					 0xfa
165					 0x7f /* No ESPI_PD */
166					 0xff
167					 0x31>;
168		};
169
170		/* Wake-up input source mapping for GPIOs in npcx9 series */
171		gpio0: gpio@40081000 {
172			wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03
173				    &wui_io04 &wui_io05 &wui_io06 &wui_io07>;
174
175			lvol-maps = <&lvol_io00 &lvol_none &lvol_none &lvol_none
176				     &lvol_none &lvol_none &lvol_none &lvol_none>;
177		};
178
179		gpio1: gpio@40083000 {
180			wui-maps = <&wui_io10 &wui_io11 &wui_none &wui_none
181				    &wui_io14 &wui_io15 &wui_io16 &wui_io17>;
182
183			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
184				     &lvol_none &lvol_none &lvol_none &lvol_none>;
185		};
186
187		gpio2: gpio@40085000 {
188			wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23
189				    &wui_io24 &wui_io25 &wui_io26 &wui_io27>;
190
191			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
192				     &lvol_none &lvol_none &lvol_none &lvol_none>;
193		};
194
195		gpio3: gpio@40087000 {
196			wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33
197				    &wui_io34 &wui_none &wui_io36 &wui_io37>;
198
199			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33
200				     &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>;
201		};
202
203		gpio4: gpio@40089000 {
204			wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43
205				    &wui_io44 &wui_io45 &wui_io46 &wui_io47>;
206
207			lvol-maps = <&lvol_io40 &lvol_none &lvol_none &lvol_none
208				     &lvol_none &lvol_none &lvol_none &lvol_none>;
209		};
210
211		gpio5: gpio@4008b000 {
212			wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53
213				    &wui_io54 &wui_io55 &wui_io56 &wui_io57>;
214
215			lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none
216				     &lvol_none &lvol_none &lvol_none &lvol_none>;
217		};
218
219		gpio6: gpio@4008d000 {
220			wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63
221				    &wui_io64 &wui_none &wui_io66 &wui_io67>;
222
223			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
224				     &lvol_io64 &lvol_none &lvol_io66 &lvol_none>;
225		};
226
227		gpio7: gpio@4008f000 {
228			wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73
229				    &wui_io74 &wui_io75 &wui_io76 &wui_none>;
230
231			lvol-maps = <&lvol_none &lvol_none &lvol_io72 &lvol_io73
232				     &lvol_io74 &lvol_io75 &lvol_none &lvol_none>;
233		};
234
235		gpio8: gpio@40091000 {
236			wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83
237				    &wui_none &wui_none &wui_none &wui_io87>;
238
239			lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_none
240				     &lvol_none &lvol_none &lvol_none &lvol_io87>;
241		};
242
243		gpio9: gpio@40093000 {
244			wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93
245				    &wui_io94 &wui_io95 &wui_io96 &wui_io97>;
246
247			lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none
248				     &lvol_none &lvol_none &lvol_none &lvol_none>;
249		};
250
251		gpioa: gpio@40095000 {
252			wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3
253				    &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>;
254
255			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none
256				     &lvol_none &lvol_none &lvol_none &lvol_none>;
257		};
258
259		gpiob: gpio@40097000 {
260			wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3
261				    &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>;
262
263			lvol-maps = <&lvol_none &lvol_none &lvol_iob2 &lvol_iob3
264				     &lvol_iob4 &lvol_iob5 &lvol_none &lvol_none>;
265		};
266
267		gpioc: gpio@40099000 {
268			wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3
269				    &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>;
270
271			lvol-maps = <&lvol_none &lvol_ioc1 &lvol_ioc2 &lvol_none
272				     &lvol_none &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>;
273		};
274
275		gpiod: gpio@4009b000 {
276			wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3
277				    &wui_iod4 &wui_iod5 &wui_none &wui_none>;
278
279			lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_none &lvol_none
280				     &lvol_none &lvol_none &lvol_none &lvol_none>;
281		};
282
283		gpioe: gpio@4009d000 {
284			wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3
285				    &wui_ioe4 &wui_ioe5 &wui_none &wui_none>;
286
287			lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_ioe3
288				     &lvol_ioe4 &lvol_none &lvol_none &lvol_none>;
289		};
290
291		gpiof: gpio@4009f000 {
292			wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3
293				    &wui_iof4 &wui_iof5 &wui_none &wui_none>;
294
295			lvol-maps = <&lvol_none &lvol_none &lvol_iof2 &lvol_iof3
296				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
297		};
298
299		/* ADC0 comparator configuration in npcx9 series */
300		adc0: adc@400d1000 {
301			channel-count = <12>;
302			threshold-count = <6>;
303		};
304
305		/* FIU0 configuration in npcx9 series */
306		qspi_fiu0: quadspi@40020000 {
307			clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
308		};
309
310		sha0: sha@13c {
311			compatible = "nuvoton,npcx-sha";
312			reg = <0x13c 0x3c>;
313			context-buffer-size = <212>;
314			status = "disabled";
315		};
316
317		shi0: shi@4000f000 {
318			compatible = "nuvoton,npcx-shi";
319			reg = <0x4000f000 0x120>;
320			interrupts = <18 1>;
321			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
322			status = "disabled";
323			buffer-rx-size = <128>;
324			buffer-tx-size = <128>;
325			shi-cs-wui =<&wui_io53>;
326		};
327
328		espi0: espi@4000a000 {
329			rx-plsize = <64>;
330			tx-plsize = <16>;
331		};
332
333		rctl: reset-controller@400c3100 {
334			compatible = "nuvoton,npcx-rst";
335			reg = <0x400c3100 0x14>;
336			#reset-cells = <1>;
337			status = "disabled";
338		};
339	};
340
341	soc-id {
342		chip-id = <0x09>;
343		revision-reg = <0x0000FFFC 4>;
344	};
345};
346