1# Copyright (c) 2022 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
6  nodes can be autogenerated using the MCUXpresso config tools combined with
7  the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
8  fields in a group select the pins to be configured, and the remaining
9  devicetree properties set configuration values for those pins
10  for example, here is an group configuring UART2 pins:
11
12  group0 {
13      pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx,
14          &iomuxc_uart2_txd_uart_tx_uart2_tx>;
15      drive-strength = "40-ohm";
16      slew-rate = "slow";
17  };
18
19  This will select UART2_RXD as UART2 rx, and UART2_TXD as UART2 tx.
20  Both pins will be configured with a slow slew rate, and maximum drive
21  strength.
22  Note that the soc level iomuxc dts file can be examined to find the possible
23  pinmux options. Here are the affects of each property on the
24  IOMUXC SW_PAD_CTL register:
25  nxp,lvttl: LVTTL=1
26  input-schmitt-enable: HYS=1
27  bias-pull-up: PUE=1
28  drive-open-drain: ODE=1
29  slew-rate: SRE=<enum_idx>
30  drive-strength: DSE=<enum_idx>
31  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
32
33  If only required properties are supplied, the pin will have the following
34  configuration:
35  LVTLL=0,
36  HYS=0,
37  PUE=0,
38  ODE=0,
39  SRE=<slew-rate>,
40  DSE=<drive-strength>,
41  SION=0,
42
43
44compatible: "nxp,imx8m-pinctrl"
45
46include: base.yaml
47
48child-binding:
49  description: iMX pin controller pin group
50  child-binding:
51    description: |
52      iMX pin controller pin configuration node.
53
54    include:
55      - name: pincfg-node.yaml
56        property-allowlist:
57          - input-schmitt-enable
58          - drive-open-drain
59          - input-enable
60          - bias-pull-up
61          - bias-pull-down
62
63    properties:
64      pinmux:
65        required: true
66        type: phandles
67        description: |
68          Pin mux selections for this group. See the soc level iomuxc DTSI file
69          for a defined list of these options.
70      drive-strength:
71        required: true
72        type: string
73        enum:
74          - "disabled"
75          - "255-ohm"
76          - "105-ohm"
77          - "75-ohm"
78          - "85-ohm"
79          - "65-ohm"
80          - "45-ohm"
81          - "40-ohm"
82        description: |
83          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
84          the drive strength is expressed as a output impedance at a given voltage,
85          but maximum current values can be calculated from these impedances
86          for a specific load impedance.
87          000 HI-Z — Output driver is disabled (Hi-Z State)
88          001 255_OHM — 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
89          010 105_OHM — 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
90          011 75_OHM — 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
91          100 85_OHM — 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
92          101 65_OHM — 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
93          110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
94          111 40_OHM — 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
95      slew-rate:
96        required: true
97        type: string
98        enum:
99          - "slow"
100          - "medium"
101          - "fast"
102          - "max"
103        description: |
104          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
105          00 SLOW — Slow Frequency Slew Rate (50Mhz)
106          01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107          10 FAST — Fast Frequency Slew Rate (150Mhz)
108          11 MAX — Max Frequency Slew Rate (200Mhz)
109      nxp,lvttl:
110        type: boolean
111        description: |
112          Enable LVTTL input. Sets LVTTL field in IOMUXC peripheral
113