# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0

description: |
  The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These
  nodes can be autogenerated using the MCUXpresso config tools combined with
  the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
  fields in a group select the pins to be configured, and the remaining
  devicetree properties set configuration values for those pins
  for example, here is an group configuring UART2 pins:

  group0 {
      pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx,
          &iomuxc_uart2_txd_uart_tx_uart2_tx>;
      drive-strength = "40-ohm";
      slew-rate = "slow";
  };

  This will select UART2_RXD as UART2 rx, and UART2_TXD as UART2 tx.
  Both pins will be configured with a slow slew rate, and maximum drive
  strength.
  Note that the soc level iomuxc dts file can be examined to find the possible
  pinmux options. Here are the affects of each property on the
  IOMUXC SW_PAD_CTL register:
  nxp,lvttl: LVTTL=1
  input-schmitt-enable: HYS=1
  bias-pull-up: PUE=1
  drive-open-drain: ODE=1
  slew-rate: SRE=<enum_idx>
  drive-strength: DSE=<enum_idx>
  input-enable: SION=1 (in SW_MUX_CTL_PAD register)

  If only required properties are supplied, the pin will have the following
  configuration:
  LVTLL=0,
  HYS=0,
  PUE=0,
  ODE=0,
  SRE=<slew-rate>,
  DSE=<drive-strength>,
  SION=0,


compatible: "nxp,imx8m-pinctrl"

include: base.yaml

child-binding:
  description: iMX pin controller pin group
  child-binding:
    description: |
      iMX pin controller pin configuration node.

    include:
      - name: pincfg-node.yaml
        property-allowlist:
          - input-schmitt-enable
          - drive-open-drain
          - input-enable
          - bias-pull-up
          - bias-pull-down

    properties:
      pinmux:
        required: true
        type: phandles
        description: |
          Pin mux selections for this group. See the soc level iomuxc DTSI file
          for a defined list of these options.
      drive-strength:
        required: true
        type: string
        enum:
          - "disabled"
          - "255-ohm"
          - "105-ohm"
          - "75-ohm"
          - "85-ohm"
          - "65-ohm"
          - "45-ohm"
          - "40-ohm"
        description: |
          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
          the drive strength is expressed as a output impedance at a given voltage,
          but maximum current values can be calculated from these impedances
          for a specific load impedance.
          000 HI-Z — Output driver is disabled (Hi-Z State)
          001 255_OHM — 255 Ohm @3.3V, 240 Ohm @2.5V, 230 Ohm @1.8V, 265 Ohm @1.2V
          010 105_OHM — 105 Ohm @3.3V, 100 Ohm @2.5V, 85 Ohm @1.8V, 110 Ohm @1.2V
          011 75_OHM — 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
          100 85_OHM — 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
          101 65_OHM — 65 Ohm @3.3V, 60 Ohm @2.5V, 55 Ohm @1.8V, 65 Ohm @1.2V
          110 45_OHM — 45 Ohm @3.3V, 45 Ohm @2.5V, 40 Ohm @1.8V, 50 Ohm @1.2V
          111 40_OHM — 40 Ohm @3.3V, 40 Ohm @2.5V, 33 Ohm @1.8V, 40 Ohm @1.2V
      slew-rate:
        required: true
        type: string
        enum:
          - "slow"
          - "medium"
          - "fast"
          - "max"
        description: |
          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
          00 SLOW — Slow Frequency Slew Rate (50Mhz)
          01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
          10 FAST — Fast Frequency Slew Rate (150Mhz)
          11 MAX — Max Frequency Slew Rate (200Mhz)
      nxp,lvttl:
        type: boolean
        description: |
          Enable LVTTL input. Sets LVTTL field in IOMUXC peripheral
