1# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
5
6config ESP_SPIRAM
7	bool "Support for external, SPI-connected RAM"
8	default n if MCUBOOT
9	default n if ESP32_USE_UNSUPPORTED_REVISION && SOC_SERIES_ESP32
10	select SHARED_MULTI_HEAP
11	help
12	  This enables support for an external SPI RAM chip, connected in
13	  parallel with the main SPI flash chip.
14
15menu "SPI RAM config"
16	depends on ESP_SPIRAM
17
18config ESP_HEAP_SEARCH_ALL_REGIONS
19	bool "Search for all available heap regions"
20	default y
21	help
22	  This configuration enables searching all available heap
23	  regions. If the region of desired capability is exhausted,
24	  memory will be allocated from other available region.
25
26config ESP_SPIRAM_HEAP_SIZE
27	int "Size of SPIRAM heap"
28	default 262134 if SYS_HEAP_SMALL_ONLY
29	default 1048576 if !SYS_HEAP_SMALL_ONLY
30	help
31	  Specify size of SPIRAM heap.
32
33config ESP_SPIRAM_MEMTEST
34	bool "Run memory test on SPI RAM initialization"
35	default y
36	help
37	  Runs a memory test on initialization. Disable this for faster startup.
38
39choice SPIRAM_MODE
40	prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
41	default SPIRAM_MODE_QUAD
42
43	config SPIRAM_MODE_QUAD
44		bool "Quad Mode PSRAM"
45
46	config SPIRAM_MODE_OCT
47		bool "Octal Mode PSRAM"
48		depends on SOC_SERIES_ESP32S3
49
50endchoice # SPIRAM_MODE
51
52choice SPIRAM_TYPE
53	prompt "Type of SPI RAM chip in use"
54	default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
55	default SPIRAM_TYPE_ESPPSRAM64
56
57config SPIRAM_TYPE_ESPPSRAM16
58	bool "ESP-PSRAM16 or APS1604"
59	depends on SPIRAM_MODE_QUAD
60
61config SPIRAM_TYPE_ESPPSRAM32
62	bool "ESP-PSRAM32 or IS25WP032"
63	depends on SPIRAM_MODE_QUAD
64
65config SPIRAM_TYPE_ESPPSRAM64
66	bool "ESP-PSRAM64, LY68L6400 or APS6408"
67
68endchoice # SPIRAM_TYPE
69
70config ESP_SPIRAM_SIZE
71	int "Size of SPIRAM part"
72	default 2097152 if SPIRAM_TYPE_ESPPSRAM16
73	default 4194304 if SPIRAM_TYPE_ESPPSRAM32
74	default 8388608 if SPIRAM_TYPE_ESPPSRAM64
75	help
76	  Specify size of SPIRAM part.
77	  NOTE: If SPIRAM size is greater than 4MB, only
78	  lower 4MB can be allocated using k_malloc().
79
80choice SPIRAM_SPEED
81	prompt "Set RAM clock speed"
82	default SPIRAM_SPEED_40M
83	help
84	  Select the speed for the SPI RAM chip.
85
86config SPIRAM_SPEED_20M
87	bool "20MHz clock speed"
88	depends on SOC_SERIES_ESP32S2
89
90config SPIRAM_SPEED_26M
91	bool "26MHz clock speed"
92	depends on SOC_SERIES_ESP32S2
93
94config SPIRAM_SPEED_40M
95	bool "40MHz clock speed"
96
97config SPIRAM_SPEED_80M
98	bool "80MHz clock speed"
99	depends on ESPTOOLPY_FLASHFREQ_80M
100
101config SPIRAM_SPEED_120M
102	bool "120MHz clock speed"
103	depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
104
105endchoice # SPIRAM_SPEED
106
107config SPIRAM_SPEED
108	int
109	default 120 if SPIRAM_SPEED_120M
110	default 80 if SPIRAM_SPEED_80M
111	default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
112
113config SPIRAM_CLK_IO
114	int
115	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
116	default 30
117
118config SPIRAM_CS_IO
119	int
120	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
121	default 26
122
123config SPIRAM_FETCH_INSTRUCTIONS
124	bool "Move Instructions in Flash to PSRAM"
125	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
126	default n
127	help
128	  If enabled, instructions in flash will be moved into PSRAM on startup.
129	  If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
130	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
131	  for more details).
132
133config SPIRAM_RODATA
134	bool "Move Read-Only Data in Flash to PSRAM"
135	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
136	default n
137	help
138	  If enabled, rodata in flash will be moved into PSRAM on startup.
139	  If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation
140	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
141	  for more details).
142
143config SPIRAM_ECC_ENABLE
144	bool "Allow enabling SPI RAM ECC"
145	default n
146	depends on SPIRAM_MODE_OCT && SOC_SERIES_ESP32S3
147	help
148	  Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149	  If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
150
151if SOC_SERIES_ESP32
152
153menu "PSRAM clock and cs IO for ESP32-DOWD"
154
155config D0WD_PSRAM_CLK_IO
156	int "PSRAM CLK IO number"
157	range 0 33
158	default 17
159	help
160	  The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
161	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
162
163config D0WD_PSRAM_CS_IO
164	int "PSRAM CS IO number"
165	range 0 33
166	default 16
167	help
168	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
169	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
170
171endmenu # PSRAM clock and cs IO for ESP32-DOWD
172
173menu "PSRAM clock and cs IO for ESP32-D2WD"
174
175config D2WD_PSRAM_CLK_IO
176	int "PSRAM CLK IO number"
177	range 0 33
178	default 9
179	help
180	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
181	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
182
183config D2WD_PSRAM_CS_IO
184	int "PSRAM CS IO number"
185	range 0 33
186	default 10
187	help
188	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
189	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
190
191endmenu # PSRAM clock and cs IO for ESP32-D2WD
192
193menu "PSRAM clock and cs IO for ESP32-PICO"
194
195config PICO_PSRAM_CS_IO
196	int "PSRAM CS IO number"
197	range 0 33
198	default 10
199	help
200	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
201
202	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
203	  IO For the reference hardware design, please refer to
204	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
205
206endmenu # PSRAM clock and cs IO for ESP32-PICO
207
208config SPIRAM_CUSTOM_SPIWP_SD3_PIN
209	bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
210	depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
211	default n
212	help
213	  This setting is only used if the SPI flash pins have been overridden by setting the eFuses
214	  SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
215
216	  When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
217	  ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
218	  mode, so a WP pin setting is necessary.
219
220	  If this config item is set to N (default), the correct WP pin will be automatically used for any
221	  Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
222	  to Y and specify the GPIO number connected to the WP pin.
223
224	  When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
225	  configured in the bootloader.
226
227config SPIRAM_SPIWP_SD3_PIN
228	int "Custom SPI PSRAM WP(SD3) Pin"
229	depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN
230	range 0 33
231	default 7
232	help
233	  The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
234
235	  If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
236	  value to the GPIO number of the SPIRAM WP pin.
237
238endif # SOC_SERIES_ESP32
239
240endmenu # ESP_SPIRAM
241
242endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
243