1# Copyright (c) 2024 Nuvoton Technology Corporation. 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 Nuvoton I3C controller 6 7 Representation: 8 9 /* If CONFIG_I3C_NPCX is enabled, the suggested clock configuration is as follows: */ 10 &pcc { 11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */ 12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */ 13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ 14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ 15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ 16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */ 17 }; 18 19 &rst { 20 status = "okay"; 21 }; 22 23 &i3c0 { 24 status = "okay"; 25 26 /* I3C clock frequency suggestion = <PP_SCL, OD_SCL> */ 27 * Full speed = <12500000, 4170000> 28 * Normal speed = <7500000, 1500000> 29 */ 30 i3c-scl-hz = <12500000>; 31 i3c-od-scl-hz = <4170000>; 32 33 bcr = <0x67>; /* Set for controller mode */ 34 }; 35 36compatible: "nuvoton,npcx-i3c" 37 38include: [i3c-controller.yaml, pinctrl-device.yaml, reset-device.yaml] 39 40properties: 41 reg: 42 required: true 43 44 interrupts: 45 required: true 46 47 resets: 48 required: true 49 50 i3c-od-scl-hz: 51 type: int 52 description: | 53 Open Drain Frequency for the I3C controller. When undefined, use 54 the controller default or as specified by the I3C specification. 55 56 instance-id: 57 required: true 58 type: int 59 description: | 60 Instance ID of the device, used to specify port number. 61 Bit[7:4] module id. 62 Bit[3:0] port id. 63 64 secondary: 65 type: boolean 66 description: Initialized as a secondary controller. 67 68 static-address: 69 type: int 70 description: | 71 Target static address. 72 73 tgt-pid: 74 type: array 75 description: | 76 Target 48-bit Provisioned ID. 77 array[0]: PID[47:33] MIPI manufacturer ID. 78 PID[32] ID type selector (i'b1 ramdom value, 1'b0 vendor fixed). 79 array[1]: PID[31:0] Random value or vendor fixed value. 80 81 bcr: 82 required: true 83 type: int 84 description: | 85 Bus Characteristics Register, used for bus enumeration with ENTDAA and 86 determine device role and capabilities of the device on the bus. 87 88 dcr: 89 type: int 90 description: | 91 Device Characteristics Register, used for bus enumeration with ENTDAA. 92 93 maximum-write: 94 type: int 95 default: 4095 96 description: | 97 Maximum number of bytes that I3C controller may write to I3C target per message. 98 Range: 8 to 4095. 99 100 maximum-read: 101 type: int 102 default: 4095 103 description: | 104 Maximum number of bytes that I3C controller may read from to I3C target per message. 105 Range: 8 to 4095. 106