1/* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/* npcx4 series pinmux mapping table */ 8#include "npcx4/npcx4-alts-map.dtsi" 9/* npcx4 series mapping table between MIWU wui bits and source device */ 10#include "npcx4/npcx4-miwus-wui-map.dtsi" 11/* npcx4 series mapping table between MIWU groups and interrupts */ 12#include "npcx4/npcx4-miwus-int-map.dtsi" 13/* npcx4 series eSPI VW mapping table */ 14#include "npcx4/npcx4-espi-vws-map.dtsi" 15/* npcx4 series low-voltage io controls mapping table */ 16#include "npcx4/npcx4-lvol-ctrl-map.dtsi" 17/* npcx4 series reset mapping table */ 18#include "zephyr/dt-bindings/reset/npcx4_reset.h" 19 20/* Device tree declarations of npcx soc family */ 21#include "npcx.dtsi" 22 23/ { 24 cpus { 25 cpu0: cpu@0 { 26 cpu-power-states = <&suspend_to_idle0>; 27 }; 28 29 power-states { 30 suspend_to_idle0: suspend-to-idle0 { 31 compatible = "zephyr,power-state"; 32 power-state-name = "suspend-to-idle"; 33 substate-id = <0>; 34 min-residency-us = <1000>; 35 }; 36 }; 37 }; 38 39 def-io-conf-list { 40 pinmux = <&alt0_gpio_no_spip 41 &alt0_gpio_no_fpip 42 &alt1_no_pwrgd 43 &alt7_no_ksi0_sl 44 &alt7_no_ksi1_sl 45 &alt7_no_ksi2_sl 46 &alt7_no_ksi3_sl 47 &alt7_no_ksi4_sl 48 &alt7_no_ksi5_sl 49 &alt7_no_ksi6_sl 50 &alt7_no_ksi7_sl 51 &alt8_no_kso00_sl 52 &alt8_no_kso01_sl 53 &alt8_no_kso02_sl 54 &alt8_no_kso03_sl 55 &alt8_no_kso04_sl 56 &alt8_no_kso05_sl 57 &alt8_no_kso06_sl 58 &alt8_no_kso07_sl 59 &alt9_no_kso08_sl 60 &alt9_no_kso09_sl 61 &alt9_no_kso10_sl 62 &alt9_no_kso11_sl 63 &alt9_no_kso12_sl 64 &alt9_no_kso13_sl 65 &alt9_no_kso14_sl 66 &alt9_no_kso15_sl 67 &alta_no_kso16_sl 68 &alta_no_kso17_sl 69 &alta_no_peci_en 70 &altc_gpio97_sl_inv 71 &altd_npsl_in1_sl 72 &altd_npsl_in2_sl 73 &altd_psl_in3_sl 74 &altd_psl_in4_sl 75 &altg_psl_gpo_sl>; 76 }; 77 78 soc { 79 compatible = "nuvoton,npcx4", "nuvoton,npcx", "simple-bus"; 80 81 /* 82 * Writing to BKUP_STS register might affect the value stored in 83 * the first byte of the BBRAM. 84 * Workaround it by not using the first byte of the BBRAM. 85 * (See npcx4 Errata 2.27) 86 */ 87 bbram: bb-ram@400af001 { 88 compatible = "nuvoton,npcx-bbram"; 89 reg = <0x400af001 0x7F 90 0x400af100 0x1>; 91 reg-names = "memory", "status"; 92 }; 93 94 /* Specific soc devices in npcx4 series */ 95 itims: timer@400b0000 { 96 compatible = "nuvoton,npcx-itim-timer"; 97 reg = <0x400b0000 0x2000 98 0x400be000 0x2000>; 99 reg-names = "evt_itim", "sys_itim"; 100 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 101 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; 102 interrupts = <28 1>; /* Event timer interrupt */ 103 }; 104 105 uart1: serial@400e0000 { 106 compatible = "nuvoton,npcx-uart"; 107 /* Index 0: UART1 register, Index 1: MDMA1 register */ 108 reg = <0x400E0000 0x2000 0x40011100 0x100>; 109 interrupts = <33 3>; 110 /* Index 0: UART1 clock, Index 1: MDMA1 clock */ 111 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4 112 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>; 113 uart-rx = <&wui_cr_sin1>; 114 status = "disabled"; 115 }; 116 117 uart2: serial@400e2000 { 118 compatible = "nuvoton,npcx-uart"; 119 /* Index 0: UART2 register, Index 1: MDMA2 register */ 120 reg = <0x400E2000 0x2000 0x40011200 0x100>; 121 interrupts = <32 3>; 122 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>; 123 uart-rx = <&wui_cr_sin2>; 124 status = "disabled"; 125 }; 126 127 uart3: serial@400e4000 { 128 compatible = "nuvoton,npcx-uart"; 129 /* Index 0: UART3 register, Index 1: MDMA3 register */ 130 reg = <0x400E4000 0x2000 0x40011300 0x100>; 131 interrupts = <38 3>; 132 /* Index 0: UART3 clock, Index 1: MDMA3 clock */ 133 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4 134 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>; 135 uart-rx = <&wui_cr_sin3>; 136 status = "disabled"; 137 }; 138 139 uart4: serial@400e6000 { 140 compatible = "nuvoton,npcx-uart"; 141 /* Index 0: UART4 register, Index 1: MDMA4 register */ 142 reg = <0x400E6000 0x2000 0x40011400 0x100>; 143 interrupts = <39 3>; 144 /* Index 0: UART4 clock, Index 1: MDMA4 clock */ 145 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3 146 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>; 147 uart-rx = <&wui_cr_sin4>; 148 status = "disabled"; 149 }; 150 151 /* Default clock and power settings in npcx4 series */ 152 pcc: clock-controller@4000d000 { 153 clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */ 154 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */ 155 apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */ 156 apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */ 157 apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */ 158 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */ 159 ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */ 160 pwdwn-ctl-val = <0xfb 161 0xff 162 0x1f /* No GDMA1_PD/GDMA2_PD */ 163 0xff 164 0xfa 165 0x7f /* No ESPI_PD */ 166 0xff 167 0xcf>; /* No FIU_PD */ 168 }; 169 170 /* Wake-up input source mapping for GPIOs in npcx4 series */ 171 gpio0: gpio@40081000 { 172 wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03 173 &wui_io04 &wui_io05 &wui_io06 &wui_io07>; 174 175 lvol-maps = <&lvol_io00 &lvol_io01 &lvol_io02 &lvol_io03 176 &lvol_io04 &lvol_io05 &lvol_io06 &lvol_io07>; 177 }; 178 179 gpio1: gpio@40083000 { 180 wui-maps = <&wui_io10 &wui_io11 &wui_io12 &wui_io13 181 &wui_io14 &wui_io15 &wui_io16 &wui_io17>; 182 183 lvol-maps = <&lvol_io10 &lvol_io11 &lvol_none &lvol_io13 184 &lvol_io14 &lvol_io15 &lvol_io16 &lvol_io17>; 185 }; 186 187 gpio2: gpio@40085000 { 188 wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23 189 &wui_io24 &wui_io25 &wui_io26 &wui_io27>; 190 191 lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23 192 &lvol_none &lvol_none &lvol_none &lvol_none>; 193 }; 194 195 gpio3: gpio@40087000 { 196 wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33 197 &wui_io34 &wui_none &wui_io36 &wui_io37>; 198 199 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33 200 &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>; 201 }; 202 203 gpio4: gpio@40089000 { 204 wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43 205 &wui_io44 &wui_io45 &wui_io46 &wui_io47>; 206 207 lvol-maps = <&lvol_io40 &lvol_io41 &lvol_io42 &lvol_io43 208 &lvol_io44 &lvol_io45 &lvol_none &lvol_none>; 209 }; 210 211 gpio5: gpio@4008b000 { 212 wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53 213 &wui_io54 &wui_io55 &wui_io56 &wui_io57>; 214 215 lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none 216 &lvol_none &lvol_none &lvol_none &lvol_none>; 217 }; 218 219 gpio6: gpio@4008d000 { 220 wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63 221 &wui_io64 &wui_none &wui_io66 &wui_io67>; 222 223 lvol-maps = <&lvol_io60 &lvol_io61 &lvol_io62 &lvol_io63 224 &lvol_io64 &lvol_none &lvol_io66 &lvol_io67>; 225 }; 226 227 gpio7: gpio@4008f000 { 228 wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73 229 &wui_io74 &wui_io75 &wui_io76 &wui_none>; 230 231 lvol-maps = <&lvol_io70 &lvol_none &lvol_io72 &lvol_io73 232 &lvol_io74 &lvol_io75 &lvol_io76 &lvol_none>; 233 }; 234 235 gpio8: gpio@40091000 { 236 wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 237 &wui_none &wui_none &wui_none &wui_io87>; 238 239 lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_io83 240 &lvol_none &lvol_none &lvol_none &lvol_io87>; 241 }; 242 243 gpio9: gpio@40093000 { 244 wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93 245 &wui_io94 &wui_io95 &wui_io96 &wui_io97>; 246 247 lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none 248 &lvol_none &lvol_none &lvol_none &lvol_none>; 249 }; 250 251 gpioa: gpio@40095000 { 252 wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 253 &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; 254 255 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none 256 &lvol_none &lvol_none &lvol_none &lvol_none>; 257 }; 258 259 gpiob: gpio@40097000 { 260 wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3 261 &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>; 262 263 lvol-maps = <&lvol_none &lvol_iob1 &lvol_iob2 &lvol_iob3 264 &lvol_iob4 &lvol_iob5 &lvol_iob6 &lvol_iob7>; 265 }; 266 267 gpioc: gpio@40099000 { 268 wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3 269 &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>; 270 271 lvol-maps = <&lvol_ioc0 &lvol_ioc1 &lvol_ioc2 &lvol_ioc3 272 &lvol_ioc4 &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>; 273 }; 274 275 gpiod: gpio@4009b000 { 276 wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3 277 &wui_iod4 &wui_iod5 &wui_iod6 &wui_none>; 278 279 lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_iod2 &lvol_iod3 280 &lvol_iod4 &lvol_iod5 &lvol_iod6 &lvol_none>; 281 }; 282 283 gpioe: gpio@4009d000 { 284 wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3 285 &wui_ioe4 &wui_ioe5 &wui_none &wui_ioe7>; 286 287 lvol-maps = <&lvol_ioe0 &lvol_ioe1 &lvol_ioe2 &lvol_ioe3 288 &lvol_ioe4 &lvol_ioe5 &lvol_none &lvol_ioe7>; 289 }; 290 291 gpiof: gpio@4009f000 { 292 wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3 293 &wui_iof4 &wui_iof5 &wui_none &wui_none>; 294 295 lvol-maps = <&lvol_iof0 &lvol_iof1 &lvol_iof2 &lvol_iof3 296 &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>; 297 }; 298 299 /* ADC0 comparator configuration in npcx4 series */ 300 adc0: adc@400d1000 { 301 channel-count = <26>; 302 threshold-count = <6>; 303 }; 304 305 /* ADC1 which reference voltage is AVCC */ 306 adc1: adc@400d5000 { 307 compatible = "nuvoton,npcx-adc"; 308 #io-channel-cells = <1>; 309 reg = <0x400d5000 0x2000>; 310 interrupts = <22 3>; 311 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>; 312 vref-mv = <3300>; 313 channel-count = <26>; 314 threshold-count = <6>; 315 status = "disabled"; 316 }; 317 318 /* FIU0 configuration in npcx4 series */ 319 qspi_fiu0: quadspi@40020000 { 320 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 5>; 321 }; 322 323 /* FIU1 configuration in npcx4 series */ 324 qspi_fiu1: quadspi@40021000 { 325 compatible = "nuvoton,npcx-fiu-qspi"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 reg = <0x40021000 0x1000>; 329 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 6>; 330 }; 331 332 sha0: sha@148 { 333 compatible = "nuvoton,npcx-sha"; 334 reg = <0x148 0x4c>; 335 context-buffer-size = <240>; 336 status = "disabled"; 337 }; 338 339 shi0: shi@4000f000 { 340 compatible = "nuvoton,npcx-shi-enhanced"; 341 reg = <0x4000f000 0x120>; 342 interrupts = <18 1>; 343 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; 344 status = "disabled"; 345 buffer-rx-size = <128>; 346 buffer-tx-size = <128>; 347 shi-cs-wui =<&wui_io53>; 348 }; 349 350 espi0: espi@4000a000 { 351 rx-plsize = <64>; 352 tx-plsize = <64>; 353 354 espi_taf: espitaf@4000a000 { 355 compatible = "nuvoton,npcx-espi-taf"; 356 reg = <0x4000a000 0x2000>; 357 status = "disabled"; 358 }; 359 }; 360 361 rctl: reset-controller@400c3100 { 362 compatible = "nuvoton,npcx-rst"; 363 reg = <0x400c3100 0x14>; 364 #reset-cells = <1>; 365 status = "disabled"; 366 }; 367 368 i3c0: i3c@400f0000 { 369 compatible = "nuvoton,npcx-i3c"; 370 371 /* reg[0]: I3C_1 register, reg[1]: MDMA5 register */ 372 reg-names = "i3c1", "mdma5"; 373 reg = <0x400f0000 0x2000>, 374 <0x40011500 0x100>; 375 376 interrupts = <29 3>; 377 378 /* Reset controller */ 379 resets = <&rctl NPCX_RESET_I3C_1>; 380 381 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 382 /* clk[2]: MDMA5 */ 383 clock-names = "mclkd", "apb4", "mdma5"; 384 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 0>, 385 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 386 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 4>; 387 388 status = "disabled"; 389 #address-cells = <3>; 390 #size-cells = <0>; 391 instance-id = <0x00>; 392 }; 393 394 i3c1: i3c@400f2000 { 395 compatible = "nuvoton,npcx-i3c"; 396 397 /* reg[0]: I3C_2 register, reg[1]: MDMA6 register */ 398 reg-names = "i3c2", "mdma6"; 399 reg = <0x400f2000 0x2000>, 400 <0x40011600 0x100>; 401 402 interrupts = <66 3>; 403 404 /* Reset controller */ 405 resets = <&rctl NPCX_RESET_I3C_2>; 406 407 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 408 /* clk[2]: MDMA6 */ 409 clock-names = "mclkd", "apb4", "mdma6"; 410 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 2>, 411 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 412 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 5>; 413 414 status = "disabled"; 415 #address-cells = <3>; 416 #size-cells = <0>; 417 instance-id = <0x10>; 418 }; 419 420 i3c2: i3c@400f4000 { 421 compatible = "nuvoton,npcx-i3c"; 422 423 /* reg[0]: I3C_3 register, reg[1]: MDMA7 register */ 424 reg-names = "i3c1", "mdma7"; 425 reg = <0x400f4000 0x2000>, 426 <0x40011700 0x100>; 427 428 interrupts = <67 3>; 429 430 /* Reset controller */ 431 resets = <&rctl NPCX_RESET_I3C_3>; 432 433 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 434 /* clk[2]: MDMA7 */ 435 clock-names = "mclkd", "apb4", "mdma7"; 436 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 3>, 437 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 438 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 6>; 439 440 status = "disabled"; 441 #address-cells = <3>; 442 #size-cells = <0>; 443 instance-id = <0x20>; 444 }; 445 }; 446 447 soc-if { 448 i2c4_0: io_i2c_ctrl4_port0 { 449 compatible = "nuvoton,npcx-i2c-port"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 port = <0x40>; 453 controller = <&i2c_ctrl4>; 454 status = "disabled"; 455 }; 456 457 i2c7_1: io_i2c_ctrl7_port1 { 458 compatible = "nuvoton,npcx-i2c-port"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 port = <0x71>; 462 controller = <&i2c_ctrl7>; 463 status = "disabled"; 464 }; 465 }; 466 467 soc-id { 468 family-id = <0x23>; 469 chip-id = <0x0a>; 470 revision-reg = <0x0000FFFC 4>; 471 }; 472}; 473
