/* * Copyright (c) 2023 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ /* npcx4 series pinmux mapping table */ #include "npcx4/npcx4-alts-map.dtsi" /* npcx4 series mapping table between MIWU wui bits and source device */ #include "npcx4/npcx4-miwus-wui-map.dtsi" /* npcx4 series mapping table between MIWU groups and interrupts */ #include "npcx4/npcx4-miwus-int-map.dtsi" /* npcx4 series eSPI VW mapping table */ #include "npcx4/npcx4-espi-vws-map.dtsi" /* npcx4 series low-voltage io controls mapping table */ #include "npcx4/npcx4-lvol-ctrl-map.dtsi" /* npcx4 series reset mapping table */ #include "zephyr/dt-bindings/reset/npcx4_reset.h" /* Device tree declarations of npcx soc family */ #include "npcx.dtsi" / { cpus { cpu0: cpu@0 { cpu-power-states = <&suspend_to_idle0>; }; power-states { suspend_to_idle0: suspend-to-idle0 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; substate-id = <0>; min-residency-us = <1000>; }; }; }; def-io-conf-list { pinmux = <&alt0_gpio_no_spip &alt0_gpio_no_fpip &alt1_no_pwrgd &alt7_no_ksi0_sl &alt7_no_ksi1_sl &alt7_no_ksi2_sl &alt7_no_ksi3_sl &alt7_no_ksi4_sl &alt7_no_ksi5_sl &alt7_no_ksi6_sl &alt7_no_ksi7_sl &alt8_no_kso00_sl &alt8_no_kso01_sl &alt8_no_kso02_sl &alt8_no_kso03_sl &alt8_no_kso04_sl &alt8_no_kso05_sl &alt8_no_kso06_sl &alt8_no_kso07_sl &alt9_no_kso08_sl &alt9_no_kso09_sl &alt9_no_kso10_sl &alt9_no_kso11_sl &alt9_no_kso12_sl &alt9_no_kso13_sl &alt9_no_kso14_sl &alt9_no_kso15_sl &alta_no_kso16_sl &alta_no_kso17_sl &alta_no_peci_en &altc_gpio97_sl_inv &altd_npsl_in1_sl &altd_npsl_in2_sl &altd_psl_in3_sl &altd_psl_in4_sl &altg_psl_gpo_sl>; }; soc { compatible = "nuvoton,npcx4", "nuvoton,npcx", "simple-bus"; /* * Writing to BKUP_STS register might affect the value stored in * the first byte of the BBRAM. * Workaround it by not using the first byte of the BBRAM. * (See npcx4 Errata 2.27) */ bbram: bb-ram@400af001 { compatible = "nuvoton,npcx-bbram"; reg = <0x400af001 0x7F 0x400af100 0x1>; reg-names = "memory", "status"; }; /* Specific soc devices in npcx4 series */ itims: timer@400b0000 { compatible = "nuvoton,npcx-itim-timer"; reg = <0x400b0000 0x2000 0x400be000 0x2000>; reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; interrupts = <28 1>; /* Event timer interrupt */ }; uart1: serial@400e0000 { compatible = "nuvoton,npcx-uart"; /* Index 0: UART1 register, Index 1: MDMA1 register */ reg = <0x400E0000 0x2000 0x40011100 0x100>; interrupts = <33 3>; /* Index 0: UART1 clock, Index 1: MDMA1 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>; uart-rx = <&wui_cr_sin1>; status = "disabled"; }; uart2: serial@400e2000 { compatible = "nuvoton,npcx-uart"; /* Index 0: UART2 register, Index 1: MDMA2 register */ reg = <0x400E2000 0x2000 0x40011200 0x100>; interrupts = <32 3>; clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>; uart-rx = <&wui_cr_sin2>; status = "disabled"; }; uart3: serial@400e4000 { compatible = "nuvoton,npcx-uart"; /* Index 0: UART3 register, Index 1: MDMA3 register */ reg = <0x400E4000 0x2000 0x40011300 0x100>; interrupts = <38 3>; /* Index 0: UART3 clock, Index 1: MDMA3 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>; uart-rx = <&wui_cr_sin3>; status = "disabled"; }; uart4: serial@400e6000 { compatible = "nuvoton,npcx-uart"; /* Index 0: UART4 register, Index 1: MDMA4 register */ reg = <0x400E6000 0x2000 0x40011400 0x100>; interrupts = <39 3>; /* Index 0: UART4 clock, Index 1: MDMA4 clock */ clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>; uart-rx = <&wui_cr_sin4>; status = "disabled"; }; /* Default clock and power settings in npcx4 series */ pcc: clock-controller@4000d000 { clock-frequency = ; /* OFMCLK runs at 120MHz */ core-prescaler = <8>; /* CORE_CLK runs at 15MHz */ apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */ apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */ apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */ apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */ ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */ pwdwn-ctl-val = <0xfb 0xff 0x1f /* No GDMA1_PD/GDMA2_PD */ 0xff 0xfa 0x7f /* No ESPI_PD */ 0xff 0xcf>; /* No FIU_PD */ }; /* Wake-up input source mapping for GPIOs in npcx4 series */ gpio0: gpio@40081000 { wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03 &wui_io04 &wui_io05 &wui_io06 &wui_io07>; lvol-maps = <&lvol_io00 &lvol_io01 &lvol_io02 &lvol_io03 &lvol_io04 &lvol_io05 &lvol_io06 &lvol_io07>; }; gpio1: gpio@40083000 { wui-maps = <&wui_io10 &wui_io11 &wui_io12 &wui_io13 &wui_io14 &wui_io15 &wui_io16 &wui_io17>; lvol-maps = <&lvol_io10 &lvol_io11 &lvol_none &lvol_io13 &lvol_io14 &lvol_io15 &lvol_io16 &lvol_io17>; }; gpio2: gpio@40085000 { wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23 &wui_io24 &wui_io25 &wui_io26 &wui_io27>; lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23 &lvol_none &lvol_none &lvol_none &lvol_none>; }; gpio3: gpio@40087000 { wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33 &wui_io34 &wui_none &wui_io36 &wui_io37>; lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33 &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>; }; gpio4: gpio@40089000 { wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43 &wui_io44 &wui_io45 &wui_io46 &wui_io47>; lvol-maps = <&lvol_io40 &lvol_io41 &lvol_io42 &lvol_io43 &lvol_io44 &lvol_io45 &lvol_none &lvol_none>; }; gpio5: gpio@4008b000 { wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53 &wui_io54 &wui_io55 &wui_io56 &wui_io57>; lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none>; }; gpio6: gpio@4008d000 { wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63 &wui_io64 &wui_none &wui_io66 &wui_io67>; lvol-maps = <&lvol_io60 &lvol_io61 &lvol_io62 &lvol_io63 &lvol_io64 &lvol_none &lvol_io66 &lvol_io67>; }; gpio7: gpio@4008f000 { wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73 &wui_io74 &wui_io75 &wui_io76 &wui_none>; lvol-maps = <&lvol_io70 &lvol_none &lvol_io72 &lvol_io73 &lvol_io74 &lvol_io75 &lvol_io76 &lvol_none>; }; gpio8: gpio@40091000 { wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 &wui_none &wui_none &wui_none &wui_io87>; lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_io83 &lvol_none &lvol_none &lvol_none &lvol_io87>; }; gpio9: gpio@40093000 { wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93 &wui_io94 &wui_io95 &wui_io96 &wui_io97>; lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none>; }; gpioa: gpio@40095000 { wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none &lvol_none>; }; gpiob: gpio@40097000 { wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3 &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>; lvol-maps = <&lvol_none &lvol_iob1 &lvol_iob2 &lvol_iob3 &lvol_iob4 &lvol_iob5 &lvol_iob6 &lvol_iob7>; }; gpioc: gpio@40099000 { wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3 &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>; lvol-maps = <&lvol_ioc0 &lvol_ioc1 &lvol_ioc2 &lvol_ioc3 &lvol_ioc4 &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>; }; gpiod: gpio@4009b000 { wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3 &wui_iod4 &wui_iod5 &wui_iod6 &wui_none>; lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_iod2 &lvol_iod3 &lvol_iod4 &lvol_iod5 &lvol_iod6 &lvol_none>; }; gpioe: gpio@4009d000 { wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3 &wui_ioe4 &wui_ioe5 &wui_none &wui_ioe7>; lvol-maps = <&lvol_ioe0 &lvol_ioe1 &lvol_ioe2 &lvol_ioe3 &lvol_ioe4 &lvol_ioe5 &lvol_none &lvol_ioe7>; }; gpiof: gpio@4009f000 { wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3 &wui_iof4 &wui_iof5 &wui_none &wui_none>; lvol-maps = <&lvol_iof0 &lvol_iof1 &lvol_iof2 &lvol_iof3 &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>; }; /* ADC0 comparator configuration in npcx4 series */ adc0: adc@400d1000 { channel-count = <26>; threshold-count = <6>; }; /* ADC1 which reference voltage is AVCC */ adc1: adc@400d5000 { compatible = "nuvoton,npcx-adc"; #io-channel-cells = <1>; reg = <0x400d5000 0x2000>; interrupts = <22 3>; clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>; vref-mv = <3300>; channel-count = <26>; threshold-count = <6>; status = "disabled"; }; /* FIU0 configuration in npcx4 series */ qspi_fiu0: quadspi@40020000 { clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 5>; }; /* FIU1 configuration in npcx4 series */ qspi_fiu1: quadspi@40021000 { compatible = "nuvoton,npcx-fiu-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40021000 0x1000>; clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 6>; }; sha0: sha@148 { compatible = "nuvoton,npcx-sha"; reg = <0x148 0x4c>; context-buffer-size = <240>; status = "disabled"; }; shi0: shi@4000f000 { compatible = "nuvoton,npcx-shi-enhanced"; reg = <0x4000f000 0x120>; interrupts = <18 1>; clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; status = "disabled"; buffer-rx-size = <128>; buffer-tx-size = <128>; shi-cs-wui =<&wui_io53>; }; espi0: espi@4000a000 { rx-plsize = <64>; tx-plsize = <64>; espi_taf: espitaf@4000a000 { compatible = "nuvoton,npcx-espi-taf"; reg = <0x4000a000 0x2000>; status = "disabled"; }; }; rctl: reset-controller@400c3100 { compatible = "nuvoton,npcx-rst"; reg = <0x400c3100 0x14>; #reset-cells = <1>; status = "disabled"; }; i3c0: i3c@400f0000 { compatible = "nuvoton,npcx-i3c"; /* reg[0]: I3C_1 register, reg[1]: MDMA5 register */ reg-names = "i3c1", "mdma5"; reg = <0x400f0000 0x2000>, <0x40011500 0x100>; interrupts = <29 3>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_1>; /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ /* clk[2]: MDMA5 */ clock-names = "mclkd", "apb4", "mdma5"; clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 0>, <&pcc NPCX_CLOCK_BUS_APB4 0 0>, <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 4>; status = "disabled"; #address-cells = <3>; #size-cells = <0>; instance-id = <0x00>; }; i3c1: i3c@400f2000 { compatible = "nuvoton,npcx-i3c"; /* reg[0]: I3C_2 register, reg[1]: MDMA6 register */ reg-names = "i3c2", "mdma6"; reg = <0x400f2000 0x2000>, <0x40011600 0x100>; interrupts = <66 3>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_2>; /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ /* clk[2]: MDMA6 */ clock-names = "mclkd", "apb4", "mdma6"; clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 2>, <&pcc NPCX_CLOCK_BUS_APB4 0 0>, <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 5>; status = "disabled"; #address-cells = <3>; #size-cells = <0>; instance-id = <0x10>; }; i3c2: i3c@400f4000 { compatible = "nuvoton,npcx-i3c"; /* reg[0]: I3C_3 register, reg[1]: MDMA7 register */ reg-names = "i3c1", "mdma7"; reg = <0x400f4000 0x2000>, <0x40011700 0x100>; interrupts = <67 3>; /* Reset controller */ resets = <&rctl NPCX_RESET_I3C_3>; /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ /* clk[2]: MDMA7 */ clock-names = "mclkd", "apb4", "mdma7"; clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 3>, <&pcc NPCX_CLOCK_BUS_APB4 0 0>, <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 6>; status = "disabled"; #address-cells = <3>; #size-cells = <0>; instance-id = <0x20>; }; }; soc-if { i2c4_0: io_i2c_ctrl4_port0 { compatible = "nuvoton,npcx-i2c-port"; #address-cells = <1>; #size-cells = <0>; port = <0x40>; controller = <&i2c_ctrl4>; status = "disabled"; }; i2c7_1: io_i2c_ctrl7_port1 { compatible = "nuvoton,npcx-i2c-port"; #address-cells = <1>; #size-cells = <0>; port = <0x71>; controller = <&i2c_ctrl7>; status = "disabled"; }; }; soc-id { family-id = <0x23>; chip-id = <0x0a>; revision-reg = <0x0000FFFC 4>; }; };