1/*
2 * Copyright (c) 2019 ML!PA Consulting GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12
13/ {
14	aliases {
15		adc-0 = &adc0;
16		adc-1 = &adc1;
17
18		port-a = &porta;
19		port-b = &portb;
20		port-c = &portc;
21		port-d = &portd;
22
23		sercom-0 = &sercom0;
24		sercom-1 = &sercom1;
25		sercom-2 = &sercom2;
26		sercom-3 = &sercom3;
27		sercom-4 = &sercom4;
28		sercom-5 = &sercom5;
29		sercom-6 = &sercom6;
30		sercom-7 = &sercom7;
31
32		tc-0 = &tc0;
33		tc-2 = &tc2;
34		tc-4 = &tc4;
35		tc-6 = &tc6;
36
37		tcc-0 = &tcc0;
38		tcc-1 = &tcc1;
39		tcc-2 = &tcc2;
40		tcc-3 = &tcc3;
41		tcc-4 = &tcc4;
42
43		watchdog0 = &wdog;
44	};
45
46	chosen {
47		zephyr,entropy = &trng;
48		zephyr,flash-controller = &nvmctrl;
49	};
50
51	cpus {
52		#address-cells = <1>;
53		#size-cells = <0>;
54
55		cpu0: cpu@0 {
56			compatible = "arm,cortex-m4f";
57			reg = <0>;
58
59			#address-cells = <1>;
60			#size-cells = <1>;
61
62			device_type = "cpu";
63
64			mpu: mpu@e000ed90 {
65				compatible = "arm,armv7m-mpu";
66				reg = <0xe000ed90 0x40>;
67			};
68		};
69	};
70
71	soc {
72		sram0: memory@20000000 {
73			compatible = "mmio-sram";
74			reg = <0x20000000 0x40000>;
75		};
76
77		backup0: memory@47000000 {
78			compatible = "mmio-sram";
79			reg = <0x47000000 0x2000>;
80		};
81
82		id: device_id@8061fc {
83			compatible = "atmel,sam0-id";
84			reg =	<0x008061FC 0x4>,
85				<0x00806010 0x4>,
86				<0x00806014 0x4>,
87				<0x00806018 0x4>;
88		};
89
90		mclk: mclk@40000800 {
91			compatible = "atmel,samd5x-mclk";
92			reg = <0x40000800 0x400>;
93
94			#clock-cells = <2>;
95		};
96
97		gclk: gclk@40001c00 {
98			compatible = "atmel,samd5x-gclk";
99			reg = <0x40001c00 0x400>;
100
101			#clock-cells = <1>;
102		};
103
104		nvmctrl: nvmctrl@41004000  {
105			compatible = "atmel,sam0-nvmctrl";
106			reg = <0x41004000 0x22>;
107			interrupts = <29 0>, <30 0>;
108
109			#address-cells = <1>;
110			#size-cells = <1>;
111
112			lock-regions = <32>;
113
114			flash0: flash@0 {
115				compatible = "soc-nv-flash";
116
117				write-block-size = <8>;
118			};
119		};
120
121		dmac: dmac@4100a000 {
122			compatible = "atmel,sam0-dmac";
123			reg = <0x4100A000 0x50>;
124			interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
125			status = "disabled";
126
127			#dma-cells = <2>;
128		};
129
130		eic: eic@40002800 {
131			compatible = "atmel,sam0-eic";
132			reg = <0x40002800 0x38>;
133			interrupts = <12 0>, <13 0>, <14 0>, <15 0>,
134				     <16 0>, <17 0>, <18 0>, <19 0>,
135				     <20 0>, <21 0>, <22 0>, <23 0>,
136				     <24 0>, <25 0>, <26 0>, <27 0>;
137		};
138
139		pinmux_a: pinmux@41008000 {
140			compatible = "atmel,sam0-pinmux";
141			reg = <0x41008000 0x80>;
142		};
143
144		pinmux_b: pinmux@41008080 {
145			compatible = "atmel,sam0-pinmux";
146			reg = <0x41008080 0x80>;
147		};
148
149		pinmux_c: pinmux@41008100 {
150			compatible = "atmel,sam0-pinmux";
151			reg = <0x41008100 0x80>;
152		};
153
154		pinmux_d: pinmux@41008180 {
155			compatible = "atmel,sam0-pinmux";
156			reg = <0x41008180 0x80>;
157		};
158
159		wdog: watchdog@40002000 {
160			compatible = "atmel,sam0-watchdog";
161			reg = <0x40002000 13>;
162			interrupts = <10 0>;
163		};
164
165		sercom0: sercom@40003000 {
166			compatible = "atmel,sam0-sercom";
167			reg = <0x40003000 0x40>;
168			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
169			clocks = <&gclk 7>, <&mclk 0x14 12>;
170			clock-names = "GCLK", "MCLK";
171			status = "disabled";
172		};
173
174		sercom1: sercom@40003400 {
175			compatible = "atmel,sam0-sercom";
176			reg = <0x40003400 0x40>;
177			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
178			clocks = <&gclk 8>, <&mclk 0x14 13>;
179			clock-names = "GCLK", "MCLK";
180			status = "disabled";
181		};
182
183		sercom2: sercom@41012000 {
184			compatible = "atmel,sam0-sercom";
185			reg = <0x41012000 0x40>;
186			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
187			clocks = <&gclk 23>, <&mclk 0x18 9>;
188			clock-names = "GCLK", "MCLK";
189			status = "disabled";
190		};
191
192		sercom3: sercom@41014000 {
193			compatible = "atmel,sam0-sercom";
194			reg = <0x41014000 0x40>;
195			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
196			clocks = <&gclk 24>, <&mclk 0x18 10>;
197			clock-names = "GCLK", "MCLK";
198			status = "disabled";
199		};
200
201		sercom4: sercom@43000000 {
202			compatible = "atmel,sam0-sercom";
203			reg = <0x43000000 0x40>;
204			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
205			clocks = <&gclk 34>, <&mclk 0x20 0>;
206			clock-names = "GCLK", "MCLK";
207			status = "disabled";
208		};
209
210		sercom5: sercom@43000400 {
211			compatible = "atmel,sam0-sercom";
212			reg = <0x43000400 0x40>;
213			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
214			clocks = <&gclk 35>, <&mclk 0x20 1>;
215			clock-names = "GCLK", "MCLK";
216			status = "disabled";
217		};
218
219		sercom6: sercom@43000800 {
220			compatible = "atmel,sam0-sercom";
221			reg = <0x43000800 0x40>;
222			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
223			clocks = <&gclk 36>, <&mclk 0x20 2>;
224			clock-names = "GCLK", "MCLK";
225			status = "disabled";
226		};
227
228		sercom7: sercom@43000c00 {
229			compatible = "atmel,sam0-sercom";
230			reg = <0x43000C00 0x40>;
231			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
232			clocks = <&gclk 37>, <&mclk 0x20 3>;
233			clock-names = "GCLK", "MCLK";
234			status = "disabled";
235		};
236
237		pinctrl: pinctrl@41008000 {
238			compatible = "atmel,sam0-pinctrl";
239			ranges = <0x41008000 0x41008000 0x200>;
240
241			#address-cells = <1>;
242			#size-cells = <1>;
243
244			porta: gpio@41008000 {
245				compatible = "atmel,sam0-gpio";
246				reg = <0x41008000 0x80>;
247
248				#atmel,pin-cells = <2>;
249				#gpio-cells = <2>;
250
251				gpio-controller;
252			};
253
254			portb: gpio@41008080 {
255				compatible = "atmel,sam0-gpio";
256				reg = <0x41008080 0x80>;
257
258				#atmel,pin-cells = <2>;
259				#gpio-cells = <2>;
260
261				gpio-controller;
262			};
263
264			portc: gpio@41008100 {
265				compatible = "atmel,sam0-gpio";
266				reg = <0x41008100 0x80>;
267
268				#atmel,pin-cells = <2>;
269				#gpio-cells = <2>;
270
271				gpio-controller;
272			};
273
274			portd: gpio@41008180 {
275				compatible = "atmel,sam0-gpio";
276				reg = <0x41008180 0x80>;
277
278				#atmel,pin-cells = <2>;
279				#gpio-cells = <2>;
280
281				gpio-controller;
282			};
283		};
284
285		usb0: usb@41000000 {
286			compatible = "atmel,sam0-usb";
287			reg = <0x41000000 0x1000>;
288			interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
289			status = "disabled";
290
291			num-bidir-endpoints = <8>;
292		};
293
294		trng: random@42002800 {
295			compatible = "atmel,sam-trng";
296			reg = <0x42002800 0x1e>;
297			interrupts = <131 0>;
298		};
299
300		rtc: rtc@40002400 {
301			compatible = "atmel,sam0-rtc";
302			reg = <0x40002400 0x1C>;
303			interrupts = <11 0>;
304			status = "disabled";
305
306			clock-generator = <0>;
307		};
308
309		adc0: adc@43001c00 {
310			compatible = "atmel,sam0-adc";
311			reg = <0x43001C00 0x4A>;
312			interrupts = <118 0>, <119 0>;
313			interrupt-names = "overrun", "resrdy";
314			clocks = <&gclk 40>, <&mclk 0x20 7>;
315			clock-names = "GCLK", "MCLK";
316			status = "disabled";
317
318			#io-channel-cells = <1>;
319
320			/*
321			 * 16 MHz max, source clock must not exceed 100 MHz.
322			 *	- table 54-8, section 54.6, page 2020
323			 *	- table 54-24, section 54.10.4, page 2031
324			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
325			 */
326			gclk = <2>;
327			prescaler = <4>;
328			calib-offset = <0>;
329		};
330
331		adc1: adc@43002000 {
332			compatible = "atmel,sam0-adc";
333			reg = <0x43002000 0x4A>;
334			interrupts = <120 0>, <121 0>;
335			interrupt-names = "overrun", "resrdy";
336			clocks = <&gclk 41>, <&mclk 0x20 8>;
337			clock-names = "GCLK", "MCLK";
338			status = "disabled";
339
340			#io-channel-cells = <1>;
341
342			/*
343			 * 16 MHz max, source clock must not exceed 100 MHz.
344			 *	- table 54-8, section 54.6, page 2020
345			 *	- table 54-24, section 54.10.4, page 2031
346			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
347			 */
348			gclk = <2>;
349			prescaler = <4>;
350			calib-offset = <14>;
351		};
352
353		tc0: tc@40003800 {
354			compatible = "atmel,sam0-tc32";
355			reg = <0x40003800 0x34>;
356			interrupts = <107 0>;
357			clocks = <&gclk 9>, <&mclk 0x14 14>;
358			clock-names = "GCLK", "MCLK";
359			status = "disabled";
360		};
361
362		tc2: tc@4101a000 {
363			compatible = "atmel,sam0-tc32";
364			reg = <0x4101A000 0x34>;
365			interrupts = <109 0>;
366			clocks = <&gclk 26>, <&mclk 0x18 13>;
367			clock-names = "GCLK", "MCLK";
368			status = "disabled";
369		};
370
371		tc4: tc@42001400 {
372			compatible = "atmel,sam0-tc32";
373			reg = <0x42001400 0x34>;
374			interrupts = <111 0>;
375			clocks = <&gclk 30>, <&mclk 0x1c 5>;
376			clock-names = "GCLK", "MCLK";
377			status = "disabled";
378		};
379
380		tc6: tc@43001400 {
381			compatible = "atmel,sam0-tc32";
382			reg = <0x43001400 0x34>;
383			interrupts = <113 0>;
384			clocks = <&gclk 39>, <&mclk 0x20 5>;
385			clock-names = "GCLK", "MCLK";
386			status = "disabled";
387		};
388
389		tcc0: tcc@41016000 {
390			compatible = "atmel,sam0-tcc";
391			reg = <0x41016000 0x2000>;
392			interrupts = <85 0>, <86 0>, <87 0>, <88 0>, <89 0>,
393				     <90 0>, <91 0>;
394			clocks = <&gclk 25>, <&mclk 0x18 11>;
395			clock-names = "GCLK", "MCLK";
396			status = "disabled";
397
398			channels = <6>;
399			counter-size = <24>;
400		};
401
402		tcc1: tcc@41018000 {
403			compatible = "atmel,sam0-tcc";
404			reg = <0x41018000 0x2000>;
405			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
406			clocks = <&gclk 25>, <&mclk 0x18 12>;
407			clock-names = "GCLK", "MCLK";
408			status = "disabled";
409
410			channels = <4>;
411			counter-size = <24>;
412		};
413
414		tcc2: tcc@42000c00 {
415			compatible = "atmel,sam0-tcc";
416			reg = <0x42000c00 0x400>;
417			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
418			clocks = <&gclk 29>, <&mclk 0x1c 3>;
419			clock-names = "GCLK", "MCLK";
420			status = "disabled";
421
422			channels = <3>;
423			counter-size = <16>;
424		};
425
426		tcc3: tcc@42001000 {
427			compatible = "atmel,sam0-tcc";
428			reg = <0x42001000 0x400>;
429			interrupts = <101 0>, <102 0>, <103 0>;
430			clocks = <&gclk 29>, <&mclk 0x1c 4>;
431			clock-names = "GCLK", "MCLK";
432			status = "disabled";
433
434			channels = <2>;
435			counter-size = <16>;
436		};
437
438		tcc4: tcc@43001000 {
439			compatible = "atmel,sam0-tcc";
440			reg = <0x43001000 0x400>;
441			interrupts = <104 0>, <105 0>, <106 0>;
442			clocks = <&gclk 38>, <&mclk 0x20 4>;
443			clock-names = "GCLK", "MCLK";
444			status = "disabled";
445
446			channels = <2>;
447			counter-size = <16>;
448		};
449	};
450};
451
452&nvic {
453	arm,num-irq-priority-bits = <3>;
454};
455