1# Copyright (c) 2024 Nuvoton Technology Corporation.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Nuvoton, NPCM PCC (Power and Clock Controller) node.
6  Besides power management, this node is also in charge of configuring the
7  Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8  High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
9  and most of NPCM hardware modules.
10
11  Here is an example of configuring OFMCLK and the other clock sources derived
12  from it in board dts file.
13  &pcc {
14      clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15      core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16      apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17      apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18      apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19      apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20      fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21      i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
22  };
23
24compatible: "nuvoton,npcm-pcc"
25
26include: [clock-controller.yaml, base.yaml]
27
28properties:
29  reg:
30    required: true
31
32  clock-frequency:
33    required: true
34    type: int
35    description: |
36      Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
37      only the following values are allowed:
38        100000000, 100 MHz
39        96000000, 96 MHz
40        80000000, 80 MHz
41        66000000, 66 MHz
42        50000000, 50 MHz
43        48000000, 48 MHz
44        40000000, 40 MHz
45        33000000, 33 MHz
46    enum:
47      - 100000000
48      - 96000000
49      - 80000000
50      - 66000000
51      - 50000000
52      - 48000000
53      - 40000000
54      - 33000000
55
56  core-prescaler:
57    type: int
58    required: true
59    description: |
60      Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
61      dividing OFMCLK(MCLK) and needs to meet the following requirements.
62      - The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
63      - Only the following values are allowed:
64        1, CORE_CLK = OFMCLK
65        2, CORE_CLK = OFMCLK / 2
66        3, CORE_CLK = OFMCLK / 3
67        4, CORE_CLK = OFMCLK / 4
68        5, CORE_CLK = OFMCLK / 5
69        6, CORE_CLK = OFMCLK / 6
70        7, CORE_CLK = OFMCLK / 7
71        8, CORE_CLK = OFMCLK / 8
72        9, CORE_CLK = OFMCLK / 9
73        10, CORE_CLK = OFMCLK / 10
74    enum:
75      - 1
76      - 2
77      - 3
78      - 4
79      - 5
80      - 6
81      - 7
82      - 8
83      - 9
84      - 10
85
86  apb1-prescaler:
87    type: int
88    required: true
89    description: |
90      APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
91      OFMCLK(MCLK) and needs to meet the following requirements.
92      - The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
93      - Only the following values are allowed:
94        1, APB1_CLK = OFMCLK
95        2, APB1_CLK = OFMCLK / 2
96        3, APB1_CLK = OFMCLK / 3
97        4, APB1_CLK = OFMCLK / 4
98        5, APB1_CLK = OFMCLK / 5
99        6, APB1_CLK = OFMCLK / 6
100        7, APB1_CLK = OFMCLK / 7
101        8, APB1_CLK = OFMCLK / 8
102        9, APB1_CLK = OFMCLK / 9
103        10, APB1_CLK = OFMCLK / 10
104    enum:
105      - 1
106      - 2
107      - 3
108      - 4
109      - 5
110      - 6
111      - 7
112      - 8
113      - 9
114      - 10
115
116  apb2-prescaler:
117    type: int
118    required: true
119    description: |
120      APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
121      OFMCLK(MCLK) and needs to meet the following requirements.
122      - The maximum APB2_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
123      - Only the following values are allowed:
124        1, APB2_CLK = OFMCLK
125        2, APB2_CLK = OFMCLK / 2
126        3, APB2_CLK = OFMCLK / 3
127        4, APB2_CLK = OFMCLK / 4
128        5, APB2_CLK = OFMCLK / 5
129        6, APB2_CLK = OFMCLK / 6
130        7, APB2_CLK = OFMCLK / 7
131        8, APB2_CLK = OFMCLK / 8
132        9, APB2_CLK = OFMCLK / 9
133        10, APB2_CLK = OFMCLK / 10
134    enum:
135      - 1
136      - 2
137      - 3
138      - 4
139      - 5
140      - 6
141      - 7
142      - 8
143      - 9
144      - 10
145
146  apb3-prescaler:
147    type: int
148    required: true
149    description: |
150      APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
151      OFMCLK(MCLK) and needs to meet the following requirements.
152      - The maximum APB3_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
153      - Only the following values are allowed:
154        1, APB3_CLK = OFMCLK
155        2, APB3_CLK = OFMCLK / 2
156        3, APB3_CLK = OFMCLK / 3
157        4, APB3_CLK = OFMCLK / 4
158        5, APB3_CLK = OFMCLK / 5
159        6, APB3_CLK = OFMCLK / 6
160        7, APB3_CLK = OFMCLK / 7
161        8, APB3_CLK = OFMCLK / 8
162        9, APB3_CLK = OFMCLK / 9
163        10, APB3_CLK = OFMCLK / 10
164    enum:
165      - 1
166      - 2
167      - 3
168      - 4
169      - 5
170      - 6
171      - 7
172      - 8
173      - 9
174      - 10
175
176  ahb6-prescaler:
177    type: int
178    required: true
179    description: |
180      AHB6 prescaler. The AHB6 bus clock (AHB6_CLK) is derived from the Core clock (CLK) via a
181      programmable divider controlled by the AHB6DIV field in HFCGP register.
182      Its frequency must be set according to the following rules:
183      - The maximum AHB6_CLK frequency is either the CLK frequency divided by 1 or 100 MHz.
184      - Only the following values are allowed:
185        1, AHB6_CLK = CORE_CLK
186        2, AHB6_CLK = CORE_CLK / 2
187        4, AHB6_CLK = CORE_CLK / 4
188    enum:
189      - 1
190      - 2
191      - 4
192
193  fiu-prescaler:
194    type: int
195    required: true
196    description: |
197      FIU prescaler. The FIU clock (FIUCLK) is derived from the Core clock (CLK) via a
198      programmable divider controlled by the FIUDIV field in HFCBCD1 register.
199      Its frequency must be set according to the following rules:
200      - The maximum FIUCLK frequency is either the CLK frequency divided by 1 or 100MHz.
201      - Only the following values are allowed:
202        1, FIU_CLK = CORE_CLK
203        2, FIU_CLK = CORE_CLK / 2
204        4, FIU_CLK = CORE_CLK / 4
205    enum:
206      - 1
207      - 2
208      - 4
209
210  i3c-prescaler:
211    type: int
212    required: true
213    description: |
214      I3C prescaler. It sets the I3C clk_slow_tc frequency, by dividing
215      APB3_CLK and it can be up to 100 MHz.
216    enum:
217      - 1
218      - 2
219      - 4
220
221clock-cells:
222  - clk_id
223