Home
last modified time | relevance | path

Searched +full:clkout +full:- +full:divider (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dnxp,kinetis-ke1xf-sim.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-ke1xf-sim"
14 clkout-source:
16 description: clkout clock source
18 clkout-divider:
20 description: clkout divider
Dnxp,kinetis-sim.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-sim"
14 pllfll-select:
19 er32k-select:
24 clkout-source:
26 description: clkout clock source
28 clkout-divider:
30 description: clkout divider
32 "#clock-cells":
36 clock-cells:
[all …]
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
33 litex,lock-timeout:
38 litex,drdy-timeout:
43 litex,divclk-divide-min:
[all …]
/Zephyr-latest/dts/bindings/can/
Despressif,esp32-twai.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Espressif ESP32 Two-Wire Automotive Interface (TWAI)
6 compatible: "espressif,esp32-twai"
8 include: [can-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 clkout-divider:
29 Clock divider for the CLKOUT signal. If not set, the CLKOUT signal is turned off.
32 Espressif MCUs like ESP32-C3.
/Zephyr-latest/drivers/clock_control/
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
87 * rate generator clock divider
92 volatile uint32_t usb_clk_div; /* USB clock divider */
94 volatile uint32_t clk_out_sel; /* CLKOUT source select */
95 volatile uint32_t clk_out_uen; /* CLKOUT source update */
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
26 static struct litex_clk_clkout *clkouts;/* clkout array for whole driver */
52 m.clkout[5].reg1 = CLKOUT5_REG1; in litex_clk_regs_addr_init()
53 m.clkout[5].reg2 = CLKOUT5_REG2; in litex_clk_regs_addr_init()
55 m.clkout[i].reg1 = addr; in litex_clk_regs_addr_init()
57 m.clkout[i].reg2 = addr; in litex_clk_regs_addr_init()
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
[all …]
Dclock_control_litex.h4 * SPDX-License-Identifier: Apache-2.0
63 BUILD_ASSERT(CLKOUT_ID(N) < NCLKOUT, "Invalid CLKOUT index"); \
64 lcko = &ldev->clkouts[N]; \
65 lcko->id = CLKOUT_ID(N); \
67 lcko->clkout_div = clkout_div; \
68 lcko->def.freq = CLKOUT_FREQ(N); \
69 lcko->def.phase = CLKOUT_PHASE(N); \
70 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
71 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \
72 lcko->margin.m = CLKOUT_MARGIN(N); \
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &sci2;
12 /delete-node/ &sci3;
13 /delete-node/ &ioport6;
14 /delete-node/ &ioport7;
15 /delete-node/ &ioport8;
20 compatible = "mmio-sram";
25 compatible = "renesas,ra-spi";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
24 gpio-controller;
25 #gpio-cells = <2>;
31 compatible = "renesas,ra-gpio-ioport";
[all …]
Dr7fa4m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &spi1;
13 /delete-node/ &adc1;
18 compatible = "mmio-sram";
23 compatible = "renesas,ra-gpio-ioport";
26 gpio-controller;
27 #gpio-cells = <2>;
[all …]
Dr7fa4w1ad2cng.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/ra_clock.h>
8 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
20 flash-controller@407e0000 {
22 compatible = "soc-nv-flash";
28 compatible = "renesas,ra-sci";
30 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e2bx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
10 /delete-node/ &agt0;
11 /delete-node/ &agt1;
12 /delete-node/ &agt2;
13 /delete-node/ &agt3;
14 /delete-node/ &agt4;
15 /delete-node/ &agt5;
16 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
[all …]
Dr7fa6m4ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa6e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
11 /delete-node/ &adc1;
16 compatible = "mmio-sram";
21 compatible = "renesas,ra-gpio-ioport";
24 gpio-controller;
25 #gpio-cells = <2>;
31 compatible = "renesas,ra-gpio-ioport";
[all …]
Dr7fa6m5xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
[all …]
Dr7fa6m2ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
[all …]
Dr7fa6m3ax.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-gpio-ioport";
22 gpio-controller;
23 #gpio-cells = <2>;
29 compatible = "renesas,ra-gpio-ioport";
32 gpio-controller;
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
51 /* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 /* Denominator of the SYSPLL0 fractional loop divider is 1 */
61 /* Numerator of the Audio PLL fractional loop divider is 0 */
63 /* Denominator of the Audio PLL fractional loop divider is 1 */
69 .num = 0, .sfg_clock_src = kCLOCK_FrgPllDiv, .divider = 255U, .mult = 0};
72 .num = 12, .sfg_clock_src = kCLOCK_FrgMainClk, .divider = 255U, .mult = 167};
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
[all …]
/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "twr_ke18f-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
27 pwm-led0 = &orange_pwm_led;
28 pwm-led1 = &yellow_pwm_led;
29 pwm-led2 = &green_pwm_led;
[all …]
/Zephyr-latest/drivers/can/
Dcan_esp32_twai.c5 * SPDX-License-Identifier: Apache-2.0
23 * Newer ESP32-series MCUs like ESP32-C3 and ESP32-S2 have some slightly different registers
56 * - TWAI_STATUS_REG has new bit 8: TWAI_MISS_ST
57 * - TWAI_INT_RAW_REG has new bit 8: TWAI_BUS_STATE_INT_ST
58 * - TWAI_INT_ENA_REG has new bit 8: TWAI_BUS_STATE_INT_ENA
77 /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
84 const struct can_sja1000_config *sja1000_config = dev->config; in can_esp32_twai_read_reg()
85 const struct can_esp32_twai_config *twai_config = sja1000_config->custom; in can_esp32_twai_read_reg()
86 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_read_reg()
93 const struct can_sja1000_config *sja1000_config = dev->config; in can_esp32_twai_write_reg()
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
61 SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK; in enable_cache64()
64 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in enable_cache64()
65 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in enable_cache64()
67 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { in enable_cache64()
70 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); in enable_cache64()
76 CACHE64_POLSEL0->REG0_TOP = 0x7FFC00; in enable_cache64()
77 CACHE64_POLSEL0->REG1_TOP = 0x0; in enable_cache64()
78 CACHE64_POLSEL0->POLSEL = in enable_cache64()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
[all …]