1 /*
2  * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
3  * Copyright (c) 2022 Martin Jäger <martin@libre.solar>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #define DT_DRV_COMPAT espressif_esp32_twai
9 
10 #include <zephyr/drivers/can/can_sja1000.h>
11 
12 #include <zephyr/drivers/can.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/logging/log.h>
17 
18 #include <soc.h>
19 
20 LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL);
21 
22 /*
23  * Newer ESP32-series MCUs like ESP32-C3 and ESP32-S2 have some slightly different registers
24  * compared to the original ESP32, which is fully compatible with the SJA1000 controller.
25  *
26  * The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible
27  * registers.
28  */
29 #ifndef CONFIG_SOC_SERIES_ESP32
30 
31 /* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */
32 #define TWAI_BUS_TIMING_0_REG           (6U)
33 #define TWAI_BAUD_PRESC_MASK            GENMASK(12, 0)
34 #define TWAI_SYNC_JUMP_WIDTH_MASK       GENMASK(15, 14)
35 #define TWAI_BAUD_PRESC_PREP(brp)	FIELD_PREP(TWAI_BAUD_PRESC_MASK, brp)
36 #define TWAI_SYNC_JUMP_WIDTH_PREP(sjw)	FIELD_PREP(TWAI_SYNC_JUMP_WIDTH_MASK, sjw)
37 
38 /*
39  * TWAI_BUS_TIMING_1_REG is compatible with CAN_SJA1000_BTR1, but needed here for the custom
40  * set_timing() function.
41  */
42 #define TWAI_BUS_TIMING_1_REG           (7U)
43 #define TWAI_TIME_SEG1_MASK             GENMASK(3, 0)
44 #define TWAI_TIME_SEG2_MASK             GENMASK(6, 4)
45 #define TWAI_TIME_SAMP                  BIT(7)
46 #define TWAI_TIME_SEG1_PREP(seg1)       FIELD_PREP(TWAI_TIME_SEG1_MASK, seg1)
47 #define TWAI_TIME_SEG2_PREP(seg2)       FIELD_PREP(TWAI_TIME_SEG2_MASK, seg2)
48 
49 /* TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR */
50 #define TWAI_CLOCK_DIVIDER_REG          (31U)
51 #define TWAI_CD_MASK			GENMASK(7, 0)
52 #define TWAI_CLOCK_OFF			BIT(8)
53 
54 /*
55  * Further incompatible registers currently not used by the driver:
56  * - TWAI_STATUS_REG has new bit 8: TWAI_MISS_ST
57  * - TWAI_INT_RAW_REG has new bit 8: TWAI_BUS_STATE_INT_ST
58  * - TWAI_INT_ENA_REG has new bit 8: TWAI_BUS_STATE_INT_ENA
59  */
60 #else
61 
62 /* Redefinitions of the SJA1000 CDR bits to simplify driver config */
63 #define TWAI_CD_MASK			GENMASK(2, 0)
64 #define TWAI_CLOCK_OFF			BIT(3)
65 
66 #endif /* !CONFIG_SOC_SERIES_ESP32 */
67 
68 struct can_esp32_twai_config {
69 	mm_reg_t base;
70 	const struct pinctrl_dev_config *pcfg;
71 	const struct device *clock_dev;
72 	const clock_control_subsys_t clock_subsys;
73 	int irq_source;
74 	int irq_priority;
75 	int irq_flags;
76 #ifndef CONFIG_SOC_SERIES_ESP32
77 	/* 32-bit variant of output clock divider register required for non-ESP32 MCUs */
78 	uint32_t cdr32;
79 #endif /* !CONFIG_SOC_SERIES_ESP32 */
80 };
81 
can_esp32_twai_read_reg(const struct device * dev,uint8_t reg)82 static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg)
83 {
84 	const struct can_sja1000_config *sja1000_config = dev->config;
85 	const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
86 	mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
87 
88 	return sys_read32(addr) & 0xFF;
89 }
90 
can_esp32_twai_write_reg(const struct device * dev,uint8_t reg,uint8_t val)91 static void can_esp32_twai_write_reg(const struct device *dev, uint8_t reg, uint8_t val)
92 {
93 	const struct can_sja1000_config *sja1000_config = dev->config;
94 	const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
95 	mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
96 
97 	sys_write32(val & 0xFF, addr);
98 }
99 
100 #ifndef CONFIG_SOC_SERIES_ESP32
101 
102 /*
103  * Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size.
104  */
can_esp32_twai_write_reg32(const struct device * dev,uint8_t reg,uint32_t val)105 static void can_esp32_twai_write_reg32(const struct device *dev, uint8_t reg, uint32_t val)
106 {
107 	const struct can_sja1000_config *sja1000_config = dev->config;
108 	const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
109 	mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t);
110 
111 	sys_write32(val, addr);
112 }
113 
114 /*
115  * Custom implementation instead of can_sja1000_set_timing required because TWAI_BUS_TIMING_0_REG
116  * is incompatible with CAN_SJA1000_BTR0.
117  */
can_esp32_twai_set_timing(const struct device * dev,const struct can_timing * timing)118 static int can_esp32_twai_set_timing(const struct device *dev, const struct can_timing *timing)
119 {
120 	struct can_sja1000_data *data = dev->data;
121 	uint8_t btr0;
122 	uint8_t btr1;
123 
124 	if (data->common.started) {
125 		return -EBUSY;
126 	}
127 
128 	k_mutex_lock(&data->mod_lock, K_FOREVER);
129 
130 	btr0 = TWAI_BAUD_PRESC_PREP(timing->prescaler - 1) |
131 	       TWAI_SYNC_JUMP_WIDTH_PREP(timing->sjw - 1);
132 	btr1 = TWAI_TIME_SEG1_PREP(timing->phase_seg1 - 1) |
133 	       TWAI_TIME_SEG2_PREP(timing->phase_seg2 - 1);
134 
135 	if ((data->common.mode & CAN_MODE_3_SAMPLES) != 0) {
136 		btr1 |= TWAI_TIME_SAMP;
137 	}
138 
139 	can_esp32_twai_write_reg32(dev, TWAI_BUS_TIMING_0_REG, btr0);
140 	can_esp32_twai_write_reg32(dev, TWAI_BUS_TIMING_1_REG, btr1);
141 
142 	k_mutex_unlock(&data->mod_lock);
143 
144 	return 0;
145 }
146 
147 #endif /* !CONFIG_SOC_SERIES_ESP32 */
148 
can_esp32_twai_get_core_clock(const struct device * dev,uint32_t * rate)149 static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate)
150 {
151 	ARG_UNUSED(dev);
152 
153 	/* The internal clock operates at half of the oscillator frequency */
154 	*rate = APB_CLK_FREQ / 2;
155 
156 	return 0;
157 }
158 
can_esp32_twai_isr(void * arg)159 static void IRAM_ATTR can_esp32_twai_isr(void *arg)
160 {
161 	const struct device *dev = (const struct device *)arg;
162 
163 	can_sja1000_isr(dev);
164 }
165 
can_esp32_twai_init(const struct device * dev)166 static int can_esp32_twai_init(const struct device *dev)
167 {
168 	const struct can_sja1000_config *sja1000_config = dev->config;
169 	const struct can_esp32_twai_config *twai_config = sja1000_config->custom;
170 	int err;
171 
172 	if (!device_is_ready(twai_config->clock_dev)) {
173 		LOG_ERR("clock control device not ready");
174 		return -ENODEV;
175 	}
176 
177 	err = pinctrl_apply_state(twai_config->pcfg, PINCTRL_STATE_DEFAULT);
178 	if (err != 0) {
179 		LOG_ERR("failed to configure TWAI pins (err %d)", err);
180 		return err;
181 	}
182 
183 	err = clock_control_on(twai_config->clock_dev, twai_config->clock_subsys);
184 	if (err != 0) {
185 		LOG_ERR("failed to enable CAN clock (err %d)", err);
186 		return err;
187 	}
188 
189 	err = can_sja1000_init(dev);
190 	if (err != 0) {
191 		LOG_ERR("failed to initialize controller (err %d)", err);
192 		return err;
193 	}
194 
195 #ifndef CONFIG_SOC_SERIES_ESP32
196 	/*
197 	 * TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs
198 	 *   - TWAI_CD has length of 8 bits instead of 3 bits
199 	 *   - TWAI_CLOCK_OFF at BIT(8) instead of BIT(3)
200 	 *   - TWAI_EXT_MODE bit missing (always "extended" = PeliCAN mode)
201 	 *
202 	 * Overwrite with 32-bit register variant configured via devicetree.
203 	 */
204 	can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32);
205 #endif /* !CONFIG_SOC_SERIES_ESP32 */
206 
207 	err = esp_intr_alloc(twai_config->irq_source,
208 			ESP_PRIO_TO_FLAGS(twai_config->irq_priority) |
209 			ESP_INT_FLAGS_CHECK(twai_config->irq_flags) | ESP_INTR_FLAG_IRAM,
210 			can_esp32_twai_isr, (void *)dev, NULL);
211 
212 	if (err != 0) {
213 		LOG_ERR("could not allocate interrupt (err %d)", err);
214 	}
215 
216 	return err;
217 }
218 
219 DEVICE_API(can, can_esp32_twai_driver_api) = {
220 	.get_capabilities = can_sja1000_get_capabilities,
221 	.start = can_sja1000_start,
222 	.stop = can_sja1000_stop,
223 	.set_mode = can_sja1000_set_mode,
224 #ifdef CONFIG_SOC_SERIES_ESP32
225 	.set_timing = can_sja1000_set_timing,
226 #else
227 	.set_timing = can_esp32_twai_set_timing,
228 #endif /* CONFIG_SOC_SERIES_ESP32 */
229 	.send = can_sja1000_send,
230 	.add_rx_filter = can_sja1000_add_rx_filter,
231 	.remove_rx_filter = can_sja1000_remove_rx_filter,
232 	.get_state = can_sja1000_get_state,
233 	.set_state_change_callback = can_sja1000_set_state_change_callback,
234 	.get_core_clock = can_esp32_twai_get_core_clock,
235 	.get_max_filters = can_sja1000_get_max_filters,
236 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
237 	.recover = can_sja1000_recover,
238 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
239 	.timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER,
240 #ifdef CONFIG_SOC_SERIES_ESP32
241 	.timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER,
242 #else
243 	/* larger prescaler allowed for newer ESP32-series MCUs */
244 	.timing_max = {
245 		.sjw = 0x4,
246 		.prop_seg = 0x0,
247 		.phase_seg1 = 0x10,
248 		.phase_seg2 = 0x8,
249 		.prescaler = 0x2000,
250 	}
251 #endif /* CONFIG_SOC_SERIES_ESP32 */
252 };
253 
254 #ifdef CONFIG_SOC_SERIES_ESP32
255 #define TWAI_CLKOUT_DIVIDER_MAX (14)
256 #define TWAI_CDR32_INIT(inst)
257 #else
258 #define TWAI_CLKOUT_DIVIDER_MAX (490)
259 #define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)
260 #endif /* CONFIG_SOC_SERIES_ESP32 */
261 
262 #define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst)                                                 \
263 	BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1),                 \
264 		(DT_INST_PROP(inst, clkout_divider) == 1 ||                                        \
265 		(DT_INST_PROP(inst, clkout_divider) % 2 == 0 &&                                    \
266 		DT_INST_PROP(inst, clkout_divider) / 2 <= TWAI_CLKOUT_DIVIDER_MAX))),              \
267 		"TWAI clkout-divider from dts invalid")
268 
269 #define CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)                                                       \
270 	COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clkout_divider),                                   \
271 		    COND_CODE_1(DT_INST_PROP(inst, clkout_divider) == 1, (TWAI_CD_MASK),           \
272 				((DT_INST_PROP(inst, clkout_divider)) / 2 - 1)),                   \
273 		    (TWAI_CLOCK_OFF))
274 
275 #define CAN_ESP32_TWAI_INIT(inst)                                                                  \
276 	PINCTRL_DT_INST_DEFINE(inst);                                                              \
277                                                                                                    \
278 	static const struct can_esp32_twai_config can_esp32_twai_config_##inst = {                 \
279 		.base = DT_INST_REG_ADDR(inst),                                                    \
280 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
281 		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, offset),         \
282 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
283 		.irq_source = DT_INST_IRQ_BY_IDX(inst, 0, irq),                                    \
284 		.irq_priority = DT_INST_IRQ_BY_IDX(inst, 0, priority),                             \
285 		.irq_flags = DT_INST_IRQ_BY_IDX(inst, 0, flags),                                   \
286 		TWAI_CDR32_INIT(inst)                                                              \
287 	};                                                                                         \
288 	CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst);                                                \
289 	static const struct can_sja1000_config can_sja1000_config_##inst =                         \
290 		CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst,                \
291 					can_esp32_twai_read_reg, can_esp32_twai_write_reg,         \
292 					CAN_SJA1000_OCR_OCMODE_BIPHASE,                            \
293 					COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0),      \
294 					(CAN_ESP32_TWAI_DT_CDR_INST_GET(inst))), 25000);           \
295                                                                                                    \
296 	static struct can_sja1000_data can_sja1000_data_##inst =                                   \
297 		CAN_SJA1000_DATA_INITIALIZER(NULL);                                                \
298                                                                                                    \
299 	CAN_DEVICE_DT_INST_DEFINE(inst, can_esp32_twai_init, NULL, &can_sja1000_data_##inst,       \
300 				  &can_sja1000_config_##inst, POST_KERNEL,                         \
301 				  CONFIG_CAN_INIT_PRIORITY, &can_esp32_twai_driver_api);
302 
303 DT_INST_FOREACH_STATUS_OKAY(CAN_ESP32_TWAI_INIT)
304