1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8#include <zephyr/dt-bindings/clock/ra_clock.h>
9#include <zephyr/dt-bindings/pwm/ra_pwm.h>
10
11/ {
12	soc {
13		sram0: memory@20000000 {
14			compatible = "mmio-sram";
15			reg = <0x20000000 DT_SIZE_K(512)>;
16		};
17
18		ioport6: gpio@400800c0 {
19			compatible = "renesas,ra-gpio-ioport";
20			reg = <0x400800c0 0x20>;
21			port = <6>;
22			gpio-controller;
23			#gpio-cells = <2>;
24			ngpios = <16>;
25			status = "disabled";
26		};
27
28		ioport7: gpio@400800e0 {
29			compatible = "renesas,ra-gpio-ioport";
30			reg = <0x400800e0 0x20>;
31			port = <7>;
32			gpio-controller;
33			#gpio-cells = <2>;
34			ngpios = <16>;
35			status = "disabled";
36		};
37
38		ioport8: gpio@40080100 {
39			compatible = "renesas,ra-gpio-ioport";
40			reg = <0x40080100 0x20>;
41			port = <8>;
42			gpio-controller;
43			#gpio-cells = <2>;
44			ngpios = <16>;
45			status = "disabled";
46		};
47
48		ioport9: gpio@40080120 {
49			compatible = "renesas,ra-gpio-ioport";
50			reg = <0x40080120 0x20>;
51			port = <9>;
52			gpio-controller;
53			#gpio-cells = <2>;
54			ngpios = <16>;
55			status = "disabled";
56		};
57
58		ioporta: gpio@40080140 {
59			compatible = "renesas,ra-gpio-ioport";
60			reg = <0x40080140 0x20>;
61			port = <10>;
62			gpio-controller;
63			#gpio-cells = <2>;
64			ngpios = <16>;
65			status = "disabled";
66		};
67
68		ioportb: gpio@40080160 {
69			compatible = "renesas,ra-gpio-ioport";
70			reg = <0x40080160 0x20>;
71			port = <11>;
72			gpio-controller;
73			#gpio-cells = <2>;
74			ngpios = <16>;
75			status = "disabled";
76		};
77
78		sci1: sci1@40118100 {
79			compatible = "renesas,ra-sci";
80			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
81			interrupt-names = "rxi", "txi", "tei", "eri";
82			reg = <0x40118100 0x100>;
83			clocks = <&pclka MSTPB 30>;
84			status = "disabled";
85			uart {
86				compatible = "renesas,ra-sci-uart";
87				channel = <1>;
88				status = "disabled";
89			};
90		};
91
92		sci2: sci2@40118200 {
93			compatible = "renesas,ra-sci";
94			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
95			interrupt-names = "rxi", "txi", "tei", "eri";
96			reg = <0x40118200 0x100>;
97			clocks = <&pclka MSTPB 29>;
98			status = "disabled";
99			uart {
100				compatible = "renesas,ra-sci-uart";
101				channel = <2>;
102				status = "disabled";
103			};
104		};
105
106		sci3: sci3@40118300 {
107			compatible = "renesas,ra-sci";
108			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
109			interrupt-names = "rxi", "txi", "tei", "eri";
110			reg = <0x40118300 0x100>;
111			clocks = <&pclka MSTPB 28>;
112			status = "disabled";
113			uart {
114				compatible = "renesas,ra-sci-uart";
115				channel = <3>;
116				status = "disabled";
117			};
118		};
119
120		sci4: sci4@40118400 {
121			compatible = "renesas,ra-sci";
122			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
123			interrupt-names = "rxi", "txi", "tei", "eri";
124			reg = <0x40118400 0x100>;
125			clocks = <&pclka MSTPB 27>;
126			status = "disabled";
127			uart {
128				compatible = "renesas,ra-sci-uart";
129				channel = <4>;
130				status = "disabled";
131			};
132		};
133
134		sci5: sci5@40118500 {
135			compatible = "renesas,ra-sci";
136			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
137			interrupt-names = "rxi", "txi", "tei", "eri";
138			reg = <0x40118500 0x100>;
139			clocks = <&pclka MSTPB 26>;
140			status = "disabled";
141			uart {
142				compatible = "renesas,ra-sci-uart";
143				channel = <5>;
144				status = "disabled";
145			};
146		};
147
148		sci6: sci6@40118600 {
149			compatible = "renesas,ra-sci";
150			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
151			interrupt-names = "rxi", "txi", "tei", "eri";
152			reg = <0x40118600 0x100>;
153			clocks = <&pclka MSTPB 25>;
154			status = "disabled";
155			uart {
156				compatible = "renesas,ra-sci-uart";
157				channel = <6>;
158				status = "disabled";
159			};
160		};
161
162		sci7: sci7@40118700 {
163			compatible = "renesas,ra-sci";
164			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
165			interrupt-names = "rxi", "txi", "tei", "eri";
166			reg = <0x40118700 0x100>;
167			clocks = <&pclka MSTPB 24>;
168			status = "disabled";
169			uart {
170				compatible = "renesas,ra-sci-uart";
171				channel = <7>;
172				status = "disabled";
173			};
174		};
175
176		sci8: sci8@40118800 {
177			compatible = "renesas,ra-sci";
178			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
179			interrupt-names = "rxi", "txi", "tei", "eri";
180			reg = <0x40118800 0x100>;
181			clocks = <&pclka MSTPB 23>;
182			status = "disabled";
183			uart {
184				compatible = "renesas,ra-sci-uart";
185				channel = <8>;
186				status = "disabled";
187			};
188		};
189
190		iic2: iic2@4009f200 {
191			compatible = "renesas,ra-iic";
192			channel = <2>;
193			reg = <0x4009f200 0x100>;
194			status = "disabled";
195		};
196
197		usbhs: usbhs@40111000 {
198			compatible = "renesas,ra-usb";
199			reg = <0x40111000 0x2000>;
200			interrupts = <54 12>, <55 12>, <56 12>;
201			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
202			num-bidir-endpoints = <10>;
203			phys = <&usbhs_phy>;
204			status = "disabled";
205			udc {
206				compatible = "renesas,ra-udc";
207				status = "disabled";
208			};
209		};
210
211		adc@40170000 {
212			channel-count = <13>;
213			channel-available-mask = <0x37ff>;
214		};
215
216		adc@40170200 {
217			channel-count = <16>;
218			channel-available-mask = <0x1fff0007>;
219		};
220
221		pwm0: pwm0@40169000 {
222			compatible = "renesas,ra-pwm";
223			divider = <RA_PWM_SOURCE_DIV_1>;
224			channel = <RA_PWM_CHANNEL_0>;
225			clocks = <&pclkd MSTPE 31>;
226			reg = <0x40169000 0x100>;
227			#pwm-cells = <3>;
228			status = "disabled";
229		};
230
231		pwm3: pwm3@40169300 {
232			compatible = "renesas,ra-pwm";
233			divider = <RA_PWM_SOURCE_DIV_1>;
234			channel = <RA_PWM_CHANNEL_3>;
235			clocks = <&pclkd MSTPE 28>;
236			reg = <0x40169300 0x100>;
237			#pwm-cells = <3>;
238			status = "disabled";
239		};
240
241		pwm6: pwm6@40169600 {
242			compatible = "renesas,ra-pwm";
243			divider = <RA_PWM_SOURCE_DIV_1>;
244			channel = <RA_PWM_CHANNEL_6>;
245			clocks = <&pclkd MSTPE 25>;
246			reg = <0x40169600 0x100>;
247			#pwm-cells = <3>;
248			status = "disabled";
249		};
250
251		pwm7: pwm7@40169700 {
252			compatible = "renesas,ra-pwm";
253			divider = <RA_PWM_SOURCE_DIV_1>;
254			channel = <RA_PWM_CHANNEL_7>;
255			clocks = <&pclkd MSTPE 24>;
256			reg = <0x40169700 0x100>;
257			#pwm-cells = <3>;
258			status = "disabled";
259		};
260
261		pwm8: pwm8@40169800 {
262			compatible = "renesas,ra-pwm";
263			divider = <RA_PWM_SOURCE_DIV_1>;
264			channel = <RA_PWM_CHANNEL_8>;
265			clocks = <&pclkd MSTPE 23>;
266			reg = <0x40169800 0x100>;
267			#pwm-cells = <3>;
268			status = "disabled";
269		};
270
271		pwm9: pwm9@40169900 {
272			compatible = "renesas,ra-pwm";
273			divider = <RA_PWM_SOURCE_DIV_1>;
274			channel = <RA_PWM_CHANNEL_9>;
275			clocks = <&pclkd MSTPE 22>;
276			reg = <0x40169900 0x100>;
277			#pwm-cells = <3>;
278			status = "disabled";
279		};
280	};
281
282	clocks: clocks {
283		#address-cells = <1>;
284		#size-cells = <1>;
285
286		xtal: clock-main-osc {
287			compatible = "renesas,ra-cgc-external-clock";
288			clock-frequency = <DT_FREQ_M(24)>;
289			#clock-cells = <0>;
290			status = "disabled";
291		};
292
293		hoco: clock-hoco {
294			compatible = "fixed-clock";
295			clock-frequency = <DT_FREQ_M(20)>;
296			#clock-cells = <0>;
297		};
298
299		moco: clock-moco {
300			compatible = "fixed-clock";
301			clock-frequency = <DT_FREQ_M(8)>;
302			#clock-cells = <0>;
303		};
304
305		loco: clock-loco {
306			compatible = "fixed-clock";
307			clock-frequency = <32768>;
308			#clock-cells = <0>;
309		};
310
311		subclk: clock-subclk {
312			compatible = "renesas,ra-cgc-subclk";
313			clock-frequency = <32768>;
314			#clock-cells = <0>;
315			status = "disabled";
316		};
317
318		pll: pll {
319			compatible = "renesas,ra-cgc-pll";
320			#clock-cells = <0>;
321
322			/* PLL */
323			clocks = <&xtal>;
324			div = <3>;
325			mul = <25 0>;
326			status = "disabled";
327		};
328
329		pll2: pll2 {
330			compatible = "renesas,ra-cgc-pll";
331			#clock-cells = <0>;
332
333			/* PLL2 */
334			div = <2>;
335			mul = <20 0>;
336			status = "disabled";
337		};
338
339		pclkblock: pclkblock@40084000 {
340			compatible = "renesas,ra-cgc-pclk-block";
341			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
342			      <0x4008400c 4>, <0x40084010 4>;
343			reg-names = "MSTPA", "MSTPB","MSTPC",
344				    "MSTPD", "MSTPE";
345			#clock-cells = <0>;
346			clocks = <&pll>;
347			status = "okay";
348
349			iclk: iclk {
350				compatible = "renesas,ra-cgc-pclk";
351				div = <1>;
352				#clock-cells = <2>;
353				status = "okay";
354			};
355
356			pclka: pclka {
357				compatible = "renesas,ra-cgc-pclk";
358				div = <2>;
359				#clock-cells = <2>;
360				status = "okay";
361			};
362
363			pclkb: pclkb {
364				compatible = "renesas,ra-cgc-pclk";
365				div = <4>;
366				#clock-cells = <2>;
367				status = "okay";
368			};
369
370			pclkc: pclkc {
371				compatible = "renesas,ra-cgc-pclk";
372				div = <4>;
373				#clock-cells = <2>;
374				status = "okay";
375			};
376
377			pclkd: pclkd {
378				compatible = "renesas,ra-cgc-pclk";
379				div = <2>;
380				#clock-cells = <2>;
381				status = "okay";
382			};
383
384			bclk: bclk {
385				compatible = "renesas,ra-cgc-pclk";
386				div = <2>;
387				bclkout: bclkout {
388					compatible = "renesas,ra-cgc-busclk";
389					clk-out-div = <2>;
390					sdclk = <0>;
391					#clock-cells = <0>;
392				};
393				#clock-cells = <2>;
394				status = "okay";
395			};
396
397			fclk: fclk {
398				compatible = "renesas,ra-cgc-pclk";
399				div = <4>;
400				#clock-cells = <2>;
401				status = "okay";
402			};
403
404			clkout: clkout {
405				compatible = "renesas,ra-cgc-pclk";
406				#clock-cells = <2>;
407				status = "disabled";
408			};
409
410			uclk: uclk {
411				compatible = "renesas,ra-cgc-pclk";
412				#clock-cells = <2>;
413				status = "disabled";
414			};
415
416			u60clk: u60clk {
417				compatible = "renesas,ra-cgc-pclk";
418				#clock-cells = <2>;
419				status = "disabled";
420			};
421
422			octaspiclk: octaspiclk {
423				compatible = "renesas,ra-cgc-pclk";
424				#clock-cells = <2>;
425				status = "disabled";
426			};
427
428			canfdclk: canfdclk {
429				compatible = "renesas,ra-cgc-pclk";
430				#clock-cells = <2>;
431				status = "disabled";
432			};
433
434			cecclk: cecclk {
435				compatible = "renesas,ra-cgc-pclk";
436				#clock-cells = <2>;
437				status = "disabled";
438			};
439		};
440	};
441
442	usbhs_phy: usbhs-phy {
443		compatible = "renesas,ra-usbphyc";
444		#phy-cells = <0>;
445	};
446};
447
448&ioport0 {
449	port-irqs = <&port_irq6 &port_irq7 &port_irq8
450	&port_irq9 &port_irq10 &port_irq11
451	&port_irq12 &port_irq13 &port_irq14>;
452	port-irq-names = "port-irq6",
453			 "port-irq7",
454			 "port-irq8",
455			 "port-irq9",
456			 "port-irq10",
457			 "port-irq11",
458			 "port-irq12",
459			 "port-irq13",
460			 "port-irq14";
461	port-irq6-pins = <0>;
462	port-irq7-pins = <1>;
463	port-irq8-pins = <2>;
464	port-irq9-pins = <4>;
465	port-irq10-pins = <5>;
466	port-irq11-pins = <6>;
467	port-irq12-pins = <8>;
468	port-irq13-pins = <9 15>;
469	port-irq14-pins = <10>;
470};
471
472&ioport1 {
473	port-irqs = <&port_irq0 &port_irq1 &port_irq2
474	&port_irq3 &port_irq4>;
475	port-irq-names = "port-irq0",
476			 "port-irq1",
477			 "port-irq2",
478			 "port-irq3",
479			 "port-irq4";
480	port-irq0-pins = <5>;
481	port-irq1-pins = <1 4>;
482	port-irq2-pins = <0>;
483	port-irq3-pins = <10>;
484	port-irq4-pins = <11>;
485};
486
487&ioport2 {
488	port-irqs = <&port_irq0 &port_irq1 &port_irq2
489	&port_irq3>;
490	port-irq-names = "port-irq0",
491			 "port-irq1",
492			 "port-irq2",
493			 "port-irq3";
494	port-irq0-pins = <6>;
495	port-irq1-pins = <5>;
496	port-irq2-pins = <3 13>;
497	port-irq3-pins = <2 12>;
498};
499
500&ioport3 {
501	port-irqs = <&port_irq5 &port_irq6
502	&port_irq8 &port_irq9>;
503	port-irq-names = "port-irq5",
504			 "port-irq6",
505			 "port-irq8",
506			 "port-irq9";
507	port-irq5-pins = <2>;
508	port-irq6-pins = <1>;
509	port-irq8-pins = <5>;
510	port-irq9-pins = <4>;
511};
512
513&ioport4 {
514	port-irqs = <&port_irq0 &port_irq4 &port_irq5
515	&port_irq6 &port_irq7 &port_irq8
516	&port_irq9 &port_irq14 &port_irq15>;
517	port-irq-names = "port-irq0",
518			 "port-irq4",
519			 "port-irq5",
520			 "port-irq6",
521			 "port-irq7",
522			 "port-irq8",
523			 "port-irq9",
524			 "port-irq14",
525			 "port-irq15";
526	port-irq0-pins = <0>;
527	port-irq4-pins = <2 11>;
528	port-irq5-pins = <1 10>;
529	port-irq6-pins = <9>;
530	port-irq7-pins = <8>;
531	port-irq8-pins = <15>;
532	port-irq9-pins = <14>;
533	port-irq14-pins = <3>;
534	port-irq15-pins = <4>;
535};
536
537&ioport5 {
538	port-irqs = <&port_irq11 &port_irq12 &port_irq14
539	&port_irq15>;
540	port-irq-names = "port-irq11",
541			 "port-irq12",
542			 "port-irq14",
543			 "port-irq15";
544	port-irq11-pins = <1>;
545	port-irq12-pins = <2>;
546	port-irq14-pins = <5 12>;
547	port-irq15-pins = <6 11>;
548};
549
550&ioport6 {
551	port-irqs = <&port_irq7>;
552	port-irq-names = "port-irq7";
553	port-irq7-pins = <15>;
554};
555
556&ioport7 {
557	port-irqs = <&port_irq7 &port_irq8 &port_irq10
558	&port_irq11>;
559	port-irq-names = "port-irq7",
560			 "port-irq8",
561			 "port-irq10",
562			 "port-irq11";
563	port-irq7-pins = <6>;
564	port-irq8-pins = <7>;
565	port-irq10-pins = <9>;
566	port-irq11-pins = <8>;
567};
568
569&ioport8 {
570	port-irqs = <&port_irq0 &port_irq1 &port_irq2
571	&port_irq3>;
572	port-irq-names = "port-irq0",
573			 "port-irq1",
574			 "port-irq2",
575			 "port-irq3";
576	port-irq0-pins = <6>;
577	port-irq1-pins = <4>;
578	port-irq2-pins = <3>;
579	port-irq3-pins = <2>;
580};
581
582&ioport9 {
583	port-irqs = <&port_irq8 &port_irq9 &port_irq10
584	&port_irq11>;
585	port-irq-names = "port-irq8",
586			 "port-irq9",
587			 "port-irq10",
588			 "port-irq11";
589	port-irq8-pins = <5>;
590	port-irq9-pins = <6>;
591	port-irq10-pins = <7>;
592	port-irq11-pins = <8>;
593};
594
595&ioporta {
596	port-irqs = <&port_irq4 &port_irq5 &port_irq6>;
597	port-irq-names = "port-irq4",
598			 "port-irq5",
599			 "port-irq6";
600	port-irq4-pins = <10>;
601	port-irq5-pins = <9>;
602	port-irq6-pins = <8>;
603};
604