Lines Matching +full:clkout +full:- +full:divider
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
9 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
14 compatible = "mmio-sram";
19 compatible = "renesas,ra-sci";
21 interrupt-names = "rxi", "txi", "tei", "eri";
26 compatible = "renesas,ra-sci-uart";
33 compatible = "renesas,ra-sci";
35 interrupt-names = "rxi", "txi", "tei", "eri";
40 compatible = "renesas,ra-sci-uart";
47 compatible = "renesas,ra-sci";
49 interrupt-names = "rxi", "txi", "tei", "eri";
54 compatible = "renesas,ra-sci-uart";
61 compatible = "renesas,ra-sci";
63 interrupt-names = "rxi", "txi", "tei", "eri";
68 compatible = "renesas,ra-sci-uart";
75 compatible = "renesas,ra-sci";
77 interrupt-names = "rxi", "txi", "tei", "eri";
82 compatible = "renesas,ra-sci-uart";
89 compatible = "renesas,ra-sci";
91 interrupt-names = "rxi", "txi", "tei", "eri";
96 compatible = "renesas,ra-sci-uart";
103 compatible = "renesas,ra-sci";
105 interrupt-names = "rxi", "txi", "tei", "eri";
110 compatible = "renesas,ra-sci-uart";
117 compatible = "renesas,ra-sci";
119 interrupt-names = "rxi", "txi", "tei", "eri";
124 compatible = "renesas,ra-sci-uart";
131 channel-count = <12>;
132 channel-available-mask = <0x33ff>;
136 channel-count = <10>;
137 channel-available-mask = <0x7f0007>;
141 compatible = "renesas,ra-gpio-ioport";
144 gpio-controller;
145 #gpio-cells = <2>;
151 compatible = "renesas,ra-gpio-ioport";
154 gpio-controller;
155 #gpio-cells = <2>;
161 compatible = "renesas,ra-gpio-ioport";
164 gpio-controller;
165 #gpio-cells = <2>;
171 compatible = "renesas,ra-pwm";
172 divider = <RA_PWM_SOURCE_DIV_1>;
176 #pwm-cells = <3>;
181 compatible = "renesas,ra-pwm";
182 divider = <RA_PWM_SOURCE_DIV_1>;
186 #pwm-cells = <3>;
191 compatible = "renesas,ra-pwm";
192 divider = <RA_PWM_SOURCE_DIV_1>;
196 #pwm-cells = <3>;
201 compatible = "renesas,ra-pwm";
202 divider = <RA_PWM_SOURCE_DIV_1>;
206 #pwm-cells = <3>;
211 compatible = "renesas,ra-pwm";
212 divider = <RA_PWM_SOURCE_DIV_1>;
216 #pwm-cells = <3>;
221 compatible = "renesas,ra-pwm";
222 divider = <RA_PWM_SOURCE_DIV_1>;
226 #pwm-cells = <3>;
232 #address-cells = <1>;
233 #size-cells = <1>;
235 xtal: clock-main-osc {
236 compatible = "renesas,ra-cgc-external-clock";
237 clock-frequency = <DT_FREQ_M(24)>;
238 #clock-cells = <0>;
242 hoco: clock-hoco {
243 compatible = "fixed-clock";
244 clock-frequency = <DT_FREQ_M(20)>;
245 #clock-cells = <0>;
248 moco: clock-moco {
249 compatible = "fixed-clock";
250 clock-frequency = <DT_FREQ_M(8)>;
251 #clock-cells = <0>;
254 loco: clock-loco {
255 compatible = "fixed-clock";
256 clock-frequency = <32768>;
257 #clock-cells = <0>;
260 subclk: clock-subclk {
261 compatible = "renesas,ra-cgc-subclk";
262 clock-frequency = <32768>;
263 #clock-cells = <0>;
268 compatible = "renesas,ra-cgc-pll";
269 #clock-cells = <0>;
279 compatible = "renesas,ra-cgc-pll";
280 #clock-cells = <0>;
289 compatible = "renesas,ra-cgc-pclk-block";
292 reg-names = "MSTPA", "MSTPB","MSTPC",
294 #clock-cells = <0>;
299 compatible = "renesas,ra-cgc-pclk";
301 #clock-cells = <2>;
306 compatible = "renesas,ra-cgc-pclk";
308 #clock-cells = <2>;
313 compatible = "renesas,ra-cgc-pclk";
315 #clock-cells = <2>;
320 compatible = "renesas,ra-cgc-pclk";
322 #clock-cells = <2>;
327 compatible = "renesas,ra-cgc-pclk";
329 #clock-cells = <2>;
334 compatible = "renesas,ra-cgc-pclk";
337 compatible = "renesas,ra-cgc-busclk";
338 clk-out-div = <2>;
340 #clock-cells = <0>;
342 #clock-cells = <2>;
347 compatible = "renesas,ra-cgc-pclk";
349 #clock-cells = <2>;
353 clkout: clkout { label
354 compatible = "renesas,ra-cgc-pclk";
355 #clock-cells = <2>;
360 compatible = "renesas,ra-cgc-pclk";
361 #clock-cells = <2>;
366 compatible = "renesas,ra-cgc-pclk";
367 #clock-cells = <2>;
375 port-irqs = <&port_irq6 &port_irq7 &port_irq8
378 port-irq-names = "port-irq6",
379 "port-irq7",
380 "port-irq8",
381 "port-irq9",
382 "port-irq10",
383 "port-irq11",
384 "port-irq12",
385 "port-irq13";
386 port-irq6-pins = <0>;
387 port-irq7-pins = <1>;
388 port-irq8-pins = <2>;
389 port-irq9-pins = <4>;
390 port-irq10-pins = <5>;
391 port-irq11-pins = <6>;
392 port-irq12-pins = <8>;
393 port-irq13-pins = <9 15>;
397 port-irqs = <&port_irq0 &port_irq1 &port_irq2
399 port-irq-names = "port-irq0",
400 "port-irq1",
401 "port-irq2",
402 "port-irq3",
403 "port-irq4";
404 port-irq0-pins = <5>;
405 port-irq1-pins = <1 4>;
406 port-irq2-pins = <0>;
407 port-irq3-pins = <10>;
408 port-irq4-pins = <11>;
412 port-irqs = <&port_irq0 &port_irq1 &port_irq2
414 port-irq-names = "port-irq0",
415 "port-irq1",
416 "port-irq2",
417 "port-irq3";
418 port-irq0-pins = <6>;
419 port-irq1-pins = <5>;
420 port-irq2-pins = <3 13>;
421 port-irq3-pins = <2 12>;
425 port-irqs = <&port_irq5 &port_irq6
427 port-irq-names = "port-irq5",
428 "port-irq6",
429 "port-irq8",
430 "port-irq9";
431 port-irq5-pins = <2>;
432 port-irq6-pins = <1>;
433 port-irq8-pins = <5>;
434 port-irq9-pins = <4>;
438 port-irqs = <&port_irq0 &port_irq4 &port_irq5
441 port-irq-names = "port-irq0",
442 "port-irq4",
443 "port-irq5",
444 "port-irq6",
445 "port-irq7",
446 "port-irq8",
447 "port-irq9",
448 "port-irq14",
449 "port-irq15";
450 port-irq0-pins = <0>;
451 port-irq4-pins = <2 11>;
452 port-irq5-pins = <1 10>;
453 port-irq6-pins = <9>;
454 port-irq7-pins = <8>;
455 port-irq8-pins = <15>;
456 port-irq9-pins = <14>;
457 port-irq14-pins = <3>;
458 port-irq15-pins = <4>;
462 port-irqs = <&port_irq11 &port_irq12 &port_irq14
464 port-irq-names = "port-irq11",
465 "port-irq12",
466 "port-irq14",
467 "port-irq15";
468 port-irq11-pins = <1>;
469 port-irq12-pins = <2>;
470 port-irq14-pins = <5 12>;
471 port-irq15-pins = <6 11>;
475 port-irqs = <&port_irq10 &port_irq11>;
476 port-irq-names = "port-irq10",
477 "port-irq11";
478 port-irq10-pins = <9>;
479 port-irq11-pins = <8>;