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Searched refs:RCC_AHB1ENR_DMA2EN (Results 1 – 25 of 124) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
432 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
449 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
456 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
Dstm32f4xx_ll_bus.h105 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h496 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
498 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
527 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
552 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RE…
568 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == R…
Dstm32f2xx_ll_bus.h82 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h526 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
528 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
574 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
1245 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
1259 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
Dstm32g4xx_ll_bus.h74 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
664 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
710 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
1368 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
1383 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
Dstm32l5xx_ll_bus.h72 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
649 … tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
710 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
1648 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
1671 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
Dstm32l4xx_ll_bus.h74 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h980 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
982 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
1075 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
1102 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) …
1123 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) …
2726 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2728 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2806 #define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
3755 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
3757 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
[all …]
Dstm32h7xx_ll_bus.h123 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h605 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
607 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
729 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
1454 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
1476 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
Dstm32f7xx_ll_bus.h89 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_bus.h78 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_bus.h76 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
/hal_stm32-3.5.0/stm32cube/stm32f4xx/soc/
Dstm32f410tx.h4585 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32f410rx.h4608 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32f410cx.h4604 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32f401xc.h4291 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32f401xe.h4291 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32f411xe.h4303 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
/hal_stm32-3.5.0/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h6236 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32wle5xx.h6236 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro
Dstm32wl54xx.h7110 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk macro

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