1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L5xx_HAL_RCC_H 20 #define STM32L5xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l5xx_hal_def.h" 28 29 /** @addtogroup STM32L5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCC_Exported_Types RCC Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 58 59 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 60 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 61 62 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 63 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 64 65 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 66 User has to set the PLLR parameter correctly to not exceed max frequency 110MHZ. 67 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 68 69 } RCC_PLLInitTypeDef; 70 71 /** 72 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 73 */ 74 typedef struct 75 { 76 uint32_t OscillatorType; /*!< The oscillators to be configured. 77 This parameter can be a value of @ref RCC_Oscillator_Type */ 78 79 uint32_t HSEState; /*!< The new state of the HSE. 80 This parameter can be a value of @ref RCC_HSE_Config */ 81 82 uint32_t LSEState; /*!< The new state of the LSE. 83 This parameter can be a value of @ref RCC_LSE_Config */ 84 85 uint32_t HSIState; /*!< The new state of the HSI. 86 This parameter can be a value of @ref RCC_HSI_Config */ 87 88 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 89 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ 90 91 uint32_t LSIState; /*!< The new state of the LSI. 92 This parameter can be a value of @ref RCC_LSI_Config */ 93 94 uint32_t LSIDiv; /*!< The division factor of the LSI. 95 This parameter can be a value of @ref RCC_LSI_Div */ 96 97 uint32_t MSIState; /*!< The new state of the MSI. 98 This parameter can be a value of @ref RCC_MSI_Config */ 99 100 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 101 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 102 103 uint32_t MSIClockRange; /*!< The MSI frequency range. 104 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 105 106 uint32_t HSI48State; /*!< The new state of the HSI48. 107 This parameter can be a value of @ref RCC_HSI48_Config */ 108 109 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 110 111 } RCC_OscInitTypeDef; 112 113 /** 114 * @brief RCC System, AHB and APB buses clock configuration structure definition 115 */ 116 typedef struct 117 { 118 uint32_t ClockType; /*!< The clock to be configured. 119 This parameter can be a value of @ref RCC_System_Clock_Type */ 120 121 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 122 This parameter can be a value of @ref RCC_System_Clock_Source */ 123 124 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 125 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 126 127 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 128 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 129 130 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 131 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 132 133 } RCC_ClkInitTypeDef; 134 135 /** 136 * @} 137 */ 138 139 /* Exported constants --------------------------------------------------------*/ 140 /** @defgroup RCC_Exported_Constants RCC Exported Constants 141 * @{ 142 */ 143 144 /** @defgroup RCC_Timeout_Value Timeout Values 145 * @{ 146 */ 147 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 148 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 149 /** 150 * @} 151 */ 152 153 /** @defgroup RCC_Oscillator_Type Oscillator Type 154 * @{ 155 */ 156 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 157 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 158 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 159 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 160 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 161 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 162 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup RCC_HSE_Config HSE Config 168 * @{ 169 */ 170 #define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ 171 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 172 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 173 /** 174 * @} 175 */ 176 177 /** @defgroup RCC_LSE_Config LSE Config 178 * @{ 179 */ 180 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 181 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 182 #define RCC_LSE_ON ((uint32_t)(RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< LSE clock activation for RCC and peripherals */ 183 #define RCC_LSE_BYPASS_RTC_ONLY ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 184 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 185 /** 186 * @} 187 */ 188 189 /** @defgroup RCC_HSI_Config HSI Config 190 * @{ 191 */ 192 #define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ 193 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 194 195 #define RCC_HSICALIBRATION_DEFAULT 0x00000040U /* Default HSI calibration trimming value */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup RCC_LSI_Config LSI Config 201 * @{ 202 */ 203 #define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ 204 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup RCC_LSI_Div LSI Div 210 * @{ 211 */ 212 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 213 #define RCC_LSI_DIV128 RCC_CSR_LSIPRE /*!< LSI clock is divided by 128 */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup RCC_MSI_Config MSI Config 219 * @{ 220 */ 221 #define RCC_MSI_OFF 0U /*!< MSI clock deactivation */ 222 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 223 224 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup RCC_HSI48_Config HSI48 Config 230 * @{ 231 */ 232 #define RCC_HSI48_OFF 0U /*!< HSI48 clock deactivation */ 233 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_PLL_Config PLL Config 239 * @{ 240 */ 241 #define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ 242 #define RCC_PLL_OFF 1U /*!< PLL deactivation */ 243 #define RCC_PLL_ON 2U /*!< PLL activation */ 244 /** 245 * @} 246 */ 247 248 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 249 * @{ 250 */ 251 #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ 252 #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ 253 #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ 254 #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ 255 #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ 256 #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ 257 #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ 258 #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ 259 #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ 260 #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ 261 #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ 262 #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ 263 #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ 264 #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ 265 #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ 266 #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 272 * @{ 273 */ 274 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 275 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 276 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 277 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 278 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 279 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 280 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 281 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 282 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 283 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 284 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 285 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 286 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 287 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 288 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 289 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 290 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 291 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 292 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 293 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 294 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 295 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 296 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 297 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 298 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 299 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 300 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 301 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 302 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 303 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 304 /** 305 * @} 306 */ 307 308 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 309 * @{ 310 */ 311 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 312 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 313 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 314 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 320 * @{ 321 */ 322 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 323 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 324 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 325 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 331 * @{ 332 */ 333 #define RCC_PLLSOURCE_NONE 0U /*!< No clock selected as PLL entry clock source */ 334 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ 335 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ 336 #define RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 342 * @{ 343 */ 344 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL */ 345 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 346 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup RCC_PLLSAI1_Clock_Source PLLSAI1 Clock Source 352 * @{ 353 */ 354 #define RCC_PLLSAI1SOURCE_NONE 0U /*!< No clock selected as PLLSAI1 entry clock source */ 355 #define RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_0 /*!< MSI clock selected as PLLSAI1 entry clock source */ 356 #define RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_1 /*!< HSI clock selected as PLLSAI1 entry clock source */ 357 #define RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_1 | RCC_PLLSAI1CFGR_PLLSAI1SRC_0) /*!< HSE clock selected as PLLSAI1 entry clock source */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 363 * @{ 364 */ 365 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 366 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 367 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup RCC_PLLSAI2_Clock_Source PLLSAI2 Clock Source 373 * @{ 374 */ 375 #define RCC_PLLSAI2SOURCE_NONE 0U /*!< No clock selected as PLLSAI2 entry clock source */ 376 #define RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_0 /*!< MSI clock selected as PLLSAI2 entry clock source */ 377 #define RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_1 /*!< HSI clock selected as PLLSAI2 entry clock source */ 378 #define RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_1 | RCC_PLLSAI2CFGR_PLLSAI2SRC_0) /*!< HSE clock selected as PLLSAI2 entry clock source */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 384 * @{ 385 */ 386 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 387 /** 388 * @} 389 */ 390 391 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 392 * @{ 393 */ 394 #define RCC_MSIRANGE_0 0UL /*!< MSI = 100 kHz */ 395 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_0 /*!< MSI = 200 kHz */ 396 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_1 /*!< MSI = 400 kHz */ 397 #define RCC_MSIRANGE_3 (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 800 kHz */ 398 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_2 /*!< MSI = 1 MHz */ 399 #define RCC_MSIRANGE_5 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0) /*!< MSI = 2 MHz */ 400 #define RCC_MSIRANGE_6 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1) /*!< MSI = 4 MHz */ 401 #define RCC_MSIRANGE_7 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 8 MHz */ 402 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_3 /*!< MSI = 16 MHz */ 403 #define RCC_MSIRANGE_9 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0) /*!< MSI = 24 MHz */ 404 #define RCC_MSIRANGE_10 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1) /*!< MSI = 32 MHz */ 405 #define RCC_MSIRANGE_11 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 48 MHz */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup RCC_System_Clock_Type System Clock Type 411 * @{ 412 */ 413 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 414 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 415 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 416 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup RCC_System_Clock_Source System Clock Source 422 * @{ 423 */ 424 #define RCC_SYSCLKSOURCE_MSI 0UL /*!< MSI selection as system clock */ 425 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ 426 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ 427 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW /*!< PLL selection as system clock */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 433 * @{ 434 */ 435 #define RCC_SYSCLKSOURCE_STATUS_MSI 0UL /*!< MSI used as system clock */ 436 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ 437 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ 438 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS /*!< PLL used as system clock */ 439 /** 440 * @} 441 */ 442 443 /** @defgroup RCC_AHBx_Clock_Source AHBx Clock Source 444 * @{ 445 */ 446 #define RCC_SYSCLK_DIV1 0UL /*!< SYSCLK not divided */ 447 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ 448 #define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ 449 #define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ 450 #define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ 451 #define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ 452 #define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ 453 #define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ 454 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 512 */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 460 * @{ 461 */ 462 #define RCC_HCLK_DIV1 0UL /*!< HCLK not divided */ 463 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_2 /*!< HCLK divided by 2 */ 464 #define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK divided by 4 */ 465 #define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK divided by 8 */ 466 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1 /*!< HCLK divided by 16 */ 467 /** 468 * @} 469 */ 470 471 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 472 * @{ 473 */ 474 #define RCC_RTCCLKSOURCE_NONE 0U /*!< No clock used as RTC clock */ 475 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 476 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 477 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 478 /** 479 * @} 480 */ 481 482 /** @defgroup RCC_MCO_Index MCO Index 483 * @{ 484 */ 485 #define RCC_MCO1 0U 486 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 487 /** 488 * @} 489 */ 490 491 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 492 * @{ 493 */ 494 #define RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO1 output disabled, no clock on MCO1 */ 495 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 496 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 497 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 498 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 499 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 500 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 501 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 502 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 508 * @{ 509 */ 510 #define RCC_MCODIV_1 0UL /*!< MCO not divided */ 511 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ 512 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ 513 #define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ 514 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup RCC_Interrupt Interrupts 520 * @{ 521 */ 522 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 523 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 524 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 525 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 526 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 527 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 528 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 529 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 530 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 531 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup RCC_Flag Flags 537 * Elements values convention: XXXYYYYYb 538 * - YYYYY : Flag position in the register 539 * - XXX : Register index 540 * - 001: CR register 541 * - 010: BDCR register 542 * - 011: CSR register 543 * - 100: CRRCR register 544 * @{ 545 */ 546 /* Flags in the CR register */ 547 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 548 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 549 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 550 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 551 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 552 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 553 554 /* Flags in the BDCR register */ 555 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 556 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 557 558 /* Flags in the CSR register */ 559 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 560 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 561 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 562 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 563 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 564 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 565 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 566 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 567 568 /* Flags in the CRRCR register */ 569 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 575 * @{ 576 */ 577 #define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ 578 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 579 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 580 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 586 * @{ 587 */ 588 #define RCC_STOP_WAKEUPCLOCK_MSI 0U /*!< MSI selection after wake-up from STOP */ 589 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCC_items RCC items 595 * @brief RCC items to configure attributes on 596 * @{ 597 */ 598 #define RCC_HSI RCC_SECCFGR_HSISEC 599 #define RCC_HSE RCC_SECCFGR_HSESEC 600 #define RCC_MSI RCC_SECCFGR_MSISEC 601 #define RCC_LSI RCC_SECCFGR_LSISEC 602 #define RCC_LSE RCC_SECCFGR_LSESEC 603 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 604 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 605 #define RCC_PRESCALER RCC_SECCFGR_PRESCSEC 606 #define RCC_PLL RCC_SECCFGR_PLLSEC 607 #define RCC_PLLSAI1 RCC_SECCFGR_PLLSAI1SEC 608 #define RCC_PLLSAI2 RCC_SECCFGR_PLLSAI2SEC 609 #define RCC_CLK48M RCC_SECCFGR_CLK48MSEC 610 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 611 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 612 RCC_SYSCLK|RCC_PRESCALER|RCC_PLL|RCC_PLLSAI1| \ 613 RCC_PLLSAI2|RCC_CLK48M|RCC_RMVF) 614 /** 615 * @} 616 */ 617 618 /** @defgroup RCC_attributes RCC attributes 619 * @brief RCC secure/non-secure and privilege/non-privilege attributes 620 * @note secure and non-secure attributes are only available from secure state when the system 621 * implement the security (TZEN=1) 622 * @{ 623 */ 624 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 625 #define RCC_SEC (RCC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 626 #define RCC_NSEC (RCC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 627 #endif /* __ARM_FEATURE_CMSE */ 628 #define RCC_PRIV (RCC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 629 #define RCC_NPRIV (RCC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 630 /** 631 * @} 632 */ 633 634 /** 635 * @} 636 */ 637 638 /* Exported macros -----------------------------------------------------------*/ 639 640 /** @defgroup RCC_Exported_Macros RCC Exported Macros 641 * @{ 642 */ 643 644 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 645 * @brief Enable or disable the AHB1 peripheral clock. 646 * @note After reset, the peripheral clock (used for registers read/write access) 647 * is disabled and the application software has to enable this clock before 648 * using it. 649 * @{ 650 */ 651 652 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 653 __IO uint32_t tmpreg; \ 654 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 655 /* Delay after an RCC peripheral clock enabling */ \ 656 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 657 UNUSED(tmpreg); \ 658 } while(0) 659 660 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 661 __IO uint32_t tmpreg; \ 662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 663 /* Delay after an RCC peripheral clock enabling */ \ 664 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 665 UNUSED(tmpreg); \ 666 } while(0) 667 668 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 669 __IO uint32_t tmpreg; \ 670 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 671 /* Delay after an RCC peripheral clock enabling */ \ 672 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 673 UNUSED(tmpreg); \ 674 } while(0) 675 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 676 __IO uint32_t tmpreg; \ 677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 678 /* Delay after an RCC peripheral clock enabling */ \ 679 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 680 UNUSED(tmpreg); \ 681 } while(0) 682 683 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 684 __IO uint32_t tmpreg; \ 685 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 686 /* Delay after an RCC peripheral clock enabling */ \ 687 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 688 UNUSED(tmpreg); \ 689 } while(0) 690 691 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 692 __IO uint32_t tmpreg; \ 693 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 694 /* Delay after an RCC peripheral clock enabling */ \ 695 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 696 UNUSED(tmpreg); \ 697 } while(0) 698 699 #define __HAL_RCC_GTZC_CLK_ENABLE() do { \ 700 __IO uint32_t tmpreg; \ 701 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ 702 /* Delay after an RCC peripheral clock enabling */ \ 703 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ 704 UNUSED(tmpreg); \ 705 } while(0) 706 707 708 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 709 710 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 711 712 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 713 714 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 715 716 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 717 718 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 719 720 #define __HAL_RCC_GTZC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) 721 722 /** 723 * @} 724 */ 725 726 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 727 * @brief Enable or disable the AHB2 peripheral clock. 728 * @note After reset, the peripheral clock (used for registers read/write access) 729 * is disabled and the application software has to enable this clock before 730 * using it. 731 * @{ 732 */ 733 734 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 735 __IO uint32_t tmpreg; \ 736 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 737 /* Delay after an RCC peripheral clock enabling */ \ 738 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 739 UNUSED(tmpreg); \ 740 } while(0) 741 742 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 743 __IO uint32_t tmpreg; \ 744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 745 /* Delay after an RCC peripheral clock enabling */ \ 746 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 747 UNUSED(tmpreg); \ 748 } while(0) 749 750 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 751 __IO uint32_t tmpreg; \ 752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 753 /* Delay after an RCC peripheral clock enabling */ \ 754 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 755 UNUSED(tmpreg); \ 756 } while(0) 757 758 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 759 __IO uint32_t tmpreg; \ 760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 761 /* Delay after an RCC peripheral clock enabling */ \ 762 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 763 UNUSED(tmpreg); \ 764 } while(0) 765 766 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 767 __IO uint32_t tmpreg; \ 768 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 769 /* Delay after an RCC peripheral clock enabling */ \ 770 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 771 UNUSED(tmpreg); \ 772 } while(0) 773 774 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 775 __IO uint32_t tmpreg; \ 776 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 777 /* Delay after an RCC peripheral clock enabling */ \ 778 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 779 UNUSED(tmpreg); \ 780 } while(0) 781 782 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 783 __IO uint32_t tmpreg; \ 784 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 785 /* Delay after an RCC peripheral clock enabling */ \ 786 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 787 UNUSED(tmpreg); \ 788 } while(0) 789 790 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 791 __IO uint32_t tmpreg; \ 792 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 793 /* Delay after an RCC peripheral clock enabling */ \ 794 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 795 UNUSED(tmpreg); \ 796 } while(0) 797 798 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 799 __IO uint32_t tmpreg; \ 800 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 801 /* Delay after an RCC peripheral clock enabling */ \ 802 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 803 UNUSED(tmpreg); \ 804 } while(0) 805 806 #if defined(AES) 807 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 808 __IO uint32_t tmpreg; \ 809 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 810 /* Delay after an RCC peripheral clock enabling */ \ 811 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 812 UNUSED(tmpreg); \ 813 } while(0) 814 #endif /* AES */ 815 816 #if defined(HASH) 817 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 818 __IO uint32_t tmpreg; \ 819 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 820 /* Delay after an RCC peripheral clock enabling */ \ 821 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 822 UNUSED(tmpreg); \ 823 } while(0) 824 #endif /* HASH */ 825 826 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 827 __IO uint32_t tmpreg; \ 828 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 829 /* Delay after an RCC peripheral clock enabling */ \ 830 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 831 UNUSED(tmpreg); \ 832 } while(0) 833 834 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 835 __IO uint32_t tmpreg; \ 836 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 837 /* Delay after an RCC peripheral clock enabling */ \ 838 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 839 UNUSED(tmpreg); \ 840 } while(0) 841 842 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 843 __IO uint32_t tmpreg; \ 844 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ 845 /* Delay after an RCC peripheral clock enabling */ \ 846 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ 847 UNUSED(tmpreg); \ 848 } while(0) 849 850 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 851 __IO uint32_t tmpreg; \ 852 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 853 /* Delay after an RCC peripheral clock enabling */ \ 854 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 855 UNUSED(tmpreg); \ 856 } while(0) 857 858 859 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 860 861 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 862 863 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 864 865 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 866 867 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 868 869 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 870 871 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 872 873 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 874 875 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 876 877 #if defined(AES) 878 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 879 #endif /* AES */ 880 881 #if defined(HASH) 882 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 883 #endif /* HASH */ 884 885 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 886 887 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 888 889 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN) 890 891 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 892 893 /** 894 * @} 895 */ 896 897 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 898 * @brief Enable or disable the AHB3 peripheral clock. 899 * @note After reset, the peripheral clock (used for registers read/write access) 900 * is disabled and the application software has to enable this clock before 901 * using it. 902 * @{ 903 */ 904 905 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 906 __IO uint32_t tmpreg; \ 907 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 908 /* Delay after an RCC peripheral clock enabling */ \ 909 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 910 UNUSED(tmpreg); \ 911 } while(0) 912 913 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 914 __IO uint32_t tmpreg; \ 915 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 916 /* Delay after an RCC peripheral clock enabling */ \ 917 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 918 UNUSED(tmpreg); \ 919 } while(0) 920 921 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 922 923 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 924 925 /** 926 * @} 927 */ 928 929 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 930 * @brief Enable or disable the APB1 peripheral clock. 931 * @note After reset, the peripheral clock (used for registers read/write access) 932 * is disabled and the application software has to enable this clock before 933 * using it. 934 * @{ 935 */ 936 937 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 938 __IO uint32_t tmpreg; \ 939 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 940 /* Delay after an RCC peripheral clock enabling */ \ 941 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 942 UNUSED(tmpreg); \ 943 } while(0) 944 945 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 946 __IO uint32_t tmpreg; \ 947 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 948 /* Delay after an RCC peripheral clock enabling */ \ 949 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 950 UNUSED(tmpreg); \ 951 } while(0) 952 953 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 954 __IO uint32_t tmpreg; \ 955 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 956 /* Delay after an RCC peripheral clock enabling */ \ 957 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 958 UNUSED(tmpreg); \ 959 } while(0) 960 961 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 962 __IO uint32_t tmpreg; \ 963 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 964 /* Delay after an RCC peripheral clock enabling */ \ 965 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 966 UNUSED(tmpreg); \ 967 } while(0) 968 969 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 970 __IO uint32_t tmpreg; \ 971 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 972 /* Delay after an RCC peripheral clock enabling */ \ 973 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 974 UNUSED(tmpreg); \ 975 } while(0) 976 977 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 978 __IO uint32_t tmpreg; \ 979 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 980 /* Delay after an RCC peripheral clock enabling */ \ 981 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 982 UNUSED(tmpreg); \ 983 } while(0) 984 985 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 986 __IO uint32_t tmpreg; \ 987 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 988 /* Delay after an RCC peripheral clock enabling */ \ 989 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 990 UNUSED(tmpreg); \ 991 } while(0) 992 993 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 994 __IO uint32_t tmpreg; \ 995 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 996 /* Delay after an RCC peripheral clock enabling */ \ 997 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 998 UNUSED(tmpreg); \ 999 } while(0) 1000 1001 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1002 __IO uint32_t tmpreg; \ 1003 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1004 /* Delay after an RCC peripheral clock enabling */ \ 1005 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1006 UNUSED(tmpreg); \ 1007 } while(0) 1008 1009 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1010 __IO uint32_t tmpreg; \ 1011 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1012 /* Delay after an RCC peripheral clock enabling */ \ 1013 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1014 UNUSED(tmpreg); \ 1015 } while(0) 1016 1017 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1018 __IO uint32_t tmpreg; \ 1019 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1020 /* Delay after an RCC peripheral clock enabling */ \ 1021 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1022 UNUSED(tmpreg); \ 1023 } while(0) 1024 1025 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1026 __IO uint32_t tmpreg; \ 1027 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1028 /* Delay after an RCC peripheral clock enabling */ \ 1029 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1030 UNUSED(tmpreg); \ 1031 } while(0) 1032 1033 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1034 __IO uint32_t tmpreg; \ 1035 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1036 /* Delay after an RCC peripheral clock enabling */ \ 1037 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1038 UNUSED(tmpreg); \ 1039 } while(0) 1040 1041 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1042 __IO uint32_t tmpreg; \ 1043 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1044 /* Delay after an RCC peripheral clock enabling */ \ 1045 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1046 UNUSED(tmpreg); \ 1047 } while(0) 1048 1049 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1050 __IO uint32_t tmpreg; \ 1051 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1052 /* Delay after an RCC peripheral clock enabling */ \ 1053 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1054 UNUSED(tmpreg); \ 1055 } while(0) 1056 1057 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1058 __IO uint32_t tmpreg; \ 1059 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1060 /* Delay after an RCC peripheral clock enabling */ \ 1061 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1062 UNUSED(tmpreg); \ 1063 } while(0) 1064 1065 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1066 __IO uint32_t tmpreg; \ 1067 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1068 /* Delay after an RCC peripheral clock enabling */ \ 1069 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1070 UNUSED(tmpreg); \ 1071 } while(0) 1072 1073 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1074 __IO uint32_t tmpreg; \ 1075 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1076 /* Delay after an RCC peripheral clock enabling */ \ 1077 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1078 UNUSED(tmpreg); \ 1079 } while(0) 1080 1081 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1082 __IO uint32_t tmpreg; \ 1083 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1084 /* Delay after an RCC peripheral clock enabling */ \ 1085 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1086 UNUSED(tmpreg); \ 1087 } while(0) 1088 1089 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1090 __IO uint32_t tmpreg; \ 1091 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1092 /* Delay after an RCC peripheral clock enabling */ \ 1093 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1094 UNUSED(tmpreg); \ 1095 } while(0) 1096 1097 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1098 __IO uint32_t tmpreg; \ 1099 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1100 /* Delay after an RCC peripheral clock enabling */ \ 1101 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1102 UNUSED(tmpreg); \ 1103 } while(0) 1104 1105 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1106 __IO uint32_t tmpreg; \ 1107 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1108 /* Delay after an RCC peripheral clock enabling */ \ 1109 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1110 UNUSED(tmpreg); \ 1111 } while(0) 1112 1113 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1114 __IO uint32_t tmpreg; \ 1115 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1116 /* Delay after an RCC peripheral clock enabling */ \ 1117 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1118 UNUSED(tmpreg); \ 1119 } while(0) 1120 1121 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1122 __IO uint32_t tmpreg; \ 1123 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1124 /* Delay after an RCC peripheral clock enabling */ \ 1125 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1126 UNUSED(tmpreg); \ 1127 } while(0) 1128 1129 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1130 __IO uint32_t tmpreg; \ 1131 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1132 /* Delay after an RCC peripheral clock enabling */ \ 1133 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1134 UNUSED(tmpreg); \ 1135 } while(0) 1136 1137 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1138 __IO uint32_t tmpreg; \ 1139 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ 1140 /* Delay after an RCC peripheral clock enabling */ \ 1141 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ 1142 UNUSED(tmpreg); \ 1143 } while(0) 1144 1145 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1146 __IO uint32_t tmpreg; \ 1147 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1148 /* Delay after an RCC peripheral clock enabling */ \ 1149 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1150 UNUSED(tmpreg); \ 1151 } while(0) 1152 1153 #if defined(USB) 1154 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1155 __IO uint32_t tmpreg; \ 1156 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ 1157 /* Delay after an RCC peripheral clock enabling */ \ 1158 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ 1159 UNUSED(tmpreg); \ 1160 } while(0) 1161 #endif /* USB */ 1162 1163 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1164 __IO uint32_t tmpreg; \ 1165 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1166 /* Delay after an RCC peripheral clock enabling */ \ 1167 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1168 UNUSED(tmpreg); \ 1169 } while(0) 1170 1171 1172 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1173 1174 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1175 1176 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1177 1178 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1179 1180 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1181 1182 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1183 1184 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1185 1186 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1187 1188 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1189 1190 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1191 1192 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1193 1194 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1195 1196 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1197 1198 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1199 1200 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1201 1202 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1203 1204 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1205 1206 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1207 1208 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1209 1210 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 1211 1212 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 1213 1214 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1215 1216 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1217 1218 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1219 1220 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) 1221 1222 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1223 1224 #if defined(USB) 1225 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); 1226 #endif /* USB */ 1227 1228 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); 1229 1230 /** 1231 * @} 1232 */ 1233 1234 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1235 * @brief Enable or disable the APB2 peripheral clock. 1236 * @note After reset, the peripheral clock (used for registers read/write access) 1237 * is disabled and the application software has to enable this clock before 1238 * using it. 1239 * @{ 1240 */ 1241 1242 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1243 __IO uint32_t tmpreg; \ 1244 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1245 /* Delay after an RCC peripheral clock enabling */ \ 1246 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1247 UNUSED(tmpreg); \ 1248 } while(0) 1249 1250 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1251 __IO uint32_t tmpreg; \ 1252 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1253 /* Delay after an RCC peripheral clock enabling */ \ 1254 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1255 UNUSED(tmpreg); \ 1256 } while(0) 1257 1258 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1259 __IO uint32_t tmpreg; \ 1260 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1261 /* Delay after an RCC peripheral clock enabling */ \ 1262 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1263 UNUSED(tmpreg); \ 1264 } while(0) 1265 1266 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1267 __IO uint32_t tmpreg; \ 1268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1269 /* Delay after an RCC peripheral clock enabling */ \ 1270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1271 UNUSED(tmpreg); \ 1272 } while(0) 1273 1274 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1275 __IO uint32_t tmpreg; \ 1276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1277 /* Delay after an RCC peripheral clock enabling */ \ 1278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1279 UNUSED(tmpreg); \ 1280 } while(0) 1281 1282 1283 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1284 __IO uint32_t tmpreg; \ 1285 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1286 /* Delay after an RCC peripheral clock enabling */ \ 1287 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1288 UNUSED(tmpreg); \ 1289 } while(0) 1290 1291 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1292 __IO uint32_t tmpreg; \ 1293 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1294 /* Delay after an RCC peripheral clock enabling */ \ 1295 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1296 UNUSED(tmpreg); \ 1297 } while(0) 1298 1299 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1300 __IO uint32_t tmpreg; \ 1301 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1302 /* Delay after an RCC peripheral clock enabling */ \ 1303 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1304 UNUSED(tmpreg); \ 1305 } while(0) 1306 1307 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1308 __IO uint32_t tmpreg; \ 1309 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1310 /* Delay after an RCC peripheral clock enabling */ \ 1311 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1312 UNUSED(tmpreg); \ 1313 } while(0) 1314 1315 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1316 __IO uint32_t tmpreg; \ 1317 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1318 /* Delay after an RCC peripheral clock enabling */ \ 1319 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1320 UNUSED(tmpreg); \ 1321 } while(0) 1322 1323 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1324 __IO uint32_t tmpreg; \ 1325 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1326 /* Delay after an RCC peripheral clock enabling */ \ 1327 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1328 UNUSED(tmpreg); \ 1329 } while(0) 1330 1331 1332 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1333 1334 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1335 1336 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1337 1338 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1339 1340 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1341 1342 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1343 1344 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1345 1346 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1347 1348 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1349 1350 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1351 1352 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 1353 1354 /** 1355 * @} 1356 */ 1357 1358 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1359 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1360 * @note After reset, the peripheral clock (used for registers read/write access) 1361 * is disabled and the application software has to enable this clock before 1362 * using it. 1363 * @{ 1364 */ 1365 1366 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1367 1368 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1369 1370 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1371 1372 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1373 1374 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1375 1376 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1377 1378 #define __HAL_RCC_GTZC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) != 0U) 1379 1380 1381 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1382 1383 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1384 1385 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1386 1387 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1388 1389 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1390 1391 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1392 1393 #define __HAL_RCC_GTZC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) == 0U) 1394 1395 /** 1396 * @} 1397 */ 1398 1399 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1400 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1401 * @note After reset, the peripheral clock (used for registers read/write access) 1402 * is disabled and the application software has to enable this clock before 1403 * using it. 1404 * @{ 1405 */ 1406 1407 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1408 1409 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1410 1411 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1412 1413 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1414 1415 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1416 1417 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1418 1419 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1420 1421 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1422 1423 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 1424 1425 #if defined(AES) 1426 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1427 #endif /* AES */ 1428 1429 #if defined(HASH) 1430 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1431 #endif /* HASH */ 1432 1433 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1434 1435 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 1436 1437 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1438 1439 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1440 1441 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1442 1443 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1444 1445 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1446 1447 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1448 1449 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1450 1451 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 1452 1453 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 1454 1455 #if defined(AES) 1456 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1457 #endif /* AES */ 1458 1459 #if defined(HASH) 1460 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 1461 #endif /* HASH */ 1462 1463 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1464 1465 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 1466 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1472 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1473 * @note After reset, the peripheral clock (used for registers read/write access) 1474 * is disabled and the application software has to enable this clock before 1475 * using it. 1476 * @{ 1477 */ 1478 1479 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1480 1481 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1482 1483 /** 1484 * @} 1485 */ 1486 1487 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1488 * @brief Check whether the APB1 peripheral clock is enabled or not. 1489 * @note After reset, the peripheral clock (used for registers read/write access) 1490 * is disabled and the application software has to enable this clock before 1491 * using it. 1492 * @{ 1493 */ 1494 1495 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1496 1497 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1498 1499 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1500 1501 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1502 1503 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1504 1505 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1506 1507 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1508 1509 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1510 1511 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1512 1513 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1514 1515 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1516 1517 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1518 1519 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1520 1521 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1522 1523 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1524 1525 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1526 1527 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1528 1529 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1530 1531 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1532 1533 #if defined(USB) 1534 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 1535 #endif /* USB */ 1536 1537 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1538 1539 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 1540 1541 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 1542 1543 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1544 1545 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1546 1547 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1548 1549 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) != 0U) 1550 1551 1552 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1553 1554 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1555 1556 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1557 1558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1559 1560 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1561 1562 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1563 1564 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 1565 1566 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 1567 1568 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1569 1570 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 1571 1572 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1573 1574 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1575 1576 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1577 1578 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1579 1580 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1581 1582 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1583 1584 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 1585 1586 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1587 1588 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1589 1590 #if defined(USB) 1591 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 1592 #endif /* USB */ 1593 1594 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 1595 1596 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 1597 1598 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 1599 1600 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 1601 1602 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 1603 1604 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 1605 1606 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) == 0U) 1607 1608 /** 1609 * @} 1610 */ 1611 1612 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1613 * @brief Check whether the APB2 peripheral clock is enabled or not. 1614 * @note After reset, the peripheral clock (used for registers read/write access) 1615 * is disabled and the application software has to enable this clock before 1616 * using it. 1617 * @{ 1618 */ 1619 1620 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 1621 1622 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 1623 1624 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 1625 1626 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 1627 1628 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 1629 1630 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 1631 1632 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 1633 1634 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 1635 1636 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 1637 1638 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 1639 1640 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 1641 1642 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 1643 1644 1645 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 1646 1647 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 1648 1649 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 1650 1651 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 1652 1653 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 1654 1655 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 1656 1657 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 1658 1659 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 1660 1661 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 1662 1663 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 1664 1665 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 1666 1667 /** 1668 * @} 1669 */ 1670 1671 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1672 * @brief Force or release AHB1 peripheral reset. 1673 * @{ 1674 */ 1675 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL) 1676 1677 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1678 1679 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1680 1681 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1682 1683 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1684 1685 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1686 1687 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1688 1689 1690 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL) 1691 1692 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1693 1694 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1695 1696 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1697 1698 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1699 1700 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1701 1702 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1703 1704 /** 1705 * @} 1706 */ 1707 1708 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1709 * @brief Force or release AHB2 peripheral reset. 1710 * @{ 1711 */ 1712 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL) 1713 1714 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1715 1716 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1717 1718 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1719 1720 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1721 1722 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1723 1724 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1725 1726 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1727 1728 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1729 1730 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 1731 1732 #if defined(AES) 1733 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1734 #endif /* AES */ 1735 1736 #if defined(HASH) 1737 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1738 #endif /* HASH */ 1739 1740 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1741 1742 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1743 1744 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) 1745 1746 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 1747 1748 1749 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL) 1750 1751 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1752 1753 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1754 1755 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1756 1757 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1758 1759 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1760 1761 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1762 1763 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1764 1765 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1766 1767 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 1768 1769 #if defined(AES) 1770 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1771 #endif /* AES */ 1772 1773 #if defined(HASH) 1774 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1775 #endif /* HASH */ 1776 1777 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1778 1779 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1780 1781 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) 1782 1783 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 1784 1785 /** 1786 * @} 1787 */ 1788 1789 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1790 * @brief Force or release AHB3 peripheral reset. 1791 * @{ 1792 */ 1793 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL) 1794 1795 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1796 1797 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 1798 1799 1800 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL) 1801 1802 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1803 1804 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 1805 1806 /** 1807 * @} 1808 */ 1809 1810 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1811 * @brief Force or release APB1 peripheral reset. 1812 * @{ 1813 */ 1814 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1815 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ 1816 WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ 1817 } while(0) 1818 1819 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1820 1821 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1822 1823 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1824 1825 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1826 1827 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1828 1829 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1830 1831 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1832 1833 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1834 1835 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1836 1837 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1838 1839 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1840 1841 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1842 1843 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1844 1845 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1846 1847 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1848 1849 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1850 1851 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1852 1853 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1854 1855 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 1856 1857 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 1858 1859 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1860 1861 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1862 1863 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1864 1865 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM3RST) 1866 1867 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 1868 1869 #if defined(USB) 1870 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_USBFSRST) 1871 #endif /* USB */ 1872 1873 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1874 1875 1876 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1877 WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ 1878 WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ 1879 } while(0) 1880 1881 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1882 1883 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1884 1885 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1886 1887 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1888 1889 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1890 1891 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1892 1893 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1894 1895 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1896 1897 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1898 1899 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1900 1901 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1902 1903 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1904 1905 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1906 1907 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1908 1909 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1910 1911 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1912 1913 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1914 1915 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1916 1917 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 1918 1919 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 1920 1921 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1922 1923 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1924 1925 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1926 1927 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM3RST) 1928 1929 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 1930 1931 #if defined(USB) 1932 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_USBFSRST) 1933 #endif /* USB */ 1934 1935 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1936 1937 /** 1938 * @} 1939 */ 1940 1941 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1942 * @brief Force or release APB2 peripheral reset. 1943 * @{ 1944 */ 1945 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL) 1946 1947 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1948 1949 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1950 1951 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1952 1953 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1954 1955 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1956 1957 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1958 1959 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1960 1961 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1962 1963 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1964 1965 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 1966 1967 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 1968 1969 1970 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL) 1971 1972 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1973 1974 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1975 1976 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1977 1978 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1979 1980 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1981 1982 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1983 1984 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1985 1986 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1987 1988 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1989 1990 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 1991 1992 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 1993 1994 /** 1995 * @} 1996 */ 1997 1998 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1999 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2000 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2001 * power consumption. 2002 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2003 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2004 * @{ 2005 */ 2006 2007 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2008 2009 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2010 2011 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2012 2013 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2014 2015 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2016 2017 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2018 2019 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2020 2021 #define __HAL_RCC_GTZC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) 2022 2023 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2024 2025 2026 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2027 2028 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2029 2030 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2031 2032 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2033 2034 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2035 2036 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2037 2038 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2039 2040 #define __HAL_RCC_GTZC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) 2041 2042 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2043 2044 /** 2045 * @} 2046 */ 2047 2048 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2049 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2050 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2051 * power consumption. 2052 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2053 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2054 * @{ 2055 */ 2056 2057 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2058 2059 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2060 2061 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2062 2063 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2064 2065 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2066 2067 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2068 2069 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2070 2071 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2072 2073 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2074 2075 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2076 2077 #if defined(AES) 2078 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2079 #endif /* AES */ 2080 2081 #if defined(HASH) 2082 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2083 #endif /* HASH */ 2084 2085 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2086 2087 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2088 2089 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) 2090 2091 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2092 2093 2094 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2095 2096 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2097 2098 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2099 2100 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2101 2102 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2103 2104 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2105 2106 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2107 2108 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2109 2110 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2111 2112 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2113 2114 #if defined(AES) 2115 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2116 #endif /* AES */ 2117 2118 #if defined(HASH) 2119 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2120 #endif /* HASH */ 2121 2122 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2123 2124 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2125 2126 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) 2127 2128 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2129 2130 /** 2131 * @} 2132 */ 2133 2134 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2135 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2136 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2137 * power consumption. 2138 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2139 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2140 * @{ 2141 */ 2142 2143 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2144 2145 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2146 2147 2148 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2149 2150 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2151 2152 /** 2153 * @} 2154 */ 2155 2156 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2157 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2158 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2159 * power consumption. 2160 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2161 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2162 * @{ 2163 */ 2164 2165 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2166 2167 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2168 2169 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2170 2171 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2172 2173 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2174 2175 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2176 2177 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2178 2179 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2180 2181 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2182 2183 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2184 2185 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2186 2187 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2188 2189 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2190 2191 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2192 2193 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2194 2195 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2196 2197 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2198 2199 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2200 2201 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2202 2203 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2204 2205 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 2206 2207 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 2208 2209 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2210 2211 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2212 2213 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2214 2215 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) 2216 2217 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2218 2219 #if defined(USB) 2220 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_USBFSSMEN) 2221 #endif /* USB */ 2222 2223 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2224 2225 2226 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2227 2228 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2229 2230 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2231 2232 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2233 2234 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2235 2236 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2237 2238 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2239 2240 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2241 2242 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2243 2244 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2245 2246 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2247 2248 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2249 2250 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2251 2252 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2253 2254 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2255 2256 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2257 2258 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2259 2260 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2261 2262 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2263 2264 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2265 2266 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 2267 2268 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 2269 2270 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2271 2272 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2273 2274 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2275 2276 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) 2277 2278 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2279 2280 #if defined(USB) 2281 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_USBFSSMEN) 2282 #endif /* USB */ 2283 2284 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2285 2286 /** 2287 * @} 2288 */ 2289 2290 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2291 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2292 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2293 * power consumption. 2294 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2295 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2296 * @{ 2297 */ 2298 2299 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2300 2301 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2302 2303 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2304 2305 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2306 2307 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2308 2309 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2310 2311 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2312 2313 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2314 2315 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2316 2317 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2318 2319 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 2320 2321 2322 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2323 2324 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2325 2326 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2327 2328 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2329 2330 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2331 2332 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2333 2334 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2335 2336 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2337 2338 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2339 2340 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2341 2342 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 2343 2344 /** 2345 * @} 2346 */ 2347 2348 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2349 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2350 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2351 * power consumption. 2352 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2353 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2354 * @{ 2355 */ 2356 2357 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 2358 2359 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 2360 2361 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 2362 2363 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 2364 2365 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 2366 2367 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 2368 2369 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 2370 2371 #define __HAL_RCC_GTZC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) != 0U) 2372 2373 2374 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 2375 2376 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 2377 2378 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 2379 2380 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 2381 2382 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 2383 2384 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 2385 2386 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 2387 2388 #define __HAL_RCC_GTZC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) == 0U) 2389 2390 /** 2391 * @} 2392 */ 2393 2394 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2395 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2396 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2397 * power consumption. 2398 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2399 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2400 * @{ 2401 */ 2402 2403 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 2404 2405 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 2406 2407 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 2408 2409 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 2410 2411 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 2412 2413 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 2414 2415 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 2416 2417 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 2418 2419 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 2420 2421 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 2422 2423 #if defined(AES) 2424 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 2425 #endif /* AES */ 2426 2427 #if defined(HASH) 2428 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 2429 #endif /* HASH */ 2430 2431 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 2432 2433 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 2434 2435 2436 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 2437 2438 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 2439 2440 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 2441 2442 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 2443 2444 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 2445 2446 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 2447 2448 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 2449 2450 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 2451 2452 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 2453 2454 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 2455 2456 #if defined(AES) 2457 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 2458 #endif /* AES */ 2459 2460 #if defined(HASH) 2461 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 2462 #endif /* HASH */ 2463 2464 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 2465 2466 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 2467 2468 /** 2469 * @} 2470 */ 2471 2472 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2473 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2474 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2475 * power consumption. 2476 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2477 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2478 * @{ 2479 */ 2480 2481 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 2482 2483 2484 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 2485 2486 /** 2487 * @} 2488 */ 2489 2490 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2491 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2492 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2493 * power consumption. 2494 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2495 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2496 * @{ 2497 */ 2498 2499 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 2500 2501 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 2502 2503 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 2504 2505 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 2506 2507 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 2508 2509 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 2510 2511 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 2512 2513 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 2514 2515 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 2516 2517 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 2518 2519 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 2520 2521 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 2522 2523 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 2524 2525 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 2526 2527 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 2528 2529 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 2530 2531 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 2532 2533 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 2534 2535 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 2536 2537 #if defined(USB) 2538 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 2539 #endif /* USB */ 2540 2541 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 2542 2543 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 2544 2545 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 2546 2547 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 2548 2549 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 2550 2551 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 2552 2553 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) != 0U) 2554 2555 2556 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 2557 2558 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 2559 2560 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 2561 2562 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 2563 2564 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 2565 2566 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 2567 2568 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 2569 2570 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 2571 2572 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 2573 2574 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 2575 2576 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 2577 2578 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 2579 2580 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 2581 2582 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 2583 2584 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 2585 2586 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 2587 2588 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 2589 2590 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 2591 2592 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 2593 2594 #if defined(USB) 2595 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 2596 #endif /* USB */ 2597 2598 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 2599 2600 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 2601 2602 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 2603 2604 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 2605 2606 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 2607 2608 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 2609 2610 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) == 0U) 2611 2612 /** 2613 * @} 2614 */ 2615 2616 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2617 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2618 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2619 * power consumption. 2620 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2621 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2622 * @{ 2623 */ 2624 2625 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 2626 2627 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 2628 2629 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 2630 2631 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 2632 2633 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 2634 2635 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 2636 2637 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 2638 2639 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 2640 2641 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 2642 2643 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 2644 2645 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 2646 2647 2648 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 2649 2650 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 2651 2652 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 2653 2654 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 2655 2656 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 2657 2658 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 2659 2660 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 2661 2662 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 2663 2664 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 2665 2666 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 2667 2668 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 2669 2670 /** 2671 * @} 2672 */ 2673 2674 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2675 * @{ 2676 */ 2677 2678 /** @brief Macros to force or release the Backup domain reset. 2679 * @note This function resets the RTC peripheral (including the backup registers) 2680 * and the RTC clock source selection in RCC_CSR register. 2681 * @note The BKPSRAM is not affected by this reset. 2682 * @retval None 2683 */ 2684 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2685 2686 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2687 2688 /** 2689 * @} 2690 */ 2691 2692 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2693 * @{ 2694 */ 2695 2696 /** @brief Macros to enable or disable the RTC clock. 2697 * @note As the RTC is in the Backup domain and write access is denied to 2698 * this domain after reset, you have to enable write access using 2699 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2700 * (to be done once after reset). 2701 * @note These macros must be used after the RTC clock source was selected. 2702 * @retval None 2703 */ 2704 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2705 2706 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2707 2708 /** 2709 * @} 2710 */ 2711 2712 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 2713 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2714 * It is used (enabled by hardware) as system clock source after startup 2715 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2716 * of the HSE used directly or indirectly as system clock (if the Clock 2717 * Security System CSS is enabled). 2718 * @note HSI can not be stopped if it is used as system clock source. In this case, 2719 * you have to select another source of the system clock then stop the HSI. 2720 * @note After enabling the HSI, the application software should wait on HSIRDY 2721 * flag to be set indicating that HSI clock is stable and can be used as 2722 * system clock source. 2723 * This parameter can be: ENABLE or DISABLE. 2724 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2725 * clock cycles. 2726 * @retval None 2727 */ 2728 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 2729 2730 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 2731 2732 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 2733 * @note The calibration is used to compensate for the variations in voltage 2734 * and temperature that influence the frequency of the internal HSI RC. 2735 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2736 * (default is RCC_HSICALIBRATION_DEFAULT). 2737 * This parameter must be a number between 0 and 0x7F. 2738 * @retval None 2739 */ 2740 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2741 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 2742 2743 /** 2744 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2745 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2746 * @note The enable of this function has not effect on the HSION bit. 2747 * This parameter can be: ENABLE or DISABLE. 2748 * @retval None 2749 */ 2750 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 2751 2752 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 2753 2754 /** 2755 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2756 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2757 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2758 * speed because of the HSI startup time. 2759 * @note The enable of this function has not effect on the HSION bit. 2760 * This parameter can be: ENABLE or DISABLE. 2761 * @retval None 2762 */ 2763 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 2764 2765 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 2766 2767 /** 2768 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2769 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2770 * It is used (enabled by hardware) as system clock source after 2771 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2772 * of failure of the HSE used directly or indirectly as system clock 2773 * (if the Clock Security System CSS is enabled). 2774 * @note MSI can not be stopped if it is used as system clock source. 2775 * In this case, you have to select another source of the system 2776 * clock then stop the MSI. 2777 * @note After enabling the MSI, the application software should wait on 2778 * MSIRDY flag to be set indicating that MSI clock is stable and can 2779 * be used as system clock source. 2780 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2781 * clock cycles. 2782 * @retval None 2783 */ 2784 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 2785 2786 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 2787 2788 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 2789 * @note The calibration is used to compensate for the variations in voltage 2790 * and temperature that influence the frequency of the internal MSI RC. 2791 * Refer to the Application Note AN3300 for more details on how to 2792 * calibrate the MSI. 2793 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2794 * (default is RCC_MSICALIBRATION_DEFAULT). 2795 * This parameter must be a number between 0 and 255. 2796 * @retval None 2797 */ 2798 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 2799 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) 2800 2801 /** 2802 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2803 * @note After restart from Reset , the MSI clock is around 4 MHz. 2804 * After stop the startup clock can be MSI (at any of its possible 2805 * frequencies, the one that was used before entering stop mode) or HSI. 2806 * After Standby its frequency can be selected between 4 possible values 2807 * (1, 2, 4 or 8 MHz). 2808 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2809 * (MSIRDY=1). 2810 * @note The MSI clock range after reset can be modified on the fly. 2811 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2812 * This parameter must be one of the following values: 2813 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz 2814 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz 2815 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz 2816 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz 2817 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2818 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2819 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2820 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2821 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2822 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2823 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2824 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2825 * @retval None 2826 */ 2827 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 2828 do { \ 2829 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 2830 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 2831 } while(0) 2832 2833 /** 2834 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 2835 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 2836 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2837 * This parameter must be one of the following values: 2838 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2839 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2840 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2841 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2842 * @retval None 2843 */ 2844 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 2845 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 2846 2847 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2848 * @retval MSI clock range. 2849 * This parameter must be one of the following values: 2850 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz 2851 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz 2852 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz 2853 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz 2854 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2855 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2856 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2857 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2858 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2859 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2860 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2861 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2862 */ 2863 #define __HAL_RCC_GET_MSI_RANGE() \ 2864 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 2865 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ 2866 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) 2867 2868 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2869 * @note After enabling the LSI, the application software should wait on 2870 * LSIRDY flag to be set indicating that LSI clock is stable and can 2871 * be used to clock the IWDG and/or the RTC. 2872 * @note LSI can not be disabled if the IWDG is running. 2873 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2874 * clock cycles. 2875 * @retval None 2876 */ 2877 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 2878 2879 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 2880 2881 /** 2882 * @brief Macro to configure the External High Speed oscillator (HSE). 2883 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2884 * supported by this macro. User should request a transition to HSE Off 2885 * first and then HSE On or HSE Bypass. 2886 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2887 * software should wait on HSERDY flag to be set indicating that HSE clock 2888 * is stable and can be used to clock the PLL and/or system clock. 2889 * @note HSE state can not be changed if it is used directly or through the 2890 * PLL as system clock. In this case, you have to select another source 2891 * of the system clock then change the HSE state (ex. disable it). 2892 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2893 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2894 * was previously enabled you have to enable it again after calling this 2895 * function. 2896 * @param __STATE__ specifies the new state of the HSE. 2897 * This parameter can be one of the following values: 2898 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2899 * 6 HSE oscillator clock cycles. 2900 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2901 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2902 * @retval None 2903 */ 2904 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2905 do { \ 2906 if((__STATE__) == RCC_HSE_ON) \ 2907 { \ 2908 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2909 } \ 2910 else if((__STATE__) == RCC_HSE_BYPASS) \ 2911 { \ 2912 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2913 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2914 } \ 2915 else \ 2916 { \ 2917 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 2918 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2919 } \ 2920 } while(0) 2921 2922 /** 2923 * @brief Macro to configure the External Low Speed oscillator (LSE). 2924 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2925 * supported by this macro. User should request a transition to LSE Off 2926 * first and then LSE On or LSE Bypass. 2927 * @note As the LSE is in the Backup domain and write access is denied to 2928 * this domain after reset, you have to enable write access using 2929 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2930 * (to be done once after reset). 2931 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2932 * software should wait on LSERDY flag to be set indicating that LSE clock 2933 * is stable and can be used to clock the RTC. 2934 * @param __STATE__ specifies the new state of the LSE. 2935 * This parameter can be one of the following values: 2936 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2937 * 6 LSE oscillator clock cycles. 2938 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2939 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2940 * @retval None 2941 */ 2942 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2943 do { \ 2944 if((__STATE__) == RCC_LSE_ON) \ 2945 { \ 2946 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2947 } \ 2948 else if((__STATE__) == RCC_LSE_BYPASS) \ 2949 { \ 2950 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2951 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2952 } \ 2953 else \ 2954 { \ 2955 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2956 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2957 } \ 2958 } while(0) 2959 2960 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2961 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2962 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2963 * flag to be set indicating that HSI48 clock is stable. 2964 * This parameter can be: ENABLE or DISABLE. 2965 * @retval None 2966 */ 2967 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2968 2969 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2970 2971 /** @brief Macros to configure the RTC clock (RTCCLK). 2972 * @note As the RTC clock configuration bits are in the Backup domain and write 2973 * access is denied to this domain after reset, you have to enable write 2974 * access using the Power Backup Access macro before to configure 2975 * the RTC clock source (to be done once after reset). 2976 * @note Once the RTC clock is configured it cannot be changed unless the 2977 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2978 * a Power On Reset (POR). 2979 * 2980 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2981 * This parameter can be one of the following values: 2982 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2983 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2984 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2985 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2986 * 2987 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2988 * work in STOP and STANDBY modes, and can be used as wakeup source. 2989 * However, when the HSE clock is used as RTC clock source, the RTC 2990 * cannot be used in STOP and STANDBY modes. 2991 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2992 * RTC clock source). 2993 * @retval None 2994 */ 2995 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 2996 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 2997 2998 2999 /** @brief Macro to get the RTC clock source. 3000 * @retval The returned value can be one of the following: 3001 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 3002 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3003 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3004 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3005 */ 3006 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 3007 3008 /** @brief Macros to enable or disable the main PLL. 3009 * @note After enabling the main PLL, the application software should wait on 3010 * PLLRDY flag to be set indicating that PLL clock is stable and can 3011 * be used as system clock source. 3012 * @note The main PLL can not be disabled if it is used as system clock source 3013 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3014 * @retval None 3015 */ 3016 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 3017 3018 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 3019 3020 /** @brief Macro to configure the PLL clock source. 3021 * @note This function must be used only when the main PLL is disabled. 3022 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3023 * This parameter can be one of the following values: 3024 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3025 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3026 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3027 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3028 * @retval None 3029 * 3030 */ 3031 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 3032 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 3033 3034 /** @brief Macro to configure the PLL source division factor M. 3035 * @note This function must be used only when the main PLL is disabled. 3036 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3037 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 3038 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3039 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3040 * of 16 MHz to limit PLL jitter. 3041 * @retval None 3042 * 3043 */ 3044 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 3045 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) 3046 3047 /** 3048 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3049 * @note This macro must be used only when the main PLL is disabled. 3050 * @note This macro preserves the PLL's output clocks enable state. 3051 * 3052 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3053 * This parameter can be one of the following values: 3054 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3055 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3056 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3057 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3058 * 3059 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3060 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3061 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3062 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3063 * of 16 MHz to limit PLL jitter. 3064 * 3065 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 3066 * This parameter must be a number between 8 and 86. 3067 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3068 * output frequency is between 64 and 344 MHz. 3069 * 3070 * @param __PLLP__ specifies the division factor for SAI clock. 3071 * This parameter must be a number in the range (2 to 31). 3072 * 3073 * @param __PLLQ__ specifies the division factor for USB FS, SDMMC1, RNG and FDCAN clocks. 3074 * This parameter must be in the range (2, 4, 6 or 8). 3075 * @note If the USB FS is used in your application, you have to set the 3076 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 3077 * the SDMMC1, RNG and FDCAN need a frequency lower than or equal to 48 MHz 3078 * to work correctly. 3079 * 3080 * @param __PLLR__ specifies the division factor for the main system clock. 3081 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 3082 * This parameter must be in the range (2, 4, 6 or 8). 3083 * @retval None 3084 */ 3085 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 3086 MODIFY_REG(RCC->PLLCFGR, \ 3087 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 3088 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ 3089 ((__PLLSOURCE__) | \ 3090 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 3091 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 3092 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 3093 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 3094 ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 3095 3096 /** @brief Macro to get the oscillator used as PLL clock source. 3097 * @retval The oscillator used as PLL clock source. The returned value can be one 3098 * of the following: 3099 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 3100 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3101 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3102 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3103 */ 3104 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 3105 3106 /** 3107 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 3108 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 3109 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 3110 * be stopped if used as System Clock. 3111 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 3112 * This parameter can be one or a combination of the following values: 3113 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 3114 * high-quality audio performance on SAI interface in case. 3115 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB FS(48 MHz), 3116 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 3117 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 3118 * @retval None 3119 */ 3120 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3121 3122 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3123 3124 /** 3125 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 3126 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 3127 * This parameter can be one of the following values: 3128 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 3129 * high-quality audio performance on SAI interface in case. 3130 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB FS (48 MHz), 3131 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 3132 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 3133 * @retval SET / RESET 3134 */ 3135 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3136 3137 /** 3138 * @brief Macro to configure the system clock source. 3139 * @param __SYSCLKSOURCE__ specifies the system clock source. 3140 * This parameter can be one of the following values: 3141 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 3142 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 3143 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 3144 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 3145 * @retval None 3146 */ 3147 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 3148 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 3149 3150 /** @brief Macro to get the clock source used as system clock. 3151 * @retval The clock source used as system clock. The returned value can be one 3152 * of the following: 3153 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 3154 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 3155 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 3156 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 3157 */ 3158 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 3159 3160 /** 3161 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3162 * @note As the LSE is in the Backup domain and write access is denied to 3163 * this domain after reset, you have to enable write access using 3164 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3165 * (to be done once after reset). 3166 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 3167 * This parameter can be one of the following values: 3168 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3169 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3170 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3171 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3172 * @retval None 3173 */ 3174 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3175 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3176 3177 /** 3178 * @brief Macro to configure the wake up from stop clock. 3179 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 3180 * This parameter can be one of the following values: 3181 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 3182 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 3183 * @retval None 3184 */ 3185 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 3186 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 3187 3188 3189 /** @brief Macro to configure the MCO clock. 3190 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3191 * This parameter can be one of the following values: 3192 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3193 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3194 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3195 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3196 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3197 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3198 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 3199 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3200 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 3201 * @param __MCODIV__ specifies the MCO clock prescaler. 3202 * This parameter can be one of the following values: 3203 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3204 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3205 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3206 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3207 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3208 */ 3209 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 3210 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 3211 3212 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3213 * @brief macros to manage the specified RCC Flags and interrupts. 3214 * @{ 3215 */ 3216 3217 /** @brief Enable RCC interrupt. 3218 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3219 * This parameter can be any combination of the following values: 3220 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3221 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3222 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3223 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3224 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3225 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3226 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3227 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3228 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3229 * @retval None 3230 */ 3231 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3232 3233 /** @brief Disable RCC interrupt. 3234 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3235 * This parameter can be any combination of the following values: 3236 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3237 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3238 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3239 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3240 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3241 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3242 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3243 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3244 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3245 * @retval None 3246 */ 3247 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3248 3249 /** @brief Clear the RCC's interrupt pending bits. 3250 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3251 * This parameter can be any combination of the following values: 3252 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3253 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3254 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3255 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3256 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3257 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3258 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3259 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3260 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3261 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3262 * @retval None 3263 */ 3264 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 3265 3266 /** @brief Check whether the RCC interrupt has occurred or not. 3267 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3268 * This parameter can be one of the following values: 3269 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3270 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3271 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3272 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3273 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3274 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3275 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3276 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3277 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3278 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3279 * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). 3280 */ 3281 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 3282 3283 /** @brief Set RMVF bit to clear the reset flags. 3284 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3285 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3286 * @retval None 3287 */ 3288 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 3289 3290 /** @brief Check whether the selected RCC flag is set or not. 3291 * @param __FLAG__ specifies the flag to check. 3292 * This parameter can be one of the following values: 3293 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3294 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3295 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3296 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3297 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready 3298 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready 3299 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 3300 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3301 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3302 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3303 * @arg @ref RCC_FLAG_BORRST BOR reset 3304 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3305 * @arg @ref RCC_FLAG_PINRST Pin reset 3306 * @arg @ref RCC_FLAG_SFTRST Software reset 3307 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3308 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3309 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3310 * @retval The new state of __FLAG__ (TRUE or FALSE). 3311 */ 3312 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3313 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3314 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3315 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3316 (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ 3317 ? 1U : 0U) 3318 3319 /** 3320 * @} 3321 */ 3322 3323 /** 3324 * @} 3325 */ 3326 3327 /* Private constants ---------------------------------------------------------*/ 3328 /** @defgroup RCC_Private_Constants RCC Private Constants 3329 * @{ 3330 */ 3331 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 3332 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 3333 #define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 3334 3335 /* Defines used for Flags */ 3336 #define CR_REG_INDEX 1U 3337 #define BDCR_REG_INDEX 2U 3338 #define CSR_REG_INDEX 3U 3339 #define CRRCR_REG_INDEX 4U 3340 3341 #define RCC_FLAG_MASK 0x0000001FU 3342 3343 /* Defines Oscillator Masks */ 3344 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ 3345 3346 3347 3348 /* Defines for attributes */ 3349 #define RCC_ATTR_SEC_MASK 0x100U 3350 #define RCC_ATTR_PRIV_MASK 0x200U 3351 3352 /** @defgroup RCC_Reset_Flag Reset Flag 3353 * @{ 3354 */ 3355 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 3356 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 3357 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 3358 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 3359 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 3360 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 3361 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 3362 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 3363 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 3364 RCC_RESET_FLAG_LPWR) 3365 /** 3366 * @} 3367 */ 3368 3369 /** 3370 * @} 3371 */ 3372 3373 /* Private macros ------------------------------------------------------------*/ 3374 /** @addtogroup RCC_Private_Macros 3375 * @{ 3376 */ 3377 3378 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 3379 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 3380 3381 3382 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 3383 ((__HSE__) == RCC_HSE_BYPASS)) 3384 3385 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || \ 3386 ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ 3387 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY)) 3388 3389 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 3390 3391 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 3392 <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 3393 3394 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 3395 3396 #define IS_RCC_LSIDIV(__DIV__) (((__DIV__) == RCC_LSI_DIV1) || ((__DIV__) == RCC_LSI_DIV128)) 3397 3398 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 3399 3400 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 3401 3402 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 3403 3404 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 3405 ((__PLL__) == RCC_PLL_ON)) 3406 3407 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 3408 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 3409 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 3410 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 3411 3412 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 3413 3414 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 3415 3416 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 3417 3418 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3419 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3420 3421 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3422 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3423 3424 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 3425 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 3426 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 3427 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 3428 3429 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) ((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) && \ 3430 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK)) == 0U)) 3431 3432 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 3433 ((__RANGE__) == RCC_MSIRANGE_1) || \ 3434 ((__RANGE__) == RCC_MSIRANGE_2) || \ 3435 ((__RANGE__) == RCC_MSIRANGE_3) || \ 3436 ((__RANGE__) == RCC_MSIRANGE_4) || \ 3437 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3438 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3439 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3440 ((__RANGE__) == RCC_MSIRANGE_8) || \ 3441 ((__RANGE__) == RCC_MSIRANGE_9) || \ 3442 ((__RANGE__) == RCC_MSIRANGE_10) || \ 3443 ((__RANGE__) == RCC_MSIRANGE_11)) 3444 3445 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 3446 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3447 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3448 ((__RANGE__) == RCC_MSIRANGE_7)) 3449 3450 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 3451 3452 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 3453 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 3454 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 3455 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 3456 3457 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 3458 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 3459 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 3460 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 3461 ((__HCLK__) == RCC_SYSCLK_DIV512)) 3462 3463 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 3464 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 3465 ((__PCLK__) == RCC_HCLK_DIV16)) 3466 3467 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 3468 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 3469 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 3470 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 3471 3472 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 3473 3474 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 3475 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 3476 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 3477 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 3478 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 3479 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 3480 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 3481 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 3482 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 3483 3484 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 3485 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 3486 ((__DIV__) == RCC_MCODIV_16)) 3487 3488 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 3489 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 3490 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 3491 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 3492 3493 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 3494 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 3495 3496 #define IS_RCC_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & RCC_HSI) == RCC_HSI) || \ 3497 (((__ITEM__) & RCC_HSE) == RCC_HSE) || \ 3498 (((__ITEM__) & RCC_MSI) == RCC_MSI) || \ 3499 (((__ITEM__) & RCC_LSI) == RCC_LSI) || \ 3500 (((__ITEM__) & RCC_LSE) == RCC_LSE) || \ 3501 (((__ITEM__) & RCC_HSI48) == RCC_HSI48) || \ 3502 (((__ITEM__) & RCC_SYSCLK) == RCC_SYSCLK) || \ 3503 (((__ITEM__) & RCC_PRESCALER) == RCC_PRESCALER) || \ 3504 (((__ITEM__) & RCC_PLL) == RCC_PLL) || \ 3505 (((__ITEM__) & RCC_PLLSAI1) == RCC_PLLSAI1) || \ 3506 (((__ITEM__) & RCC_PLLSAI2) == RCC_PLLSAI2) || \ 3507 (((__ITEM__) & RCC_CLK48M) == RCC_CLK48M) || \ 3508 (((__ITEM__) & RCC_RMVF) == RCC_RMVF) || \ 3509 (((__ITEM__) & ~(RCC_ALL)) == 0U)) 3510 3511 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3512 3513 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & RCC_SEC) == RCC_SEC) || \ 3514 (((__ATTRIBUTES__) & RCC_NSEC) == RCC_NSEC) || \ 3515 (((__ATTRIBUTES__) & RCC_PRIV) == RCC_PRIV) || \ 3516 (((__ATTRIBUTES__) & RCC_NPRIV) == RCC_NPRIV)) && \ 3517 (((__ATTRIBUTES__) & ~(RCC_SEC|RCC_NSEC|RCC_PRIV|RCC_NPRIV)) == 0U)) 3518 3519 #else 3520 3521 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & RCC_PRIV) == RCC_PRIV) || \ 3522 (((__ATTRIBUTES__) & RCC_NPRIV) == RCC_NPRIV)) && \ 3523 (((__ATTRIBUTES__) & ~(RCC_PRIV|RCC_NPRIV)) == 0U)) 3524 3525 #endif /* __ARM_FEATURE_CMSE */ 3526 3527 /** 3528 * @} 3529 */ 3530 3531 /* Include RCC HAL Extended module */ 3532 #include "stm32l5xx_hal_rcc_ex.h" 3533 3534 /* Exported functions --------------------------------------------------------*/ 3535 /** @addtogroup RCC_Exported_Functions 3536 * @{ 3537 */ 3538 3539 3540 /** @addtogroup RCC_Exported_Functions_Group1 3541 * @{ 3542 */ 3543 3544 /* Initialization and de-initialization functions ******************************/ 3545 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3546 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3547 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3548 3549 /** 3550 * @} 3551 */ 3552 3553 /** @addtogroup RCC_Exported_Functions_Group2 3554 * @{ 3555 */ 3556 3557 /* Peripheral Control functions ************************************************/ 3558 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3559 void HAL_RCC_EnableCSS(void); 3560 uint32_t HAL_RCC_GetSysClockFreq(void); 3561 uint32_t HAL_RCC_GetHCLKFreq(void); 3562 uint32_t HAL_RCC_GetPCLK1Freq(void); 3563 uint32_t HAL_RCC_GetPCLK2Freq(void); 3564 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3565 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3566 /* CSS NMI IRQ handler */ 3567 void HAL_RCC_NMI_IRQHandler(void); 3568 /* User Callbacks in non blocking mode (IT mode) */ 3569 void HAL_RCC_CSSCallback(void); 3570 3571 uint32_t HAL_RCC_GetResetSource(void); 3572 3573 /** 3574 * @} 3575 */ 3576 3577 /** @addtogroup RCC_Exported_Functions_Group3 3578 * @{ 3579 */ 3580 3581 /* Attributes management functions ******************************************/ 3582 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 3583 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 3584 3585 /** 3586 * @} 3587 */ 3588 3589 /** 3590 * @} 3591 */ 3592 3593 /** 3594 * @} 3595 */ 3596 3597 /** 3598 * @} 3599 */ 3600 3601 #ifdef __cplusplus 3602 } 3603 #endif 3604 3605 #endif /* STM32L5xx_HAL_RCC_H */ 3606 3607
