1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F2xx_HAL_RCC_H 20 #define __STM32F2xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f2xx_hal_def.h" 28 29 /** @addtogroup STM32F2xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCC_Exported_Types RCC Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ 58 59 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). 60 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 61 62 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ 64 65 }RCC_PLLInitTypeDef; 66 67 /** 68 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 69 */ 70 typedef struct 71 { 72 uint32_t OscillatorType; /*!< The oscillators to be configured. 73 This parameter can be a value of @ref RCC_Oscillator_Type */ 74 75 uint32_t HSEState; /*!< The new state of the HSE. 76 This parameter can be a value of @ref RCC_HSE_Config */ 77 78 uint32_t LSEState; /*!< The new state of the LSE. 79 This parameter can be a value of @ref RCC_LSE_Config */ 80 81 uint32_t HSIState; /*!< The new state of the HSI. 82 This parameter can be a value of @ref RCC_HSI_Config */ 83 84 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 85 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 86 87 uint32_t LSIState; /*!< The new state of the LSI. 88 This parameter can be a value of @ref RCC_LSI_Config */ 89 90 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 91 }RCC_OscInitTypeDef; 92 93 /** 94 * @brief RCC System, AHB and APB busses clock configuration structure definition 95 */ 96 typedef struct 97 { 98 uint32_t ClockType; /*!< The clock to be configured. 99 This parameter can be a value of @ref RCC_System_Clock_Type */ 100 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 102 This parameter can be a value of @ref RCC_System_Clock_Source */ 103 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 106 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 109 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 112 113 }RCC_ClkInitTypeDef; 114 115 /** 116 * @} 117 */ 118 119 /* Exported constants --------------------------------------------------------*/ 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants 121 * @{ 122 */ 123 124 /** @defgroup RCC_Oscillator_Type Oscillator Type 125 * @{ 126 */ 127 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 128 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 129 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 130 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 131 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 132 /** 133 * @} 134 */ 135 136 /** @defgroup RCC_HSE_Config HSE Config 137 * @{ 138 */ 139 #define RCC_HSE_OFF ((uint8_t)0x00) 140 #define RCC_HSE_ON ((uint8_t)0x01) 141 #define RCC_HSE_BYPASS ((uint8_t)0x05) 142 /** 143 * @} 144 */ 145 146 /** @defgroup RCC_LSE_Config LSE Config 147 * @{ 148 */ 149 #define RCC_LSE_OFF ((uint8_t)0x00) 150 #define RCC_LSE_ON ((uint8_t)0x01) 151 #define RCC_LSE_BYPASS ((uint8_t)0x05) 152 /** 153 * @} 154 */ 155 156 /** @defgroup RCC_HSI_Config HSI Config 157 * @{ 158 */ 159 #define RCC_HSI_OFF ((uint8_t)0x00) 160 #define RCC_HSI_ON ((uint8_t)0x01) 161 162 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup RCC_LSI_Config LSI Config 168 * @{ 169 */ 170 #define RCC_LSI_OFF ((uint8_t)0x00) 171 #define RCC_LSI_ON ((uint8_t)0x01) 172 /** 173 * @} 174 */ 175 176 /** @defgroup RCC_PLL_Config PLL Config 177 * @{ 178 */ 179 #define RCC_PLL_NONE ((uint8_t)0x00) 180 #define RCC_PLL_OFF ((uint8_t)0x01) 181 #define RCC_PLL_ON ((uint8_t)0x02) 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 187 * @{ 188 */ 189 #define RCC_PLLP_DIV2 0x00000002U 190 #define RCC_PLLP_DIV4 0x00000004U 191 #define RCC_PLLP_DIV6 0x00000006U 192 #define RCC_PLLP_DIV8 0x00000008U 193 /** 194 * @} 195 */ 196 197 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 198 * @{ 199 */ 200 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI 201 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE 202 /** 203 * @} 204 */ 205 206 /** @defgroup RCC_System_Clock_Type System Clock Type 207 * @{ 208 */ 209 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U 210 #define RCC_CLOCKTYPE_HCLK 0x00000002U 211 #define RCC_CLOCKTYPE_PCLK1 0x00000004U 212 #define RCC_CLOCKTYPE_PCLK2 0x00000008U 213 /** 214 * @} 215 */ 216 217 /** @defgroup RCC_System_Clock_Source System Clock Source 218 * @{ 219 */ 220 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 221 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 222 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 228 * @{ 229 */ 230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 233 /** 234 * @} 235 */ 236 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 238 * @{ 239 */ 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 249 /** 250 * @} 251 */ 252 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source 254 * @{ 255 */ 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 261 /** 262 * @} 263 */ 264 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 266 * @{ 267 */ 268 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U 269 #define RCC_RTCCLKSOURCE_LSE 0x00000100U 270 #define RCC_RTCCLKSOURCE_LSI 0x00000200U 271 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U 272 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U 273 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U 274 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U 275 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U 276 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U 277 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U 278 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U 279 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U 280 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U 281 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U 282 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U 283 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U 284 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U 285 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U 286 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U 287 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U 288 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U 289 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U 290 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U 291 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U 292 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U 293 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U 294 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U 295 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U 296 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U 297 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U 298 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U 299 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U 300 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U 301 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U 302 /** 303 * @} 304 */ 305 306 /** @defgroup RCC_MCO_Index MCO Index 307 * @{ 308 */ 309 #define RCC_MCO1 0x00000000U 310 #define RCC_MCO2 0x00000001U 311 /** 312 * @} 313 */ 314 315 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 316 * @{ 317 */ 318 #define RCC_MCO1SOURCE_HSI 0x00000000U 319 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 320 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 321 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 322 /** 323 * @} 324 */ 325 326 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 327 * @{ 328 */ 329 #define RCC_MCO2SOURCE_SYSCLK 0x00000000U 330 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 331 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 332 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 333 /** 334 * @} 335 */ 336 337 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 338 * @{ 339 */ 340 #define RCC_MCODIV_1 0x00000000U 341 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 342 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 343 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 344 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE 345 /** 346 * @} 347 */ 348 349 /** @defgroup RCC_Interrupt Interrupts 350 * @{ 351 */ 352 #define RCC_IT_LSIRDY ((uint8_t)0x01) 353 #define RCC_IT_LSERDY ((uint8_t)0x02) 354 #define RCC_IT_HSIRDY ((uint8_t)0x04) 355 #define RCC_IT_HSERDY ((uint8_t)0x08) 356 #define RCC_IT_PLLRDY ((uint8_t)0x10) 357 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 358 #define RCC_IT_CSS ((uint8_t)0x80) 359 /** 360 * @} 361 */ 362 363 /** @defgroup RCC_Flag Flags 364 * Elements values convention: 0XXYYYYYb 365 * - YYYYY : Flag position in the register 366 * - 0XX : Register index 367 * - 01: CR register 368 * - 10: BDCR register 369 * - 11: CSR register 370 * @{ 371 */ 372 /* Flags in the CR register */ 373 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 374 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 375 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 376 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 377 378 /* Flags in the BDCR register */ 379 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 380 381 /* Flags in the CSR register */ 382 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 383 #define RCC_FLAG_BORRST ((uint8_t)0x79) 384 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 385 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 386 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 387 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 388 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 389 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 390 /** 391 * @} 392 */ 393 394 /** 395 * @} 396 */ 397 398 /* Exported macro ------------------------------------------------------------*/ 399 /** @defgroup RCC_Exported_Macros RCC Exported Macros 400 * @{ 401 */ 402 403 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 404 * @brief Enable or disable the AHB1 peripheral clock. 405 * @note After reset, the peripheral clock (used for registers read/write access) 406 * is disabled and the application software has to enable this clock before 407 * using it. 408 * @{ 409 */ 410 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 411 __IO uint32_t tmpreg = 0x00U; \ 412 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 413 /* Delay after an RCC peripheral clock enabling */ \ 414 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 415 UNUSED(tmpreg); \ 416 } while(0) 417 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 418 __IO uint32_t tmpreg = 0x00U; \ 419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 420 /* Delay after an RCC peripheral clock enabling */ \ 421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 422 UNUSED(tmpreg); \ 423 } while(0) 424 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 425 __IO uint32_t tmpreg = 0x00U; \ 426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 427 /* Delay after an RCC peripheral clock enabling */ \ 428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 429 UNUSED(tmpreg); \ 430 } while(0) 431 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 432 __IO uint32_t tmpreg = 0x00U; \ 433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 434 /* Delay after an RCC peripheral clock enabling */ \ 435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ 436 UNUSED(tmpreg); \ 437 } while(0) 438 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 439 __IO uint32_t tmpreg = 0x00U; \ 440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 441 /* Delay after an RCC peripheral clock enabling */ \ 442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ 443 UNUSED(tmpreg); \ 444 } while(0) 445 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 446 __IO uint32_t tmpreg = 0x00U; \ 447 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 448 /* Delay after an RCC peripheral clock enabling */ \ 449 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ 450 UNUSED(tmpreg); \ 451 } while(0) 452 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 453 __IO uint32_t tmpreg = 0x00U; \ 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 455 /* Delay after an RCC peripheral clock enabling */ \ 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ 457 UNUSED(tmpreg); \ 458 } while(0) 459 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 460 __IO uint32_t tmpreg = 0x00U; \ 461 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 462 /* Delay after an RCC peripheral clock enabling */ \ 463 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 464 UNUSED(tmpreg); \ 465 } while(0) 466 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 467 __IO uint32_t tmpreg = 0x00U; \ 468 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 469 /* Delay after an RCC peripheral clock enabling */ \ 470 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ 471 UNUSED(tmpreg); \ 472 } while(0) 473 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 474 __IO uint32_t tmpreg = 0x00U; \ 475 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 476 /* Delay after an RCC peripheral clock enabling */ \ 477 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ 478 UNUSED(tmpreg); \ 479 } while(0) 480 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 481 __IO uint32_t tmpreg = 0x00U; \ 482 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 483 /* Delay after an RCC peripheral clock enabling */ \ 484 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ 485 UNUSED(tmpreg); \ 486 } while(0) 487 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 488 __IO uint32_t tmpreg = 0x00U; \ 489 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 490 /* Delay after an RCC peripheral clock enabling */ \ 491 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 492 UNUSED(tmpreg); \ 493 } while(0) 494 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 495 __IO uint32_t tmpreg = 0x00U; \ 496 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 497 /* Delay after an RCC peripheral clock enabling */ \ 498 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 499 UNUSED(tmpreg); \ 500 } while(0) 501 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 502 __IO uint32_t tmpreg = 0x00U; \ 503 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 504 /* Delay after an RCC peripheral clock enabling */ \ 505 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 506 UNUSED(tmpreg); \ 507 } while(0) 508 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ 509 __IO uint32_t tmpreg = 0x00U; \ 510 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 511 /* Delay after an RCC peripheral clock enabling */ \ 512 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ 513 UNUSED(tmpreg); \ 514 } while(0) 515 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) 516 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) 517 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) 518 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) 519 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) 520 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) 521 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) 522 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) 523 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) 524 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) 525 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) 526 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) 527 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) 528 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) 529 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) 530 /** 531 * @} 532 */ 533 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 534 * @brief Get the enable or disable status of the AHB1 peripheral clock. 535 * @note After reset, the peripheral clock (used for registers read/write access) 536 * is disabled and the application software has to enable this clock before 537 * using it. 538 * @{ 539 */ 540 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) 541 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) 542 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) 543 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET) 544 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET) 545 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET) 546 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET) 547 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) 548 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET) 549 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET) 550 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET) 551 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) 552 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) 553 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET) 554 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 555 556 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) 557 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) 558 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) 559 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET) 560 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET) 561 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET) 562 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET) 563 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) 564 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET) 565 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET) 566 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET) 567 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) 568 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) 569 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET) 570 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 571 /** 572 * @} 573 */ 574 575 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 576 * @brief Enable or disable the AHB2 peripheral clock. 577 * @note After reset, the peripheral clock (used for registers read/write access) 578 * is disabled and the application software has to enable this clock before 579 * using it. 580 * @{ 581 */ 582 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ 583 __HAL_RCC_SYSCFG_CLK_ENABLE();\ 584 }while(0) 585 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 586 __IO uint32_t tmpreg = 0x00U; \ 587 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 588 /* Delay after an RCC peripheral clock enabling */ \ 589 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ 590 UNUSED(tmpreg); \ 591 } while(0) 592 593 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) 594 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) 595 /** 596 * @} 597 */ 598 599 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status 600 * @brief Get the enable or disable status of the AHB2 peripheral clock. 601 * @note After reset, the peripheral clock (used for registers read/write access) 602 * is disabled and the application software has to enable this clock before 603 * using it. 604 * @{ 605 */ 606 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET) 607 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET) 608 609 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET) 610 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET) 611 /** 612 * @} 613 */ 614 615 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 616 * @brief Enables or disables the AHB3 peripheral clock. 617 * @note After reset, the peripheral clock (used for registers read/write access) 618 * is disabled and the application software has to enable this clock before 619 * using it. 620 * @{ 621 */ 622 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 623 __IO uint32_t tmpreg = 0x00U; \ 624 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 625 /* Delay after an RCC peripheral clock enabling */ \ 626 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ 627 UNUSED(tmpreg); \ 628 } while(0) 629 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) 630 /** 631 * @} 632 */ 633 634 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status 635 * @brief Get the enable or disable status of the AHB3 peripheral clock. 636 * @note After reset, the peripheral clock (used for registers read/write access) 637 * is disabled and the application software has to enable this clock before 638 * using it. 639 * @{ 640 */ 641 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET) 642 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET) 643 /** 644 * @} 645 */ 646 647 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 648 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 649 * @note After reset, the peripheral clock (used for registers read/write access) 650 * is disabled and the application software has to enable this clock before 651 * using it. 652 * @{ 653 */ 654 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 655 __IO uint32_t tmpreg = 0x00U; \ 656 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 657 /* Delay after an RCC peripheral clock enabling */ \ 658 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 659 UNUSED(tmpreg); \ 660 } while(0) 661 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 662 __IO uint32_t tmpreg = 0x00U; \ 663 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 664 /* Delay after an RCC peripheral clock enabling */ \ 665 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 666 UNUSED(tmpreg); \ 667 } while(0) 668 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 669 __IO uint32_t tmpreg = 0x00U; \ 670 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 671 /* Delay after an RCC peripheral clock enabling */ \ 672 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 673 UNUSED(tmpreg); \ 674 } while(0) 675 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 676 __IO uint32_t tmpreg = 0x00U; \ 677 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 678 /* Delay after an RCC peripheral clock enabling */ \ 679 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 680 UNUSED(tmpreg); \ 681 } while(0) 682 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 683 __IO uint32_t tmpreg = 0x00U; \ 684 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 685 /* Delay after an RCC peripheral clock enabling */ \ 686 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 687 UNUSED(tmpreg); \ 688 } while(0) 689 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 690 __IO uint32_t tmpreg = 0x00U; \ 691 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 692 /* Delay after an RCC peripheral clock enabling */ \ 693 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 694 UNUSED(tmpreg); \ 695 } while(0) 696 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 697 __IO uint32_t tmpreg = 0x00U; \ 698 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 699 /* Delay after an RCC peripheral clock enabling */ \ 700 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 701 UNUSED(tmpreg); \ 702 } while(0) 703 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 704 __IO uint32_t tmpreg = 0x00U; \ 705 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 706 /* Delay after an RCC peripheral clock enabling */ \ 707 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 708 UNUSED(tmpreg); \ 709 } while(0) 710 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 711 __IO uint32_t tmpreg = 0x00U; \ 712 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 713 /* Delay after an RCC peripheral clock enabling */ \ 714 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 715 UNUSED(tmpreg); \ 716 } while(0) 717 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 718 __IO uint32_t tmpreg = 0x00U; \ 719 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 720 /* Delay after an RCC peripheral clock enabling */ \ 721 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 722 UNUSED(tmpreg); \ 723 } while(0) 724 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 725 __IO uint32_t tmpreg = 0x00U; \ 726 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 727 /* Delay after an RCC peripheral clock enabling */ \ 728 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 729 UNUSED(tmpreg); \ 730 } while(0) 731 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 732 __IO uint32_t tmpreg = 0x00U; \ 733 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 734 /* Delay after an RCC peripheral clock enabling */ \ 735 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 736 UNUSED(tmpreg); \ 737 } while(0) 738 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 739 __IO uint32_t tmpreg = 0x00U; \ 740 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 741 /* Delay after an RCC peripheral clock enabling */ \ 742 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 743 UNUSED(tmpreg); \ 744 } while(0) 745 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 746 __IO uint32_t tmpreg = 0x00U; \ 747 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 748 /* Delay after an RCC peripheral clock enabling */ \ 749 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 750 UNUSED(tmpreg); \ 751 } while(0) 752 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 753 __IO uint32_t tmpreg = 0x00U; \ 754 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 755 /* Delay after an RCC peripheral clock enabling */ \ 756 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 757 UNUSED(tmpreg); \ 758 } while(0) 759 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 760 __IO uint32_t tmpreg = 0x00U; \ 761 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 762 /* Delay after an RCC peripheral clock enabling */ \ 763 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 764 UNUSED(tmpreg); \ 765 } while(0) 766 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 767 __IO uint32_t tmpreg = 0x00U; \ 768 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 769 /* Delay after an RCC peripheral clock enabling */ \ 770 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 771 UNUSED(tmpreg); \ 772 } while(0) 773 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 774 __IO uint32_t tmpreg = 0x00U; \ 775 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 776 /* Delay after an RCC peripheral clock enabling */ \ 777 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 778 UNUSED(tmpreg); \ 779 } while(0) 780 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 781 __IO uint32_t tmpreg = 0x00U; \ 782 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 783 /* Delay after an RCC peripheral clock enabling */ \ 784 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ 785 UNUSED(tmpreg); \ 786 } while(0) 787 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 788 __IO uint32_t tmpreg = 0x00U; \ 789 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 790 /* Delay after an RCC peripheral clock enabling */ \ 791 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 792 UNUSED(tmpreg); \ 793 } while(0) 794 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 795 __IO uint32_t tmpreg = 0x00U; \ 796 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 797 /* Delay after an RCC peripheral clock enabling */ \ 798 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 799 UNUSED(tmpreg); \ 800 } while(0) 801 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 802 __IO uint32_t tmpreg = 0x00U; \ 803 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 804 /* Delay after an RCC peripheral clock enabling */ \ 805 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 806 UNUSED(tmpreg); \ 807 } while(0) 808 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 809 __IO uint32_t tmpreg = 0x00U; \ 810 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 811 /* Delay after an RCC peripheral clock enabling */ \ 812 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 813 UNUSED(tmpreg); \ 814 } while(0) 815 816 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 817 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 818 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 819 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 820 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 821 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 822 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 823 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 824 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 825 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 826 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 827 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 828 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 829 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 830 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 831 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 832 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 833 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 834 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) 835 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 836 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 837 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 838 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 839 /** 840 * @} 841 */ 842 843 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 844 * @brief Get the enable or disable status of the APB1 peripheral clock. 845 * @note After reset, the peripheral clock (used for registers read/write access) 846 * is disabled and the application software has to enable this clock before 847 * using it. 848 * @{ 849 */ 850 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET) 851 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET) 852 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET) 853 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET) 854 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET) 855 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET) 856 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET) 857 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET) 858 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET) 859 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET) 860 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET) 861 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET) 862 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET) 863 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET) 864 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET) 865 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET) 866 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET) 867 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET) 868 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET) 869 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET) 870 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET) 871 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET) 872 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET) 873 874 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET) 875 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET) 876 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET) 877 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET) 878 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET) 879 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET) 880 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET) 881 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET) 882 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET) 883 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET) 884 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET) 885 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET) 886 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET) 887 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET) 888 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET) 889 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET) 890 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET) 891 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET) 892 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET) 893 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET) 894 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET) 895 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET) 896 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET) 897 /** 898 * @} 899 */ 900 901 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 902 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 903 * @note After reset, the peripheral clock (used for registers read/write access) 904 * is disabled and the application software has to enable this clock before 905 * using it. 906 * @{ 907 */ 908 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 909 __IO uint32_t tmpreg = 0x00U; \ 910 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 911 /* Delay after an RCC peripheral clock enabling */ \ 912 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 913 UNUSED(tmpreg); \ 914 } while(0) 915 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 916 __IO uint32_t tmpreg = 0x00U; \ 917 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 918 /* Delay after an RCC peripheral clock enabling */ \ 919 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 920 UNUSED(tmpreg); \ 921 } while(0) 922 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 923 __IO uint32_t tmpreg = 0x00U; \ 924 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 925 /* Delay after an RCC peripheral clock enabling */ \ 926 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 927 UNUSED(tmpreg); \ 928 } while(0) 929 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 930 __IO uint32_t tmpreg = 0x00U; \ 931 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 932 /* Delay after an RCC peripheral clock enabling */ \ 933 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 934 UNUSED(tmpreg); \ 935 } while(0) 936 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 937 __IO uint32_t tmpreg = 0x00U; \ 938 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 939 /* Delay after an RCC peripheral clock enabling */ \ 940 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 941 UNUSED(tmpreg); \ 942 } while(0) 943 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 944 __IO uint32_t tmpreg = 0x00U; \ 945 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 946 /* Delay after an RCC peripheral clock enabling */ \ 947 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 948 UNUSED(tmpreg); \ 949 } while(0) 950 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 951 __IO uint32_t tmpreg = 0x00U; \ 952 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 953 /* Delay after an RCC peripheral clock enabling */ \ 954 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 955 UNUSED(tmpreg); \ 956 } while(0) 957 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 958 __IO uint32_t tmpreg = 0x00U; \ 959 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 960 /* Delay after an RCC peripheral clock enabling */ \ 961 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ 962 UNUSED(tmpreg); \ 963 } while(0) 964 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 965 __IO uint32_t tmpreg = 0x00U; \ 966 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 967 /* Delay after an RCC peripheral clock enabling */ \ 968 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 969 UNUSED(tmpreg); \ 970 } while(0) 971 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg = 0x00U; \ 973 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 976 UNUSED(tmpreg); \ 977 } while(0) 978 979 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 980 __IO uint32_t tmpreg = 0x00U; \ 981 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 982 /* Delay after an RCC peripheral clock enabling */ \ 983 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 984 UNUSED(tmpreg); \ 985 } while(0) 986 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 987 __IO uint32_t tmpreg = 0x00U; \ 988 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 989 /* Delay after an RCC peripheral clock enabling */ \ 990 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 991 UNUSED(tmpreg); \ 992 } while(0) 993 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 994 __IO uint32_t tmpreg = 0x00U; \ 995 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 996 /* Delay after an RCC peripheral clock enabling */ \ 997 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 998 UNUSED(tmpreg); \ 999 } while(0) 1000 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 1001 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1002 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 1003 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 1004 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 1005 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1006 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1007 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) 1008 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 1009 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 1010 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 1011 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1012 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 1013 /** 1014 * @} 1015 */ 1016 1017 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1018 * @brief Get the enable or disable status of the APB2 peripheral clock. 1019 * @note After reset, the peripheral clock (used for registers read/write access) 1020 * is disabled and the application software has to enable this clock before 1021 * using it. 1022 * @{ 1023 */ 1024 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET) 1025 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET) 1026 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET) 1027 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET) 1028 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET) 1029 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET) 1030 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET) 1031 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET) 1032 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET) 1033 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET) 1034 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET) 1035 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET) 1036 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET) 1037 1038 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET) 1039 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET) 1040 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET) 1041 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET) 1042 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET) 1043 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET) 1044 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET) 1045 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET) 1046 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET) 1047 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET) 1048 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET) 1049 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET) 1050 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET) 1051 /** 1052 * @} 1053 */ 1054 1055 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset 1056 * @brief Force or release AHB1 peripheral reset. 1057 * @{ 1058 */ 1059 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 1060 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) 1061 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) 1062 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) 1063 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) 1064 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) 1065 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) 1066 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) 1067 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) 1068 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) 1069 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) 1070 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 1071 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 1072 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) 1073 #define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST)) 1074 1075 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 1076 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) 1077 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) 1078 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) 1079 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) 1080 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) 1081 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) 1082 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) 1083 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) 1084 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) 1085 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) 1086 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) 1087 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) 1088 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) 1089 #define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST)) 1090 /** 1091 * @} 1092 */ 1093 1094 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset 1095 * @brief Force or release AHB2 peripheral reset. 1096 * @{ 1097 */ 1098 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) 1099 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) 1100 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) 1101 1102 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) 1103 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) 1104 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 1110 * @brief Force or release APB1 peripheral reset. 1111 * @{ 1112 */ 1113 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 1114 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 1115 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 1116 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1117 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1118 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1119 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1120 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1121 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1122 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1123 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 1124 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 1125 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1126 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 1127 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1128 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1129 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1130 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 1131 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 1132 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) 1133 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1134 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1135 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 1136 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1137 1138 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 1139 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 1140 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 1141 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1142 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1143 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1144 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1145 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1146 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1147 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1148 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 1149 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 1150 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1151 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 1152 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1153 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1154 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1155 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 1156 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 1157 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) 1158 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1159 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1160 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 1161 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1162 /** 1163 * @} 1164 */ 1165 1166 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 1167 * @brief Force or release APB2 peripheral reset. 1168 * @{ 1169 */ 1170 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 1171 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 1172 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1173 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 1174 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 1175 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) 1176 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) 1177 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 1178 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 1179 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 1180 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1181 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 1182 1183 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 1184 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 1185 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1186 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 1187 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 1188 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) 1189 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) 1190 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 1191 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 1192 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 1193 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1194 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 1195 /** 1196 * @} 1197 */ 1198 1199 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset 1200 * @brief Force or release AHB3 peripheral reset. 1201 * @{ 1202 */ 1203 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) 1204 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) 1205 1206 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 1207 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) 1208 /** 1209 * @} 1210 */ 1211 1212 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 1213 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1214 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1215 * power consumption. 1216 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1217 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1218 * @{ 1219 */ 1220 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) 1221 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) 1222 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) 1223 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) 1224 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) 1225 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) 1226 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) 1227 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) 1228 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) 1229 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) 1230 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) 1231 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) 1232 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) 1233 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) 1234 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 1235 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 1236 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) 1237 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) 1238 1239 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) 1240 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) 1241 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) 1242 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) 1243 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) 1244 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) 1245 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) 1246 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) 1247 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) 1248 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) 1249 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) 1250 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) 1251 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) 1252 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) 1253 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) 1254 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) 1255 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) 1256 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) 1257 /** 1258 * @} 1259 */ 1260 1261 /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable 1262 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 1263 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1264 * power consumption. 1265 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1266 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1267 * @{ 1268 */ 1269 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) 1270 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) 1271 1272 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) 1273 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) 1274 /** 1275 * @} 1276 */ 1277 1278 /** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable 1279 * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. 1280 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1281 * power consumption. 1282 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1283 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1284 * @{ 1285 */ 1286 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) 1287 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) 1288 /** 1289 * @} 1290 */ 1291 1292 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 1293 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1294 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1295 * power consumption. 1296 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1297 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1298 * @{ 1299 */ 1300 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) 1301 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) 1302 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) 1303 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 1304 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) 1305 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) 1306 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) 1307 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) 1308 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) 1309 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 1310 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 1311 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) 1312 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 1313 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) 1314 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) 1315 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) 1316 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 1317 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 1318 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) 1319 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 1320 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) 1321 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) 1322 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) 1323 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) 1324 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) 1325 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) 1326 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 1327 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) 1328 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) 1329 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) 1330 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) 1331 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) 1332 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 1333 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 1334 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) 1335 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 1336 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) 1337 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) 1338 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) 1339 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 1340 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 1341 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) 1342 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 1343 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) 1344 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) 1345 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) 1346 /** 1347 * @} 1348 */ 1349 1350 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 1351 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1352 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1353 * power consumption. 1354 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 1355 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1356 * @{ 1357 */ 1358 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) 1359 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 1360 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) 1361 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 1362 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) 1363 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 1364 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 1365 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) 1366 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 1367 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) 1368 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 1369 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) 1370 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) 1371 1372 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) 1373 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 1374 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) 1375 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 1376 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) 1377 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 1378 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 1379 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) 1380 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 1381 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) 1382 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 1383 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) 1384 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) 1385 /** 1386 * @} 1387 */ 1388 1389 /** @defgroup RCC_HSI_Configuration HSI Configuration 1390 * @{ 1391 */ 1392 1393 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 1394 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1395 * It is used (enabled by hardware) as system clock source after startup 1396 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure 1397 * of the HSE used directly or indirectly as system clock (if the Clock 1398 * Security System CSS is enabled). 1399 * @note HSI can not be stopped if it is used as system clock source. In this case, 1400 * you have to select another source of the system clock then stop the HSI. 1401 * @note After enabling the HSI, the application software should wait on HSIRDY 1402 * flag to be set indicating that HSI clock is stable and can be used as 1403 * system clock source. 1404 * This parameter can be: ENABLE or DISABLE. 1405 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1406 * clock cycles. 1407 */ 1408 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 1409 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 1410 1411 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1412 * @note The calibration is used to compensate for the variations in voltage 1413 * and temperature that influence the frequency of the internal HSI RC. 1414 * @param __HSICalibrationValue__ specifies the calibration trimming value. 1415 * (default is RCC_HSICALIBRATION_DEFAULT). 1416 * This parameter must be a number between 0 and 0x1F. 1417 */ 1418 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ 1419 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))) 1420 /** 1421 * @} 1422 */ 1423 1424 /** @defgroup RCC_LSI_Configuration LSI Configuration 1425 * @{ 1426 */ 1427 1428 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 1429 * @note After enabling the LSI, the application software should wait on 1430 * LSIRDY flag to be set indicating that LSI clock is stable and can 1431 * be used to clock the IWDG and/or the RTC. 1432 * @note LSI can not be disabled if the IWDG is running. 1433 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1434 * clock cycles. 1435 */ 1436 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 1437 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup RCC_HSE_Configuration HSE Configuration 1443 * @{ 1444 */ 1445 1446 /** 1447 * @brief Macro to configure the External High Speed oscillator (HSE). 1448 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 1449 * User should request a transition to HSE Off first and then HSE On or HSE Bypass. 1450 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1451 * software should wait on HSERDY flag to be set indicating that HSE clock 1452 * is stable and can be used to clock the PLL and/or system clock. 1453 * @note HSE state can not be changed if it is used directly or through the 1454 * PLL as system clock. In this case, you have to select another source 1455 * of the system clock then change the HSE state (ex. disable it). 1456 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1457 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1458 * was previously enabled you have to enable it again after calling this 1459 * function. 1460 * @param __STATE__ specifies the new state of the HSE. 1461 * This parameter can be one of the following values: 1462 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 1463 * 6 HSE oscillator clock cycles. 1464 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 1465 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 1466 */ 1467 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__)) 1468 /** 1469 * @} 1470 */ 1471 1472 /** @defgroup RCC_LSE_Configuration LSE Configuration 1473 * @{ 1474 */ 1475 /** 1476 * @brief Macro to configure the External Low Speed oscillator (LSE). 1477 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 1478 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 1479 * @note As the LSE is in the Backup domain and write access is denied to 1480 * this domain after reset, you have to enable write access using 1481 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 1482 * (to be done once after reset). 1483 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1484 * software should wait on LSERDY flag to be set indicating that LSE clock 1485 * is stable and can be used to clock the RTC. 1486 * @param __STATE__ specifies the new state of the LSE. 1487 * This parameter can be one of the following values: 1488 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 1489 * 6 LSE oscillator clock cycles. 1490 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 1491 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 1492 */ 1493 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__)) 1494 1495 /** 1496 * @} 1497 */ 1498 1499 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration 1500 * @{ 1501 */ 1502 1503 /** @brief Macros to enable or disable the RTC clock. 1504 * @note These macros must be used only after the RTC clock source was selected. 1505 */ 1506 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 1507 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 1508 1509 /** @brief Macros to configure the RTC clock (RTCCLK). 1510 * @note As the RTC clock configuration bits are in the Backup domain and write 1511 * access is denied to this domain after reset, you have to enable write 1512 * access using the Power Backup Access macro before to configure 1513 * the RTC clock source (to be done once after reset). 1514 * @note Once the RTC clock is configured it can't be changed unless the 1515 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 1516 * a Power On Reset (POR). 1517 * @param __RTCCLKSource__ specifies the RTC clock source. 1518 * This parameter can be one of the following values: 1519 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. 1520 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. 1521 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. 1522 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 1523 * as RTC clock, where x:[2,31] 1524 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1525 * work in STOP and STANDBY modes, and can be used as wake-up source. 1526 * However, when the HSE clock is used as RTC clock source, the RTC 1527 * cannot be used in STOP and STANDBY modes. 1528 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1529 * RTC clock source). 1530 */ 1531 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 1532 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 1533 1534 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 1535 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 1536 } while (0U) 1537 1538 /** @brief Macro to get the RTC clock source. 1539 * @retval The clock source can be one of the following values: 1540 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 1541 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 1542 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1543 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1544 */ 1545 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 1546 1547 /** 1548 * @brief Get the RTC and HSE clock divider (RTCPRE). 1549 * @retval Returned value can be one of the following values: 1550 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected 1551 * as RTC clock, where x:[2,31] 1552 */ 1553 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) 1554 1555 /** @brief Macros to force or release the Backup domain reset. 1556 * @note This function resets the RTC peripheral (including the backup registers) 1557 * and the RTC clock source selection in RCC_CSR register. 1558 * @note The BKPSRAM is not affected by this reset. 1559 */ 1560 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 1561 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 1562 /** 1563 * @} 1564 */ 1565 1566 /** @defgroup RCC_PLL_Configuration PLL Configuration 1567 * @{ 1568 */ 1569 1570 /** @brief Macros to enable or disable the main PLL. 1571 * @note After enabling the main PLL, the application software should wait on 1572 * PLLRDY flag to be set indicating that PLL clock is stable and can 1573 * be used as system clock source. 1574 * @note The main PLL can not be disabled if it is used as system clock source 1575 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1576 */ 1577 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 1578 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 1579 1580 1581 /** @brief Macro to configure the main PLL clock source, multiplication and division factors. 1582 * @note This function must be used only when the main PLL is disabled. 1583 * @param __RCC_PLLSource__ specifies the PLL entry clock source. 1584 * This parameter can be one of the following values: 1585 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 1586 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 1587 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. 1588 * @param __PLLM__ specifies the division factor for PLL VCO input clock 1589 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 1590 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1591 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 1592 * of 2 MHz to limit PLL jitter. 1593 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 1594 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 1595 * @note You have to set the PLLN parameter correctly to ensure that the VCO 1596 * output frequency is between 192 and 432 MHz. 1597 * 1598 * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) 1599 * This parameter must be a number in the range {2, 4, 6, or 8}. 1600 * 1601 * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks 1602 * This parameter must be a number between Min_Data = 2 and Max_Data = 15. 1603 * @note If the USB OTG FS is used in your application, you have to set the 1604 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 1605 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work 1606 * correctly. 1607 * 1608 */ 1609 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ 1610 MODIFY_REG(RCC->PLLCFGR, \ 1611 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ), \ 1612 ((__RCC_PLLSource__) | (__PLLM__)| ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ 1613 ((((__PLLP__) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos))) 1614 /** 1615 * @} 1616 */ 1617 1618 /** @brief Macro to configure the PLL clock source. 1619 * @note This function must be used only when the main PLL is disabled. 1620 * @param __PLLSOURCE__ specifies the PLL entry clock source. 1621 * This parameter can be one of the following values: 1622 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 1623 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 1624 * 1625 */ 1626 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 1627 1628 /** @brief Macro to configure the PLL multiplication factor. 1629 * @note This function must be used only when the main PLL is disabled. 1630 * @param __PLLM__ specifies the division factor for PLL VCO input clock 1631 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 1632 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1633 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 1634 * of 2 MHz to limit PLL jitter. 1635 * 1636 */ 1637 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 1638 1639 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration 1640 * @{ 1641 */ 1642 1643 /** @brief Macros to enable or disable the PLLI2S. 1644 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 1645 */ 1646 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 1647 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 1648 1649 /** @brief Macro to configure the PLLI2S clock multiplication and division factors . 1650 * @note This macro must be used only when the PLLI2S is disabled. 1651 * @note PLLI2S clock source is common with the main PLL (configured in 1652 * HAL_RCC_ClockConfig() API). 1653 * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock 1654 * This parameter must be a number between Min_Data = 192 and Max_Data = 432. 1655 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO 1656 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. 1657 * @param __PLLI2SR__ specifies the division factor for I2S clock 1658 * This parameter must be a number between Min_Data = 2 and Max_Data = 7. 1659 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz 1660 * on the I2S clock frequency. 1661 */ 1662 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))) 1663 1664 /** @brief Macro to configure the I2S clock source (I2SCLK). 1665 * @note This function must be called before enabling the I2S APB clock. 1666 * @param __SOURCE__ specifies the I2S clock source. 1667 * This parameter can be one of the following values: 1668 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. 1669 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin 1670 * used as I2S clock source. 1671 */ 1672 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) 1673 /** 1674 * @} 1675 */ 1676 1677 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1678 * @{ 1679 */ 1680 1681 /** @brief Macro to configure the MCO1 clock. 1682 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1683 * This parameter can be one of the following values: 1684 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 1685 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 1686 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 1687 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source 1688 * @param __MCODIV__ specifies the MCO clock prescaler. 1689 * This parameter can be one of the following values: 1690 * @arg RCC_MCODIV_1: no division applied to MCOx clock 1691 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1692 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1693 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1694 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1695 */ 1696 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1697 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1698 1699 /** @brief Macro to configure the MCO2 clock. 1700 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1701 * This parameter can be one of the following values: 1702 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 1703 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source 1704 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 1705 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source 1706 * @param __MCODIV__ specifies the MCO clock prescaler. 1707 * This parameter can be one of the following values: 1708 * @arg RCC_MCODIV_1: no division applied to MCOx clock 1709 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1710 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1711 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1712 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1713 */ 1714 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1715 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); 1716 /** 1717 * @} 1718 */ 1719 1720 /** @defgroup RCC_Get_Clock_source Get Clock source 1721 * @{ 1722 */ 1723 /** 1724 * @brief Macro to configure the system clock source. 1725 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. 1726 * This parameter can be one of the following values: 1727 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 1728 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 1729 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 1730 */ 1731 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 1732 1733 /** @brief Macro to get the clock source used as system clock. 1734 * @retval The clock source used as system clock. The returned value can be one 1735 * of the following: 1736 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 1737 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 1738 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 1739 */ 1740 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 1741 1742 /** @brief Macro to get the oscillator used as PLL clock source. 1743 * @retval The oscillator used as PLL clock source. The returned value can be one 1744 * of the following: 1745 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 1746 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 1747 */ 1748 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 1749 /** 1750 * @} 1751 */ 1752 1753 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1754 * @brief macros to manage the specified RCC Flags and interrupts. 1755 * @{ 1756 */ 1757 1758 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 1759 * the selected interrupts). 1760 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1761 * This parameter can be any combination of the following values: 1762 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1763 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1764 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1765 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1766 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1767 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1768 */ 1769 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1770 1771 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 1772 * the selected interrupts). 1773 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1774 * This parameter can be any combination of the following values: 1775 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1776 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1777 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1778 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1779 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1780 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1781 */ 1782 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1783 1784 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 1785 * bits to clear the selected interrupt pending bits. 1786 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1787 * This parameter can be any combination of the following values: 1788 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1789 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1790 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1791 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1792 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1793 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1794 * @arg RCC_IT_CSS: Clock Security System interrupt 1795 */ 1796 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1797 1798 /** @brief Check the RCC's interrupt has occurred or not. 1799 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1800 * This parameter can be one of the following values: 1801 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1802 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1803 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1804 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1805 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1806 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1807 * @arg RCC_IT_CSS: Clock Security System interrupt 1808 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1809 */ 1810 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1811 1812 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 1813 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 1814 */ 1815 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1816 1817 /** @brief Check RCC flag is set or not. 1818 * @param __FLAG__ specifies the flag to check. 1819 * This parameter can be one of the following values: 1820 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. 1821 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. 1822 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. 1823 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. 1824 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. 1825 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. 1826 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. 1827 * @arg RCC_FLAG_PINRST: Pin reset. 1828 * @arg RCC_FLAG_PORRST: POR/PDR reset. 1829 * @arg RCC_FLAG_SFTRST: Software reset. 1830 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. 1831 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. 1832 * @arg RCC_FLAG_LPWRRST: Low Power reset. 1833 * @retval The new state of __FLAG__ (TRUE or FALSE). 1834 */ 1835 #define RCC_FLAG_MASK ((uint8_t)0x1FU) 1836 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 1837 1838 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)) 1839 /** 1840 * @} 1841 */ 1842 1843 /** 1844 * @} 1845 */ 1846 1847 /* Include RCC HAL Extended module */ 1848 #include "stm32f2xx_hal_rcc_ex.h" 1849 /* Exported functions --------------------------------------------------------*/ 1850 /** @addtogroup RCC_Exported_Functions 1851 * @{ 1852 */ 1853 1854 /** @addtogroup RCC_Exported_Functions_Group1 1855 * @{ 1856 */ 1857 /* Initialization and de-initialization functions ******************************/ 1858 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1859 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1860 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1861 /** 1862 * @} 1863 */ 1864 1865 /** @addtogroup RCC_Exported_Functions_Group2 1866 * @{ 1867 */ 1868 /* Peripheral Control functions ************************************************/ 1869 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1870 void HAL_RCC_EnableCSS(void); 1871 void HAL_RCC_DisableCSS(void); 1872 uint32_t HAL_RCC_GetSysClockFreq(void); 1873 uint32_t HAL_RCC_GetHCLKFreq(void); 1874 uint32_t HAL_RCC_GetPCLK1Freq(void); 1875 uint32_t HAL_RCC_GetPCLK2Freq(void); 1876 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1877 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1878 1879 /* CSS NMI IRQ handler */ 1880 void HAL_RCC_NMI_IRQHandler(void); 1881 1882 /* User Callbacks in non blocking mode (IT mode) */ 1883 void HAL_RCC_CSSCallback(void); 1884 1885 /** 1886 * @} 1887 */ 1888 1889 /** 1890 * @} 1891 */ 1892 1893 /* Private types -------------------------------------------------------------*/ 1894 /* Private variables ---------------------------------------------------------*/ 1895 /* Private constants ---------------------------------------------------------*/ 1896 /** @defgroup RCC_Private_Constants RCC Private Constants 1897 * @{ 1898 */ 1899 1900 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion 1901 * @brief RCC registers bit address in the alias region 1902 * @{ 1903 */ 1904 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 1905 /* --- CR Register ---*/ 1906 /* Alias word address of HSION bit */ 1907 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) 1908 #define RCC_HSION_BIT_NUMBER 0x00U 1909 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) 1910 /* Alias word address of CSSON bit */ 1911 #define RCC_CSSON_BIT_NUMBER 0x13U 1912 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) 1913 /* Alias word address of PLLON bit */ 1914 #define RCC_PLLON_BIT_NUMBER 0x18U 1915 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) 1916 /* Alias word address of PLLI2SON bit */ 1917 #define RCC_PLLI2SON_BIT_NUMBER 0x1AU 1918 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) 1919 1920 /* --- CFGR Register ---*/ 1921 /* Alias word address of I2SSRC bit */ 1922 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) 1923 #define RCC_I2SSRC_BIT_NUMBER 0x17U 1924 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) 1925 1926 /* --- BDCR Register ---*/ 1927 /* Alias word address of RTCEN bit */ 1928 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) 1929 #define RCC_RTCEN_BIT_NUMBER 0x0FU 1930 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) 1931 /* Alias word address of BDRST bit */ 1932 #define RCC_BDRST_BIT_NUMBER 0x10U 1933 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) 1934 1935 /* --- CSR Register ---*/ 1936 /* Alias word address of LSION bit */ 1937 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) 1938 #define RCC_LSION_BIT_NUMBER 0x00U 1939 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) 1940 1941 /* CR register byte 3 (Bits[23:16]) base address */ 1942 #define RCC_CR_BYTE2_ADDRESS 0x40023802U 1943 1944 /* CIR register byte 2 (Bits[15:8]) base address */ 1945 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) 1946 1947 /* CIR register byte 3 (Bits[23:16]) base address */ 1948 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) 1949 1950 /* BDCR register base address */ 1951 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) 1952 1953 #define RCC_DBP_TIMEOUT_VALUE 2U 1954 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 1955 1956 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 1957 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */ 1958 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */ 1959 1960 #define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 100 ms */ 1961 /** 1962 * @} 1963 */ 1964 1965 /** 1966 * @} 1967 */ 1968 1969 /* Private macros ------------------------------------------------------------*/ 1970 /** @defgroup RCC_Private_Macros RCC Private Macros 1971 * @{ 1972 */ 1973 1974 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 1975 * @{ 1976 */ 1977 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) 1978 1979 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 1980 ((HSE) == RCC_HSE_BYPASS)) 1981 1982 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 1983 ((LSE) == RCC_LSE_BYPASS)) 1984 1985 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 1986 1987 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 1988 1989 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) 1990 1991 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 1992 ((SOURCE) == RCC_PLLSOURCE_HSE)) 1993 1994 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 1995 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 1996 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) 1997 1998 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 1999 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 2000 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 2001 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 2002 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 2003 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 2004 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ 2005 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 2006 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 2007 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 2008 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ 2009 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 2010 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ 2011 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 2012 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ 2013 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 2014 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ 2015 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 2016 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ 2017 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 2018 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ 2019 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 2020 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ 2021 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 2022 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ 2023 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 2024 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ 2025 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 2026 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ 2027 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 2028 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ 2029 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) 2030 2031 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) 2032 2033 #define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U)) 2034 2035 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) 2036 2037 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 2038 2039 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ 2040 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ 2041 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ 2042 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ 2043 ((HCLK) == RCC_SYSCLK_DIV512)) 2044 2045 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) 2046 2047 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ 2048 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ 2049 ((PCLK) == RCC_HCLK_DIV16)) 2050 2051 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 2052 2053 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 2054 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) 2055 2056 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ 2057 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) 2058 2059 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 2060 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 2061 ((DIV) == RCC_MCODIV_5)) 2062 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) 2063 2064 /** 2065 * @} 2066 */ 2067 2068 /** 2069 * @} 2070 */ 2071 2072 /** 2073 * @} 2074 */ 2075 2076 /** 2077 * @} 2078 */ 2079 2080 #ifdef __cplusplus 2081 } 2082 #endif 2083 2084 #endif /* __STM32F2xx_HAL_RCC_H */ 2085 2086
