1 /**
2   ******************************************************************************
3   * @file    stm32f410rx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - peripherals registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32f410rx
30   * @{
31   */
32 
33 #ifndef __STM32F410Rx_H
34 #define __STM32F410Rx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46   */
47 #define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
48 #define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32F4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
69   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
70   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
71   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
72   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
73   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
74   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
75   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
76 /******  STM32 specific Interrupt Numbers **********************************************************************/
77   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
78   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
79   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
80   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
81   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
82   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
83   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
84   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
85   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
86   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
87   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
88   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
89   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
90   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
91   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
92   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
93   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
94   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
95   ADC_IRQn                    = 18,     /*!< ADC1 global Interrupts                                            */
96   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
97   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
98    TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                            */
99   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
100   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
101   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
102   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
103   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
104   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
105   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
106   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
107   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
108   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
109   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
110   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
111   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
112   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
113   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global Interrupt and DAC Global Interrupt                    */
114   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
115   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
116   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
117   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
118   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
119   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
120   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
121   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
122   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
123   RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
124   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
125   SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
126   FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */
127   FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */
128   LPTIM1_IRQn                 = 97      /*!< LPTIM1 interrupt                                                  */
129 } IRQn_Type;
130 
131 /**
132   * @}
133   */
134 
135 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
136 #include "system_stm32f4xx.h"
137 #include <stdint.h>
138 
139 /** @addtogroup Peripheral_registers_structures
140   * @{
141   */
142 
143 /**
144   * @brief Analog to Digital Converter
145   */
146 
147 typedef struct
148 {
149   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
150   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
151   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
152   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
153   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
154   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
155   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
156   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
157   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
158   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
159   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
160   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
161   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
162   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
163   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
164   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
165   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
166   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
167   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
168   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
169 } ADC_TypeDef;
170 
171 typedef struct
172 {
173   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
174   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
175   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
176                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
177 } ADC_Common_TypeDef;
178 
179 /**
180   * @brief CRC calculation unit
181   */
182 
183 typedef struct
184 {
185   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
186   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
187   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
188   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
189   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
190 } CRC_TypeDef;
191 
192 /**
193   * @brief Digital to Analog Converter
194   */
195 
196 typedef struct
197 {
198   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
199   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
200   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
201   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
202   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
203   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
204   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
205   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
206   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
207   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
208   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
209   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
210   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
211   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
212 } DAC_TypeDef;
213 
214 /**
215   * @brief Debug MCU
216   */
217 
218 typedef struct
219 {
220   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
221   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
222   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
223   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
224 }DBGMCU_TypeDef;
225 
226 
227 /**
228   * @brief DMA Controller
229   */
230 
231 typedef struct
232 {
233   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
234   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
235   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
236   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
237   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
238   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
239 } DMA_Stream_TypeDef;
240 
241 typedef struct
242 {
243   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
244   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
245   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
246   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
247 } DMA_TypeDef;
248 
249 /**
250   * @brief External Interrupt/Event Controller
251   */
252 
253 typedef struct
254 {
255   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
256   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
257   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
258   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
259   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
260   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
261 } EXTI_TypeDef;
262 
263 /**
264   * @brief FLASH Registers
265   */
266 
267 typedef struct
268 {
269   __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
270   __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
271   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
272   __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
273   __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
274   __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
275   __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
276 } FLASH_TypeDef;
277 
278 /**
279   * @brief General Purpose I/O
280   */
281 
282 typedef struct
283 {
284   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
285   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
286   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
287   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
288   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
289   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
290   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
291   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
292   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
293 } GPIO_TypeDef;
294 
295 /**
296   * @brief System configuration controller
297   */
298 
299 typedef struct
300 {
301   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
302   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
303   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
304   uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */
305   __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */
306   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
307   __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x24      */
308 } SYSCFG_TypeDef;
309 
310 /**
311   * @brief Inter-integrated Circuit Interface
312   */
313 
314 typedef struct
315 {
316   __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
317   __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
318   __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
319   __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
320   __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
321   __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
322   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
323   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
324   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
325   __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
326 } I2C_TypeDef;
327 
328 /**
329   * @brief Inter-integrated Circuit Interface
330   */
331 
332 typedef struct
333 {
334   __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */
335   __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */
336   __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */
337   __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */
338   __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */
339   __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */
340   __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
341   __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */
342   __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */
343   __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */
344   __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */
345 } FMPI2C_TypeDef;
346 
347 /**
348   * @brief Independent WATCHDOG
349   */
350 
351 typedef struct
352 {
353   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
354   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
355   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
356   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
357 } IWDG_TypeDef;
358 
359 
360 /**
361   * @brief Power Control
362   */
363 
364 typedef struct
365 {
366   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
367   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
368 } PWR_TypeDef;
369 
370 /**
371   * @brief Reset and Clock Control
372   */
373 
374 typedef struct
375 {
376   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
377   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
378   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
379   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
380   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
381   uint32_t      RESERVED0[3];  /*!< Reserved, 0x14-0x1C                                                               */
382   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
383   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
384   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
385   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
386   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                               */
387   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
388   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
389   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
390   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
391   uint32_t      RESERVED4[3];  /*!< Reserved, 0x54-0x5C                                                               */
392   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
393   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
394   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
395   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
396   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
397   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
398   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
399   uint32_t      RESERVED7[2];   /*!< Reserved, 0x84-0x88                                                              */
400   __IO uint32_t DCKCFGR;       /*!< RCC DCKCFGR configuration register,                         Address offset: 0x8C  */
401   __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90  */
402   __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */
403 } RCC_TypeDef;
404 
405 /**
406   * @brief Real-Time Clock
407   */
408 
409 typedef struct
410 {
411   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
412   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
413   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
414   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
415   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
416   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
417   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
418   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
419   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
420   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
421   __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
422   __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
423   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
424   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
425   __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
426   __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
427   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
428   __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
429   __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
430   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
431   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
432   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
433   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
434   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
435   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
436   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
437   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
438   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
439   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
440   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
441   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
442   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
443   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
444   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
445   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
446   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
447   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
448   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
449   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
450   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
451 } RTC_TypeDef;
452 
453 /**
454   * @brief Serial Peripheral Interface
455   */
456 
457 typedef struct
458 {
459   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
460   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
461   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
462   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
463   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
464   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
465   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
466   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
467   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
468 } SPI_TypeDef;
469 
470 
471 /**
472   * @brief TIM
473   */
474 
475 typedef struct
476 {
477   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
478   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
479   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
480   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
481   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
482   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
483   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
484   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
485   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
486   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
487   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
488   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
489   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
490   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
491   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
492   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
493   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
494   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
495   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
496   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
497   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
498 } TIM_TypeDef;
499 
500 /**
501   * @brief Universal Synchronous Asynchronous Receiver Transmitter
502   */
503 
504 typedef struct
505 {
506   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
507   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
508   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
509   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
510   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
511   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
512   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
513 } USART_TypeDef;
514 
515 /**
516   * @brief Window WATCHDOG
517   */
518 
519 typedef struct
520 {
521   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
522   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
523   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
524 } WWDG_TypeDef;
525 
526 /**
527   * @brief RNG
528   */
529 
530 typedef struct
531 {
532   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
533   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
534   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
535 } RNG_TypeDef;
536 
537 
538 /**
539   * @brief LPTIMER
540   */
541 typedef struct
542 {
543   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
544   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
545   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
546   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
547   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
548   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
549   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
550   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
551   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
552 } LPTIM_TypeDef;
553 
554 /**
555   * @}
556   */
557 
558 /** @addtogroup Peripheral_memory_map
559   * @{
560   */
561 #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
562 #define SRAM1_BASE            0x20000000UL /*!< SRAM1(32 KB) base address in the alias region                              */
563 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
564 #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(32 KB) base address in the bit-band region                           */
565 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
566 #define FLASH_END             0x0801FFFFUL /*!< FLASH end address                                                          */
567 #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
568 #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
569 
570 /* Legacy defines */
571 #define SRAM_BASE             SRAM1_BASE
572 #define SRAM_BB_BASE          SRAM1_BB_BASE
573 
574 /*!< Peripheral memory map */
575 #define APB1PERIPH_BASE       PERIPH_BASE
576 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
577 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
578 
579 /*!< APB1 peripherals */
580 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
581 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
582 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400UL)
583 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
584 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
585 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
586 #define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
587 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
588 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
589 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
590 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
591 #define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)
592 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
593 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
594 
595 /*!< APB2 peripherals */
596 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
597 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
598 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
599 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
600 #define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)
601 /* Legacy define */
602 #define ADC_BASE               ADC1_COMMON_BASE
603 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
604 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
605 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
606 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
607 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
608 #define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)
609 
610 /*!< AHB1 peripherals */
611 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
612 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
613 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
614 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
615 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
616 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
617 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
618 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
619 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
620 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
621 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
622 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
623 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
624 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
625 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
626 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
627 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
628 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
629 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
630 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
631 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
632 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
633 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
634 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
635 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
636 
637 #define RNG_BASE              (PERIPH_BASE + 0x80000UL)
638 
639 /*!< Debug MCU registers base address */
640 #define DBGMCU_BASE           0xE0042000UL
641 
642 #define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
643 #define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
644 #define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
645 /**
646   * @}
647   */
648 
649 /** @addtogroup Peripheral_declaration
650   * @{
651   */
652 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
653 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
654 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
655 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
656 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
657 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
658 #define USART2              ((USART_TypeDef *) USART2_BASE)
659 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
660 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
661 #define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)
662 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
663 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
664 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
665 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
666 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
667 #define USART1              ((USART_TypeDef *) USART1_BASE)
668 #define USART6              ((USART_TypeDef *) USART6_BASE)
669 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
670 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
671 /* Legacy define */
672 #define ADC                  ADC1_COMMON
673 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
674 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
675 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
676 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
677 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
678 #define SPI5                ((SPI_TypeDef *) SPI5_BASE)
679 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
680 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
681 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
682 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
683 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
684 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
685 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
686 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
687 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
688 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
689 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
690 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
691 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
692 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
693 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
694 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
695 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
696 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
697 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
698 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
699 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
700 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
701 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
702 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
703 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
704 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
705 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
706 
707 /**
708   * @}
709   */
710 
711 /** @addtogroup Exported_constants
712   * @{
713   */
714 
715 /** @addtogroup Hardware_Constant_Definition
716   * @{
717   */
718 #define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
719 /**
720   * @}
721   */
722 
723   /** @addtogroup Peripheral_Registers_Bits_Definition
724   * @{
725   */
726 
727 /******************************************************************************/
728 /*                         Peripheral Registers_Bits_Definition               */
729 /******************************************************************************/
730 
731 /******************************************************************************/
732 /*                                                                            */
733 /*                        Analog to Digital Converter                         */
734 /*                                                                            */
735 /******************************************************************************/
736 
737 /********************  Bit definition for ADC_SR register  ********************/
738 #define ADC_SR_AWD_Pos            (0U)
739 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
740 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
741 #define ADC_SR_EOC_Pos            (1U)
742 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
743 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
744 #define ADC_SR_JEOC_Pos           (2U)
745 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
746 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
747 #define ADC_SR_JSTRT_Pos          (3U)
748 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
749 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
750 #define ADC_SR_STRT_Pos           (4U)
751 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
752 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
753 #define ADC_SR_OVR_Pos            (5U)
754 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
755 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
756 
757 /*******************  Bit definition for ADC_CR1 register  ********************/
758 #define ADC_CR1_AWDCH_Pos         (0U)
759 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
760 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
761 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
762 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
763 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
764 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
765 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
766 #define ADC_CR1_EOCIE_Pos         (5U)
767 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
768 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
769 #define ADC_CR1_AWDIE_Pos         (6U)
770 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
771 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
772 #define ADC_CR1_JEOCIE_Pos        (7U)
773 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
774 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
775 #define ADC_CR1_SCAN_Pos          (8U)
776 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
777 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
778 #define ADC_CR1_AWDSGL_Pos        (9U)
779 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
780 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
781 #define ADC_CR1_JAUTO_Pos         (10U)
782 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
783 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
784 #define ADC_CR1_DISCEN_Pos        (11U)
785 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
786 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
787 #define ADC_CR1_JDISCEN_Pos       (12U)
788 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
789 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
790 #define ADC_CR1_DISCNUM_Pos       (13U)
791 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
792 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
793 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
794 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
795 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
796 #define ADC_CR1_JAWDEN_Pos        (22U)
797 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
798 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
799 #define ADC_CR1_AWDEN_Pos         (23U)
800 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
801 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
802 #define ADC_CR1_RES_Pos           (24U)
803 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
804 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
805 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
806 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
807 #define ADC_CR1_OVRIE_Pos         (26U)
808 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
809 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
810 
811 /*******************  Bit definition for ADC_CR2 register  ********************/
812 #define ADC_CR2_ADON_Pos          (0U)
813 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
814 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
815 #define ADC_CR2_CONT_Pos          (1U)
816 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
817 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
818 #define ADC_CR2_DMA_Pos           (8U)
819 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
820 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
821 #define ADC_CR2_DDS_Pos           (9U)
822 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
823 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
824 #define ADC_CR2_EOCS_Pos          (10U)
825 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
826 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
827 #define ADC_CR2_ALIGN_Pos         (11U)
828 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
829 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
830 #define ADC_CR2_JEXTSEL_Pos       (16U)
831 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
832 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
833 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
834 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
835 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
836 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
837 #define ADC_CR2_JEXTEN_Pos        (20U)
838 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
839 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
840 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
841 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
842 #define ADC_CR2_JSWSTART_Pos      (22U)
843 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
844 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
845 #define ADC_CR2_EXTSEL_Pos        (24U)
846 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
847 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
848 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
849 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
850 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
851 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
852 #define ADC_CR2_EXTEN_Pos         (28U)
853 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
854 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
855 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
856 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
857 #define ADC_CR2_SWSTART_Pos       (30U)
858 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
859 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
860 
861 /******************  Bit definition for ADC_SMPR1 register  *******************/
862 #define ADC_SMPR1_SMP10_Pos       (0U)
863 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
864 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
865 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
866 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
867 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
868 #define ADC_SMPR1_SMP11_Pos       (3U)
869 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
870 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
871 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
872 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
873 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
874 #define ADC_SMPR1_SMP12_Pos       (6U)
875 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
876 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
877 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
878 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
879 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
880 #define ADC_SMPR1_SMP13_Pos       (9U)
881 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
882 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
883 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
884 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
885 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
886 #define ADC_SMPR1_SMP14_Pos       (12U)
887 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
888 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
889 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
890 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
891 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
892 #define ADC_SMPR1_SMP15_Pos       (15U)
893 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
894 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
895 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
896 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
897 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
898 #define ADC_SMPR1_SMP16_Pos       (18U)
899 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
900 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
901 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
902 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
903 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
904 #define ADC_SMPR1_SMP17_Pos       (21U)
905 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
906 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
907 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
908 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
909 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
910 #define ADC_SMPR1_SMP18_Pos       (24U)
911 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
912 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
913 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
914 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
915 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
916 
917 /******************  Bit definition for ADC_SMPR2 register  *******************/
918 #define ADC_SMPR2_SMP0_Pos        (0U)
919 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
920 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
921 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
922 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
923 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
924 #define ADC_SMPR2_SMP1_Pos        (3U)
925 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
926 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
927 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
928 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
929 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
930 #define ADC_SMPR2_SMP2_Pos        (6U)
931 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
932 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
933 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
934 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
935 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
936 #define ADC_SMPR2_SMP3_Pos        (9U)
937 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
938 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
939 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
940 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
941 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
942 #define ADC_SMPR2_SMP4_Pos        (12U)
943 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
944 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
945 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
946 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
947 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
948 #define ADC_SMPR2_SMP5_Pos        (15U)
949 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
950 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
951 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
952 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
953 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
954 #define ADC_SMPR2_SMP6_Pos        (18U)
955 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
956 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
957 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
958 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
959 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
960 #define ADC_SMPR2_SMP7_Pos        (21U)
961 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
962 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
963 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
964 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
965 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
966 #define ADC_SMPR2_SMP8_Pos        (24U)
967 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
968 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
969 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
970 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
971 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
972 #define ADC_SMPR2_SMP9_Pos        (27U)
973 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
974 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
975 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
976 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
977 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
978 
979 /******************  Bit definition for ADC_JOFR1 register  *******************/
980 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
981 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
982 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
983 
984 /******************  Bit definition for ADC_JOFR2 register  *******************/
985 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
986 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
987 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
988 
989 /******************  Bit definition for ADC_JOFR3 register  *******************/
990 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
991 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
992 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
993 
994 /******************  Bit definition for ADC_JOFR4 register  *******************/
995 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
996 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
997 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
998 
999 /*******************  Bit definition for ADC_HTR register  ********************/
1000 #define ADC_HTR_HT_Pos            (0U)
1001 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1002 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1003 
1004 /*******************  Bit definition for ADC_LTR register  ********************/
1005 #define ADC_LTR_LT_Pos            (0U)
1006 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1007 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1008 
1009 /*******************  Bit definition for ADC_SQR1 register  *******************/
1010 #define ADC_SQR1_SQ13_Pos         (0U)
1011 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1012 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1013 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1014 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1015 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1016 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1017 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1018 #define ADC_SQR1_SQ14_Pos         (5U)
1019 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1020 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1021 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1022 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1023 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1024 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1025 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1026 #define ADC_SQR1_SQ15_Pos         (10U)
1027 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1028 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1029 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1030 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1031 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1032 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1033 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1034 #define ADC_SQR1_SQ16_Pos         (15U)
1035 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1036 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1037 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1038 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1039 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1040 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1041 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1042 #define ADC_SQR1_L_Pos            (20U)
1043 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1044 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1045 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1046 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1047 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1048 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1049 
1050 /*******************  Bit definition for ADC_SQR2 register  *******************/
1051 #define ADC_SQR2_SQ7_Pos          (0U)
1052 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1053 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1054 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1055 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1056 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1057 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1058 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1059 #define ADC_SQR2_SQ8_Pos          (5U)
1060 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1061 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1062 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1063 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1064 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1065 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1066 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1067 #define ADC_SQR2_SQ9_Pos          (10U)
1068 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1069 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1070 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1071 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1072 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1073 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1074 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1075 #define ADC_SQR2_SQ10_Pos         (15U)
1076 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1077 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1078 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1079 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1080 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1081 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1082 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1083 #define ADC_SQR2_SQ11_Pos         (20U)
1084 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1085 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1086 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1087 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1088 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1089 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1090 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1091 #define ADC_SQR2_SQ12_Pos         (25U)
1092 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1093 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1094 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1095 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1096 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1097 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1098 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1099 
1100 /*******************  Bit definition for ADC_SQR3 register  *******************/
1101 #define ADC_SQR3_SQ1_Pos          (0U)
1102 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1103 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1104 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1105 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1106 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1107 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1108 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1109 #define ADC_SQR3_SQ2_Pos          (5U)
1110 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1111 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1112 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1113 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1114 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1115 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1116 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1117 #define ADC_SQR3_SQ3_Pos          (10U)
1118 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1119 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1120 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1121 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1122 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1123 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1124 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1125 #define ADC_SQR3_SQ4_Pos          (15U)
1126 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1127 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1128 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1129 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1130 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1131 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1132 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1133 #define ADC_SQR3_SQ5_Pos          (20U)
1134 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1135 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1136 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1137 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1138 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1139 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1140 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1141 #define ADC_SQR3_SQ6_Pos          (25U)
1142 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1143 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1144 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1145 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1146 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1147 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1148 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1149 
1150 /*******************  Bit definition for ADC_JSQR register  *******************/
1151 #define ADC_JSQR_JSQ1_Pos         (0U)
1152 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1153 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1154 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1155 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1156 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1157 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1158 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1159 #define ADC_JSQR_JSQ2_Pos         (5U)
1160 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1161 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1162 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1163 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1164 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1165 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1166 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1167 #define ADC_JSQR_JSQ3_Pos         (10U)
1168 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1169 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1170 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1171 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1172 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1173 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1174 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1175 #define ADC_JSQR_JSQ4_Pos         (15U)
1176 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1177 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1178 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1179 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1180 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1181 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1182 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1183 #define ADC_JSQR_JL_Pos           (20U)
1184 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1185 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1186 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1187 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1188 
1189 /*******************  Bit definition for ADC_JDR1 register  *******************/
1190 #define ADC_JDR1_JDATA_Pos        (0U)
1191 #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1192 #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1193 
1194 /*******************  Bit definition for ADC_JDR2 register  *******************/
1195 #define ADC_JDR2_JDATA_Pos        (0U)
1196 #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1197 #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1198 
1199 /*******************  Bit definition for ADC_JDR3 register  *******************/
1200 #define ADC_JDR3_JDATA_Pos        (0U)
1201 #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1202 #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1203 
1204 /*******************  Bit definition for ADC_JDR4 register  *******************/
1205 #define ADC_JDR4_JDATA_Pos        (0U)
1206 #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1207 #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1208 
1209 /********************  Bit definition for ADC_DR register  ********************/
1210 #define ADC_DR_DATA_Pos           (0U)
1211 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1212 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1213 #define ADC_DR_ADC2DATA_Pos       (16U)
1214 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1215 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1216 
1217 /*******************  Bit definition for ADC_CSR register  ********************/
1218 #define ADC_CSR_AWD1_Pos          (0U)
1219 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1220 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1221 #define ADC_CSR_EOC1_Pos          (1U)
1222 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1223 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1224 #define ADC_CSR_JEOC1_Pos         (2U)
1225 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1226 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1227 #define ADC_CSR_JSTRT1_Pos        (3U)
1228 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1229 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1230 #define ADC_CSR_STRT1_Pos         (4U)
1231 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1232 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1233 #define ADC_CSR_OVR1_Pos          (5U)
1234 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1235 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1236 
1237 /* Legacy defines */
1238 #define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
1239 
1240 /*******************  Bit definition for ADC_CCR register  ********************/
1241 #define ADC_CCR_MULTI_Pos         (0U)
1242 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1243 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1244 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1245 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1246 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1247 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1248 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1249 #define ADC_CCR_DELAY_Pos         (8U)
1250 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1251 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1252 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1253 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1254 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1255 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1256 #define ADC_CCR_DDS_Pos           (13U)
1257 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1258 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1259 #define ADC_CCR_DMA_Pos           (14U)
1260 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1261 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1262 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1263 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1264 #define ADC_CCR_ADCPRE_Pos        (16U)
1265 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1266 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1267 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1268 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1269 #define ADC_CCR_VBATE_Pos         (22U)
1270 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1271 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1272 #define ADC_CCR_TSVREFE_Pos       (23U)
1273 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1274 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1275 
1276 /*******************  Bit definition for ADC_CDR register  ********************/
1277 #define ADC_CDR_DATA1_Pos         (0U)
1278 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1279 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1280 #define ADC_CDR_DATA2_Pos         (16U)
1281 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1282 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1283 
1284 /* Legacy defines */
1285 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1286 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1287 
1288 /******************************************************************************/
1289 /*                                                                            */
1290 /*                          CRC calculation unit                              */
1291 /*                                                                            */
1292 /******************************************************************************/
1293 /*******************  Bit definition for CRC_DR register  *********************/
1294 #define CRC_DR_DR_Pos       (0U)
1295 #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
1296 #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
1297 
1298 
1299 /*******************  Bit definition for CRC_IDR register  ********************/
1300 #define CRC_IDR_IDR_Pos     (0U)
1301 #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
1302 #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
1303 
1304 
1305 /********************  Bit definition for CRC_CR register  ********************/
1306 #define CRC_CR_RESET_Pos    (0U)
1307 #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
1308 #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
1309 
1310 /******************************************************************************/
1311 /*                                                                            */
1312 /*                      Digital to Analog Converter                           */
1313 /*                                                                            */
1314 /******************************************************************************/
1315 /********************  Bit definition for DAC_CR register  ********************/
1316 #define DAC_CR_EN1_Pos              (0U)
1317 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
1318 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
1319 #define DAC_CR_BOFF1_Pos            (1U)
1320 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
1321 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
1322 #define DAC_CR_TEN1_Pos             (2U)
1323 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
1324 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
1325 
1326 #define DAC_CR_TSEL1_Pos            (3U)
1327 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
1328 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1329 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
1330 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
1331 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
1332 
1333 #define DAC_CR_WAVE1_Pos            (6U)
1334 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
1335 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1336 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
1337 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
1338 
1339 #define DAC_CR_MAMP1_Pos            (8U)
1340 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
1341 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1342 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
1343 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
1344 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
1345 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
1346 
1347 #define DAC_CR_DMAEN1_Pos           (12U)
1348 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
1349 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
1350 #define DAC_CR_DMAUDRIE1_Pos        (13U)
1351 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
1352 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
1353 #define DAC_CR_EN2_Pos              (16U)
1354 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
1355 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
1356 #define DAC_CR_BOFF2_Pos            (17U)
1357 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
1358 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
1359 #define DAC_CR_TEN2_Pos             (18U)
1360 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
1361 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
1362 
1363 #define DAC_CR_TSEL2_Pos            (19U)
1364 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
1365 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1366 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
1367 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
1368 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
1369 
1370 #define DAC_CR_WAVE2_Pos            (22U)
1371 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
1372 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1373 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
1374 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
1375 
1376 #define DAC_CR_MAMP2_Pos            (24U)
1377 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
1378 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1379 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
1380 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
1381 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
1382 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
1383 
1384 #define DAC_CR_DMAEN2_Pos           (28U)
1385 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
1386 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
1387 #define DAC_CR_DMAUDRIE2_Pos        (29U)
1388 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
1389 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
1390 
1391 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1392 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
1393 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
1394 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
1395 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
1396 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
1397 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
1398 
1399 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1400 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
1401 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
1402 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1403 
1404 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1405 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
1406 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
1407 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1408 
1409 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1410 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
1411 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
1412 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1413 
1414 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
1415 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
1416 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
1417 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1418 
1419 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
1420 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
1421 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
1422 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1423 
1424 /******************  Bit definition for DAC_DHR8R2 register  ******************/
1425 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
1426 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
1427 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1428 
1429 /*****************  Bit definition for DAC_DHR12RD register  ******************/
1430 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
1431 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
1432 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1433 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
1434 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
1435 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1436 
1437 /*****************  Bit definition for DAC_DHR12LD register  ******************/
1438 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
1439 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
1440 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1441 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
1442 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
1443 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1444 
1445 /******************  Bit definition for DAC_DHR8RD register  ******************/
1446 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
1447 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
1448 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1449 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
1450 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
1451 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1452 
1453 /*******************  Bit definition for DAC_DOR1 register  *******************/
1454 #define DAC_DOR1_DACC1DOR_Pos       (0U)
1455 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
1456 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
1457 
1458 /*******************  Bit definition for DAC_DOR2 register  *******************/
1459 #define DAC_DOR2_DACC2DOR_Pos       (0U)
1460 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
1461 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
1462 
1463 /********************  Bit definition for DAC_SR register  ********************/
1464 #define DAC_SR_DMAUDR1_Pos          (13U)
1465 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
1466 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
1467 #define DAC_SR_DMAUDR2_Pos          (29U)
1468 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
1469 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
1470 
1471 
1472 /******************************************************************************/
1473 /*                                                                            */
1474 /*                             DMA Controller                                 */
1475 /*                                                                            */
1476 /******************************************************************************/
1477 /********************  Bits definition for DMA_SxCR register  *****************/
1478 #define DMA_SxCR_CHSEL_Pos       (25U)
1479 #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
1480 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
1481 #define DMA_SxCR_CHSEL_0         0x02000000U
1482 #define DMA_SxCR_CHSEL_1         0x04000000U
1483 #define DMA_SxCR_CHSEL_2         0x08000000U
1484 #define DMA_SxCR_MBURST_Pos      (23U)
1485 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
1486 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
1487 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
1488 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
1489 #define DMA_SxCR_PBURST_Pos      (21U)
1490 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
1491 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
1492 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
1493 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
1494 #define DMA_SxCR_CT_Pos          (19U)
1495 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
1496 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
1497 #define DMA_SxCR_DBM_Pos         (18U)
1498 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
1499 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
1500 #define DMA_SxCR_PL_Pos          (16U)
1501 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
1502 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
1503 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
1504 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
1505 #define DMA_SxCR_PINCOS_Pos      (15U)
1506 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
1507 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
1508 #define DMA_SxCR_MSIZE_Pos       (13U)
1509 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
1510 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
1511 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
1512 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
1513 #define DMA_SxCR_PSIZE_Pos       (11U)
1514 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
1515 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
1516 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
1517 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
1518 #define DMA_SxCR_MINC_Pos        (10U)
1519 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
1520 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
1521 #define DMA_SxCR_PINC_Pos        (9U)
1522 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
1523 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
1524 #define DMA_SxCR_CIRC_Pos        (8U)
1525 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
1526 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
1527 #define DMA_SxCR_DIR_Pos         (6U)
1528 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
1529 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
1530 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
1531 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
1532 #define DMA_SxCR_PFCTRL_Pos      (5U)
1533 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
1534 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
1535 #define DMA_SxCR_TCIE_Pos        (4U)
1536 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
1537 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
1538 #define DMA_SxCR_HTIE_Pos        (3U)
1539 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
1540 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
1541 #define DMA_SxCR_TEIE_Pos        (2U)
1542 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
1543 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
1544 #define DMA_SxCR_DMEIE_Pos       (1U)
1545 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
1546 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
1547 #define DMA_SxCR_EN_Pos          (0U)
1548 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
1549 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
1550 
1551 /* Legacy defines */
1552 #define DMA_SxCR_ACK_Pos         (20U)
1553 #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
1554 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
1555 
1556 /********************  Bits definition for DMA_SxCNDTR register  **************/
1557 #define DMA_SxNDT_Pos            (0U)
1558 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
1559 #define DMA_SxNDT                DMA_SxNDT_Msk
1560 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
1561 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
1562 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
1563 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
1564 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
1565 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
1566 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
1567 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
1568 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
1569 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
1570 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
1571 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
1572 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
1573 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
1574 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
1575 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
1576 
1577 /********************  Bits definition for DMA_SxFCR register  ****************/
1578 #define DMA_SxFCR_FEIE_Pos       (7U)
1579 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
1580 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
1581 #define DMA_SxFCR_FS_Pos         (3U)
1582 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
1583 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
1584 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
1585 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
1586 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
1587 #define DMA_SxFCR_DMDIS_Pos      (2U)
1588 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
1589 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
1590 #define DMA_SxFCR_FTH_Pos        (0U)
1591 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
1592 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
1593 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
1594 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
1595 
1596 /********************  Bits definition for DMA_LISR register  *****************/
1597 #define DMA_LISR_TCIF3_Pos       (27U)
1598 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
1599 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
1600 #define DMA_LISR_HTIF3_Pos       (26U)
1601 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
1602 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
1603 #define DMA_LISR_TEIF3_Pos       (25U)
1604 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
1605 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
1606 #define DMA_LISR_DMEIF3_Pos      (24U)
1607 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
1608 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
1609 #define DMA_LISR_FEIF3_Pos       (22U)
1610 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
1611 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
1612 #define DMA_LISR_TCIF2_Pos       (21U)
1613 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
1614 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
1615 #define DMA_LISR_HTIF2_Pos       (20U)
1616 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
1617 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
1618 #define DMA_LISR_TEIF2_Pos       (19U)
1619 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
1620 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
1621 #define DMA_LISR_DMEIF2_Pos      (18U)
1622 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
1623 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
1624 #define DMA_LISR_FEIF2_Pos       (16U)
1625 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
1626 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
1627 #define DMA_LISR_TCIF1_Pos       (11U)
1628 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
1629 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
1630 #define DMA_LISR_HTIF1_Pos       (10U)
1631 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
1632 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
1633 #define DMA_LISR_TEIF1_Pos       (9U)
1634 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
1635 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
1636 #define DMA_LISR_DMEIF1_Pos      (8U)
1637 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
1638 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
1639 #define DMA_LISR_FEIF1_Pos       (6U)
1640 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
1641 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
1642 #define DMA_LISR_TCIF0_Pos       (5U)
1643 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
1644 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
1645 #define DMA_LISR_HTIF0_Pos       (4U)
1646 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
1647 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
1648 #define DMA_LISR_TEIF0_Pos       (3U)
1649 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
1650 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
1651 #define DMA_LISR_DMEIF0_Pos      (2U)
1652 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
1653 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
1654 #define DMA_LISR_FEIF0_Pos       (0U)
1655 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
1656 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
1657 
1658 /********************  Bits definition for DMA_HISR register  *****************/
1659 #define DMA_HISR_TCIF7_Pos       (27U)
1660 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
1661 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
1662 #define DMA_HISR_HTIF7_Pos       (26U)
1663 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
1664 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
1665 #define DMA_HISR_TEIF7_Pos       (25U)
1666 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
1667 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
1668 #define DMA_HISR_DMEIF7_Pos      (24U)
1669 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
1670 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
1671 #define DMA_HISR_FEIF7_Pos       (22U)
1672 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
1673 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
1674 #define DMA_HISR_TCIF6_Pos       (21U)
1675 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
1676 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
1677 #define DMA_HISR_HTIF6_Pos       (20U)
1678 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
1679 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
1680 #define DMA_HISR_TEIF6_Pos       (19U)
1681 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
1682 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
1683 #define DMA_HISR_DMEIF6_Pos      (18U)
1684 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
1685 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
1686 #define DMA_HISR_FEIF6_Pos       (16U)
1687 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
1688 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
1689 #define DMA_HISR_TCIF5_Pos       (11U)
1690 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
1691 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
1692 #define DMA_HISR_HTIF5_Pos       (10U)
1693 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
1694 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
1695 #define DMA_HISR_TEIF5_Pos       (9U)
1696 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
1697 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
1698 #define DMA_HISR_DMEIF5_Pos      (8U)
1699 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
1700 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
1701 #define DMA_HISR_FEIF5_Pos       (6U)
1702 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
1703 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
1704 #define DMA_HISR_TCIF4_Pos       (5U)
1705 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
1706 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
1707 #define DMA_HISR_HTIF4_Pos       (4U)
1708 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
1709 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
1710 #define DMA_HISR_TEIF4_Pos       (3U)
1711 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
1712 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
1713 #define DMA_HISR_DMEIF4_Pos      (2U)
1714 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
1715 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
1716 #define DMA_HISR_FEIF4_Pos       (0U)
1717 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
1718 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
1719 
1720 /********************  Bits definition for DMA_LIFCR register  ****************/
1721 #define DMA_LIFCR_CTCIF3_Pos     (27U)
1722 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
1723 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
1724 #define DMA_LIFCR_CHTIF3_Pos     (26U)
1725 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
1726 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
1727 #define DMA_LIFCR_CTEIF3_Pos     (25U)
1728 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
1729 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
1730 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
1731 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
1732 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
1733 #define DMA_LIFCR_CFEIF3_Pos     (22U)
1734 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
1735 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
1736 #define DMA_LIFCR_CTCIF2_Pos     (21U)
1737 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
1738 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
1739 #define DMA_LIFCR_CHTIF2_Pos     (20U)
1740 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
1741 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
1742 #define DMA_LIFCR_CTEIF2_Pos     (19U)
1743 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
1744 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
1745 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
1746 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
1747 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
1748 #define DMA_LIFCR_CFEIF2_Pos     (16U)
1749 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
1750 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
1751 #define DMA_LIFCR_CTCIF1_Pos     (11U)
1752 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
1753 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
1754 #define DMA_LIFCR_CHTIF1_Pos     (10U)
1755 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
1756 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
1757 #define DMA_LIFCR_CTEIF1_Pos     (9U)
1758 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
1759 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
1760 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
1761 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
1762 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
1763 #define DMA_LIFCR_CFEIF1_Pos     (6U)
1764 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
1765 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
1766 #define DMA_LIFCR_CTCIF0_Pos     (5U)
1767 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
1768 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
1769 #define DMA_LIFCR_CHTIF0_Pos     (4U)
1770 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
1771 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
1772 #define DMA_LIFCR_CTEIF0_Pos     (3U)
1773 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
1774 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
1775 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
1776 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
1777 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
1778 #define DMA_LIFCR_CFEIF0_Pos     (0U)
1779 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
1780 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
1781 
1782 /********************  Bits definition for DMA_HIFCR  register  ****************/
1783 #define DMA_HIFCR_CTCIF7_Pos     (27U)
1784 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
1785 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
1786 #define DMA_HIFCR_CHTIF7_Pos     (26U)
1787 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
1788 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
1789 #define DMA_HIFCR_CTEIF7_Pos     (25U)
1790 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
1791 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
1792 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
1793 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
1794 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
1795 #define DMA_HIFCR_CFEIF7_Pos     (22U)
1796 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
1797 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
1798 #define DMA_HIFCR_CTCIF6_Pos     (21U)
1799 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
1800 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
1801 #define DMA_HIFCR_CHTIF6_Pos     (20U)
1802 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
1803 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
1804 #define DMA_HIFCR_CTEIF6_Pos     (19U)
1805 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
1806 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
1807 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
1808 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
1809 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
1810 #define DMA_HIFCR_CFEIF6_Pos     (16U)
1811 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
1812 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
1813 #define DMA_HIFCR_CTCIF5_Pos     (11U)
1814 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
1815 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
1816 #define DMA_HIFCR_CHTIF5_Pos     (10U)
1817 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
1818 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
1819 #define DMA_HIFCR_CTEIF5_Pos     (9U)
1820 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
1821 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
1822 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
1823 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
1824 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
1825 #define DMA_HIFCR_CFEIF5_Pos     (6U)
1826 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
1827 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
1828 #define DMA_HIFCR_CTCIF4_Pos     (5U)
1829 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
1830 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
1831 #define DMA_HIFCR_CHTIF4_Pos     (4U)
1832 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
1833 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
1834 #define DMA_HIFCR_CTEIF4_Pos     (3U)
1835 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
1836 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
1837 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
1838 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
1839 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
1840 #define DMA_HIFCR_CFEIF4_Pos     (0U)
1841 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
1842 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
1843 
1844 /******************  Bit definition for DMA_SxPAR register  ********************/
1845 #define DMA_SxPAR_PA_Pos         (0U)
1846 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
1847 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
1848 
1849 /******************  Bit definition for DMA_SxM0AR register  ********************/
1850 #define DMA_SxM0AR_M0A_Pos       (0U)
1851 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
1852 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
1853 
1854 /******************  Bit definition for DMA_SxM1AR register  ********************/
1855 #define DMA_SxM1AR_M1A_Pos       (0U)
1856 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
1857 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
1858 
1859 
1860 /******************************************************************************/
1861 /*                                                                            */
1862 /*                    External Interrupt/Event Controller                     */
1863 /*                                                                            */
1864 /******************************************************************************/
1865 /*******************  Bit definition for EXTI_IMR register  *******************/
1866 #define EXTI_IMR_MR0_Pos          (0U)
1867 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
1868 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
1869 #define EXTI_IMR_MR1_Pos          (1U)
1870 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
1871 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
1872 #define EXTI_IMR_MR2_Pos          (2U)
1873 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
1874 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
1875 #define EXTI_IMR_MR3_Pos          (3U)
1876 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
1877 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
1878 #define EXTI_IMR_MR4_Pos          (4U)
1879 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
1880 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
1881 #define EXTI_IMR_MR5_Pos          (5U)
1882 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
1883 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
1884 #define EXTI_IMR_MR6_Pos          (6U)
1885 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
1886 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
1887 #define EXTI_IMR_MR7_Pos          (7U)
1888 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
1889 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
1890 #define EXTI_IMR_MR8_Pos          (8U)
1891 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
1892 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
1893 #define EXTI_IMR_MR9_Pos          (9U)
1894 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
1895 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
1896 #define EXTI_IMR_MR10_Pos         (10U)
1897 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
1898 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
1899 #define EXTI_IMR_MR11_Pos         (11U)
1900 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
1901 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
1902 #define EXTI_IMR_MR12_Pos         (12U)
1903 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
1904 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
1905 #define EXTI_IMR_MR13_Pos         (13U)
1906 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
1907 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
1908 #define EXTI_IMR_MR14_Pos         (14U)
1909 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
1910 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
1911 #define EXTI_IMR_MR15_Pos         (15U)
1912 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
1913 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
1914 #define EXTI_IMR_MR16_Pos         (16U)
1915 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
1916 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
1917 #define EXTI_IMR_MR17_Pos         (17U)
1918 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
1919 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
1920 #define EXTI_IMR_MR18_Pos         (18U)
1921 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
1922 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
1923 #define EXTI_IMR_MR19_Pos         (19U)
1924 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
1925 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
1926 #define EXTI_IMR_MR20_Pos         (20U)
1927 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
1928 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
1929 #define EXTI_IMR_MR21_Pos         (21U)
1930 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
1931 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
1932 #define EXTI_IMR_MR22_Pos         (22U)
1933 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
1934 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
1935 #define EXTI_IMR_MR23_Pos         (23U)
1936 #define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */
1937 #define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */
1938 
1939 /* Reference Defines */
1940 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
1941 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
1942 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
1943 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
1944 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
1945 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
1946 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
1947 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
1948 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
1949 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
1950 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
1951 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
1952 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
1953 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
1954 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
1955 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
1956 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
1957 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
1958 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
1959 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
1960 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
1961 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
1962 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
1963 #define  EXTI_IMR_IM23                       EXTI_IMR_MR23
1964 #define EXTI_IMR_IM_Pos           (0U)
1965 #define EXTI_IMR_IM_Msk           (0xFFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */
1966 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
1967 
1968 /*******************  Bit definition for EXTI_EMR register  *******************/
1969 #define EXTI_EMR_MR0_Pos          (0U)
1970 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
1971 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
1972 #define EXTI_EMR_MR1_Pos          (1U)
1973 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
1974 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
1975 #define EXTI_EMR_MR2_Pos          (2U)
1976 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
1977 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
1978 #define EXTI_EMR_MR3_Pos          (3U)
1979 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
1980 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
1981 #define EXTI_EMR_MR4_Pos          (4U)
1982 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
1983 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
1984 #define EXTI_EMR_MR5_Pos          (5U)
1985 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
1986 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
1987 #define EXTI_EMR_MR6_Pos          (6U)
1988 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
1989 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
1990 #define EXTI_EMR_MR7_Pos          (7U)
1991 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
1992 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
1993 #define EXTI_EMR_MR8_Pos          (8U)
1994 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
1995 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
1996 #define EXTI_EMR_MR9_Pos          (9U)
1997 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
1998 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
1999 #define EXTI_EMR_MR10_Pos         (10U)
2000 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
2001 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
2002 #define EXTI_EMR_MR11_Pos         (11U)
2003 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
2004 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
2005 #define EXTI_EMR_MR12_Pos         (12U)
2006 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
2007 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
2008 #define EXTI_EMR_MR13_Pos         (13U)
2009 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
2010 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
2011 #define EXTI_EMR_MR14_Pos         (14U)
2012 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
2013 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
2014 #define EXTI_EMR_MR15_Pos         (15U)
2015 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
2016 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
2017 #define EXTI_EMR_MR16_Pos         (16U)
2018 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
2019 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
2020 #define EXTI_EMR_MR17_Pos         (17U)
2021 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
2022 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
2023 #define EXTI_EMR_MR18_Pos         (18U)
2024 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
2025 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
2026 #define EXTI_EMR_MR19_Pos         (19U)
2027 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
2028 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
2029 #define EXTI_EMR_MR20_Pos         (20U)
2030 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
2031 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
2032 #define EXTI_EMR_MR21_Pos         (21U)
2033 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
2034 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
2035 #define EXTI_EMR_MR22_Pos         (22U)
2036 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
2037 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
2038 #define EXTI_EMR_MR23_Pos         (23U)
2039 #define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */
2040 #define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */
2041 
2042 /* Reference Defines */
2043 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
2044 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
2045 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
2046 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
2047 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
2048 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
2049 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
2050 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
2051 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
2052 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
2053 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
2054 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
2055 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
2056 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
2057 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
2058 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
2059 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
2060 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
2061 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
2062 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
2063 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
2064 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
2065 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
2066 #define  EXTI_EMR_EM23                       EXTI_EMR_MR23
2067 
2068 /******************  Bit definition for EXTI_RTSR register  *******************/
2069 #define EXTI_RTSR_TR0_Pos         (0U)
2070 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
2071 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
2072 #define EXTI_RTSR_TR1_Pos         (1U)
2073 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
2074 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
2075 #define EXTI_RTSR_TR2_Pos         (2U)
2076 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
2077 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
2078 #define EXTI_RTSR_TR3_Pos         (3U)
2079 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
2080 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
2081 #define EXTI_RTSR_TR4_Pos         (4U)
2082 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
2083 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
2084 #define EXTI_RTSR_TR5_Pos         (5U)
2085 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
2086 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
2087 #define EXTI_RTSR_TR6_Pos         (6U)
2088 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
2089 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
2090 #define EXTI_RTSR_TR7_Pos         (7U)
2091 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
2092 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
2093 #define EXTI_RTSR_TR8_Pos         (8U)
2094 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
2095 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
2096 #define EXTI_RTSR_TR9_Pos         (9U)
2097 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
2098 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
2099 #define EXTI_RTSR_TR10_Pos        (10U)
2100 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
2101 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
2102 #define EXTI_RTSR_TR11_Pos        (11U)
2103 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
2104 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
2105 #define EXTI_RTSR_TR12_Pos        (12U)
2106 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
2107 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
2108 #define EXTI_RTSR_TR13_Pos        (13U)
2109 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
2110 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
2111 #define EXTI_RTSR_TR14_Pos        (14U)
2112 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
2113 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
2114 #define EXTI_RTSR_TR15_Pos        (15U)
2115 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
2116 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
2117 #define EXTI_RTSR_TR16_Pos        (16U)
2118 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
2119 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
2120 #define EXTI_RTSR_TR17_Pos        (17U)
2121 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
2122 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
2123 #define EXTI_RTSR_TR18_Pos        (18U)
2124 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
2125 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
2126 #define EXTI_RTSR_TR19_Pos        (19U)
2127 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
2128 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
2129 #define EXTI_RTSR_TR20_Pos        (20U)
2130 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
2131 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
2132 #define EXTI_RTSR_TR21_Pos        (21U)
2133 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
2134 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
2135 #define EXTI_RTSR_TR22_Pos        (22U)
2136 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
2137 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
2138 #define EXTI_RTSR_TR23_Pos        (23U)
2139 #define EXTI_RTSR_TR23_Msk        (0x1UL << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */
2140 #define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */
2141 
2142 /******************  Bit definition for EXTI_FTSR register  *******************/
2143 #define EXTI_FTSR_TR0_Pos         (0U)
2144 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
2145 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
2146 #define EXTI_FTSR_TR1_Pos         (1U)
2147 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
2148 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
2149 #define EXTI_FTSR_TR2_Pos         (2U)
2150 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
2151 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
2152 #define EXTI_FTSR_TR3_Pos         (3U)
2153 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
2154 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
2155 #define EXTI_FTSR_TR4_Pos         (4U)
2156 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
2157 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
2158 #define EXTI_FTSR_TR5_Pos         (5U)
2159 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
2160 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
2161 #define EXTI_FTSR_TR6_Pos         (6U)
2162 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
2163 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
2164 #define EXTI_FTSR_TR7_Pos         (7U)
2165 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
2166 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
2167 #define EXTI_FTSR_TR8_Pos         (8U)
2168 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
2169 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
2170 #define EXTI_FTSR_TR9_Pos         (9U)
2171 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
2172 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
2173 #define EXTI_FTSR_TR10_Pos        (10U)
2174 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
2175 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
2176 #define EXTI_FTSR_TR11_Pos        (11U)
2177 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
2178 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
2179 #define EXTI_FTSR_TR12_Pos        (12U)
2180 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
2181 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
2182 #define EXTI_FTSR_TR13_Pos        (13U)
2183 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
2184 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
2185 #define EXTI_FTSR_TR14_Pos        (14U)
2186 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
2187 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
2188 #define EXTI_FTSR_TR15_Pos        (15U)
2189 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
2190 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
2191 #define EXTI_FTSR_TR16_Pos        (16U)
2192 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
2193 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
2194 #define EXTI_FTSR_TR17_Pos        (17U)
2195 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
2196 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
2197 #define EXTI_FTSR_TR18_Pos        (18U)
2198 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
2199 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
2200 #define EXTI_FTSR_TR19_Pos        (19U)
2201 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
2202 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
2203 #define EXTI_FTSR_TR20_Pos        (20U)
2204 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
2205 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
2206 #define EXTI_FTSR_TR21_Pos        (21U)
2207 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
2208 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
2209 #define EXTI_FTSR_TR22_Pos        (22U)
2210 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
2211 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
2212 #define EXTI_FTSR_TR23_Pos        (23U)
2213 #define EXTI_FTSR_TR23_Msk        (0x1UL << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */
2214 #define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */
2215 
2216 /******************  Bit definition for EXTI_SWIER register  ******************/
2217 #define EXTI_SWIER_SWIER0_Pos     (0U)
2218 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
2219 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
2220 #define EXTI_SWIER_SWIER1_Pos     (1U)
2221 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
2222 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
2223 #define EXTI_SWIER_SWIER2_Pos     (2U)
2224 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
2225 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
2226 #define EXTI_SWIER_SWIER3_Pos     (3U)
2227 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
2228 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
2229 #define EXTI_SWIER_SWIER4_Pos     (4U)
2230 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
2231 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
2232 #define EXTI_SWIER_SWIER5_Pos     (5U)
2233 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
2234 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
2235 #define EXTI_SWIER_SWIER6_Pos     (6U)
2236 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
2237 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
2238 #define EXTI_SWIER_SWIER7_Pos     (7U)
2239 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
2240 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
2241 #define EXTI_SWIER_SWIER8_Pos     (8U)
2242 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
2243 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
2244 #define EXTI_SWIER_SWIER9_Pos     (9U)
2245 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
2246 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
2247 #define EXTI_SWIER_SWIER10_Pos    (10U)
2248 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
2249 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
2250 #define EXTI_SWIER_SWIER11_Pos    (11U)
2251 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
2252 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
2253 #define EXTI_SWIER_SWIER12_Pos    (12U)
2254 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
2255 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
2256 #define EXTI_SWIER_SWIER13_Pos    (13U)
2257 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
2258 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
2259 #define EXTI_SWIER_SWIER14_Pos    (14U)
2260 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
2261 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
2262 #define EXTI_SWIER_SWIER15_Pos    (15U)
2263 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
2264 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
2265 #define EXTI_SWIER_SWIER16_Pos    (16U)
2266 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
2267 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
2268 #define EXTI_SWIER_SWIER17_Pos    (17U)
2269 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
2270 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
2271 #define EXTI_SWIER_SWIER18_Pos    (18U)
2272 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
2273 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
2274 #define EXTI_SWIER_SWIER19_Pos    (19U)
2275 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
2276 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
2277 #define EXTI_SWIER_SWIER20_Pos    (20U)
2278 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
2279 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
2280 #define EXTI_SWIER_SWIER21_Pos    (21U)
2281 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
2282 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
2283 #define EXTI_SWIER_SWIER22_Pos    (22U)
2284 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
2285 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
2286 #define EXTI_SWIER_SWIER23_Pos    (23U)
2287 #define EXTI_SWIER_SWIER23_Msk    (0x1UL << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */
2288 #define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */
2289 
2290 /*******************  Bit definition for EXTI_PR register  ********************/
2291 #define EXTI_PR_PR0_Pos           (0U)
2292 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
2293 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
2294 #define EXTI_PR_PR1_Pos           (1U)
2295 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
2296 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
2297 #define EXTI_PR_PR2_Pos           (2U)
2298 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
2299 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
2300 #define EXTI_PR_PR3_Pos           (3U)
2301 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
2302 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
2303 #define EXTI_PR_PR4_Pos           (4U)
2304 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
2305 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
2306 #define EXTI_PR_PR5_Pos           (5U)
2307 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
2308 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
2309 #define EXTI_PR_PR6_Pos           (6U)
2310 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
2311 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
2312 #define EXTI_PR_PR7_Pos           (7U)
2313 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
2314 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
2315 #define EXTI_PR_PR8_Pos           (8U)
2316 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
2317 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
2318 #define EXTI_PR_PR9_Pos           (9U)
2319 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
2320 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
2321 #define EXTI_PR_PR10_Pos          (10U)
2322 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
2323 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
2324 #define EXTI_PR_PR11_Pos          (11U)
2325 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
2326 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
2327 #define EXTI_PR_PR12_Pos          (12U)
2328 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
2329 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
2330 #define EXTI_PR_PR13_Pos          (13U)
2331 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
2332 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
2333 #define EXTI_PR_PR14_Pos          (14U)
2334 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
2335 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
2336 #define EXTI_PR_PR15_Pos          (15U)
2337 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
2338 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
2339 #define EXTI_PR_PR16_Pos          (16U)
2340 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
2341 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
2342 #define EXTI_PR_PR17_Pos          (17U)
2343 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
2344 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
2345 #define EXTI_PR_PR18_Pos          (18U)
2346 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
2347 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
2348 #define EXTI_PR_PR19_Pos          (19U)
2349 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
2350 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
2351 #define EXTI_PR_PR20_Pos          (20U)
2352 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
2353 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
2354 #define EXTI_PR_PR21_Pos          (21U)
2355 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
2356 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
2357 #define EXTI_PR_PR22_Pos          (22U)
2358 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
2359 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
2360 #define EXTI_PR_PR23_Pos          (23U)
2361 #define EXTI_PR_PR23_Msk          (0x1UL << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */
2362 #define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */
2363 
2364 /******************************************************************************/
2365 /*                                                                            */
2366 /*                                    FLASH                                   */
2367 /*                                                                            */
2368 /******************************************************************************/
2369 /*******************  Bits definition for FLASH_ACR register  *****************/
2370 #define FLASH_ACR_LATENCY_Pos          (0U)
2371 #define FLASH_ACR_LATENCY_Msk          (0x7UL << FLASH_ACR_LATENCY_Pos)         /*!< 0x00000007 */
2372 #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
2373 #define FLASH_ACR_LATENCY_0WS          0x00000000U
2374 #define FLASH_ACR_LATENCY_1WS          0x00000001U
2375 #define FLASH_ACR_LATENCY_2WS          0x00000002U
2376 #define FLASH_ACR_LATENCY_3WS          0x00000003U
2377 #define FLASH_ACR_LATENCY_4WS          0x00000004U
2378 #define FLASH_ACR_LATENCY_5WS          0x00000005U
2379 #define FLASH_ACR_LATENCY_6WS          0x00000006U
2380 #define FLASH_ACR_LATENCY_7WS          0x00000007U
2381 
2382 
2383 #define FLASH_ACR_PRFTEN_Pos           (8U)
2384 #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
2385 #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
2386 #define FLASH_ACR_ICEN_Pos             (9U)
2387 #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
2388 #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
2389 #define FLASH_ACR_DCEN_Pos             (10U)
2390 #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
2391 #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
2392 #define FLASH_ACR_ICRST_Pos            (11U)
2393 #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
2394 #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
2395 #define FLASH_ACR_DCRST_Pos            (12U)
2396 #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
2397 #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
2398 #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
2399 #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
2400 #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
2401 #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
2402 #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
2403 #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
2404 
2405 /*******************  Bits definition for FLASH_SR register  ******************/
2406 #define FLASH_SR_EOP_Pos               (0U)
2407 #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
2408 #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
2409 #define FLASH_SR_SOP_Pos               (1U)
2410 #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
2411 #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
2412 #define FLASH_SR_WRPERR_Pos            (4U)
2413 #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
2414 #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
2415 #define FLASH_SR_PGAERR_Pos            (5U)
2416 #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
2417 #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
2418 #define FLASH_SR_PGPERR_Pos            (6U)
2419 #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
2420 #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
2421 #define FLASH_SR_PGSERR_Pos            (7U)
2422 #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
2423 #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
2424 #define FLASH_SR_RDERR_Pos            (8U)
2425 #define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */
2426 #define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk
2427 #define FLASH_SR_BSY_Pos               (16U)
2428 #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
2429 #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
2430 
2431 /*******************  Bits definition for FLASH_CR register  ******************/
2432 #define FLASH_CR_PG_Pos                (0U)
2433 #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
2434 #define FLASH_CR_PG                    FLASH_CR_PG_Msk
2435 #define FLASH_CR_SER_Pos               (1U)
2436 #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
2437 #define FLASH_CR_SER                   FLASH_CR_SER_Msk
2438 #define FLASH_CR_MER_Pos               (2U)
2439 #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
2440 #define FLASH_CR_MER                   FLASH_CR_MER_Msk
2441 #define FLASH_CR_SNB_Pos               (3U)
2442 #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
2443 #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
2444 #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
2445 #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
2446 #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
2447 #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
2448 #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
2449 #define FLASH_CR_PSIZE_Pos             (8U)
2450 #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
2451 #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
2452 #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
2453 #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
2454 #define FLASH_CR_STRT_Pos              (16U)
2455 #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
2456 #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
2457 #define FLASH_CR_EOPIE_Pos             (24U)
2458 #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
2459 #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
2460 #define FLASH_CR_ERRIE_Pos             (25U)
2461 #define FLASH_CR_ERRIE_Msk             (0x1UL << FLASH_CR_ERRIE_Pos)
2462 #define FLASH_CR_ERRIE                 FLASH_CR_ERRIE_Msk
2463 #define FLASH_CR_LOCK_Pos              (31U)
2464 #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
2465 #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
2466 
2467 /*******************  Bits definition for FLASH_OPTCR register  ***************/
2468 #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
2469 #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
2470 #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
2471 #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
2472 #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
2473 #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
2474 
2475 #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
2476 #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
2477 #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
2478 #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
2479 #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
2480 #define FLASH_OPTCR_WDG_SW_Pos         (5U)
2481 #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
2482 #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
2483 #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
2484 #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
2485 #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
2486 #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
2487 #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
2488 #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
2489 #define FLASH_OPTCR_RDP_Pos            (8U)
2490 #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
2491 #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
2492 #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
2493 #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
2494 #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
2495 #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
2496 #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
2497 #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
2498 #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
2499 #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
2500 #define FLASH_OPTCR_nWRP_Pos           (16U)
2501 #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
2502 #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
2503 #define FLASH_OPTCR_nWRP_0             0x00010000U
2504 #define FLASH_OPTCR_nWRP_1             0x00020000U
2505 #define FLASH_OPTCR_nWRP_2             0x00040000U
2506 #define FLASH_OPTCR_nWRP_3             0x00080000U
2507 #define FLASH_OPTCR_nWRP_4             0x00100000U
2508 #define FLASH_OPTCR_nWRP_5             0x00200000U
2509 #define FLASH_OPTCR_nWRP_6             0x00400000U
2510 #define FLASH_OPTCR_nWRP_7             0x00800000U
2511 #define FLASH_OPTCR_nWRP_8             0x01000000U
2512 #define FLASH_OPTCR_nWRP_9             0x02000000U
2513 #define FLASH_OPTCR_nWRP_10            0x04000000U
2514 #define FLASH_OPTCR_nWRP_11            0x08000000U
2515 
2516 /******************  Bits definition for FLASH_OPTCR1 register  ***************/
2517 #define FLASH_OPTCR1_nWRP_Pos          (16U)
2518 #define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
2519 #define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk
2520 #define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
2521 #define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
2522 #define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
2523 #define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
2524 #define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
2525 #define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
2526 #define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
2527 #define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
2528 #define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
2529 #define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
2530 #define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
2531 #define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
2532 
2533 /******************************************************************************/
2534 /*                                                                            */
2535 /*                            General Purpose I/O                             */
2536 /*                                                                            */
2537 /******************************************************************************/
2538 /******************  Bits definition for GPIO_MODER register  *****************/
2539 #define GPIO_MODER_MODER0_Pos            (0U)
2540 #define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
2541 #define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk
2542 #define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
2543 #define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
2544 #define GPIO_MODER_MODER1_Pos            (2U)
2545 #define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
2546 #define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk
2547 #define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
2548 #define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
2549 #define GPIO_MODER_MODER2_Pos            (4U)
2550 #define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
2551 #define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk
2552 #define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
2553 #define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
2554 #define GPIO_MODER_MODER3_Pos            (6U)
2555 #define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
2556 #define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk
2557 #define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
2558 #define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
2559 #define GPIO_MODER_MODER4_Pos            (8U)
2560 #define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
2561 #define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk
2562 #define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
2563 #define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
2564 #define GPIO_MODER_MODER5_Pos            (10U)
2565 #define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
2566 #define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk
2567 #define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
2568 #define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
2569 #define GPIO_MODER_MODER6_Pos            (12U)
2570 #define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
2571 #define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk
2572 #define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
2573 #define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
2574 #define GPIO_MODER_MODER7_Pos            (14U)
2575 #define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
2576 #define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk
2577 #define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
2578 #define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
2579 #define GPIO_MODER_MODER8_Pos            (16U)
2580 #define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
2581 #define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk
2582 #define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
2583 #define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
2584 #define GPIO_MODER_MODER9_Pos            (18U)
2585 #define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
2586 #define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk
2587 #define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
2588 #define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
2589 #define GPIO_MODER_MODER10_Pos           (20U)
2590 #define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
2591 #define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk
2592 #define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
2593 #define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
2594 #define GPIO_MODER_MODER11_Pos           (22U)
2595 #define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
2596 #define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk
2597 #define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
2598 #define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
2599 #define GPIO_MODER_MODER12_Pos           (24U)
2600 #define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
2601 #define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk
2602 #define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
2603 #define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
2604 #define GPIO_MODER_MODER13_Pos           (26U)
2605 #define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
2606 #define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk
2607 #define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
2608 #define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
2609 #define GPIO_MODER_MODER14_Pos           (28U)
2610 #define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
2611 #define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk
2612 #define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
2613 #define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
2614 #define GPIO_MODER_MODER15_Pos           (30U)
2615 #define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
2616 #define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk
2617 #define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
2618 #define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
2619 
2620 /* Legacy defines */
2621 #define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos
2622 #define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
2623 #define GPIO_MODER_MODE0                 GPIO_MODER_MODER0
2624 #define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
2625 #define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
2626 #define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos
2627 #define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
2628 #define GPIO_MODER_MODE1                 GPIO_MODER_MODER1
2629 #define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
2630 #define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
2631 #define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos
2632 #define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
2633 #define GPIO_MODER_MODE2                 GPIO_MODER_MODER2
2634 #define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
2635 #define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
2636 #define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos
2637 #define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
2638 #define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
2639 #define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
2640 #define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
2641 #define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
2642 #define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
2643 #define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
2644 #define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
2645 #define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
2646 #define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
2647 #define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
2648 #define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
2649 #define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
2650 #define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
2651 #define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
2652 #define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
2653 #define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
2654 #define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
2655 #define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
2656 #define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
2657 #define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
2658 #define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
2659 #define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
2660 #define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
2661 #define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
2662 #define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER8_Msk
2663 #define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
2664 #define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
2665 #define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
2666 #define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
2667 #define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
2668 #define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
2669 #define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
2670 #define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
2671 #define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
2672 #define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
2673 #define GPIO_MODER_MODE10                GPIO_MODER_MODER10
2674 #define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
2675 #define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
2676 #define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
2677 #define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
2678 #define GPIO_MODER_MODE11                GPIO_MODER_MODER11
2679 #define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
2680 #define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
2681 #define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
2682 #define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
2683 #define GPIO_MODER_MODE12                GPIO_MODER_MODER12
2684 #define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
2685 #define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
2686 #define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
2687 #define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
2688 #define GPIO_MODER_MODE13                GPIO_MODER_MODER13
2689 #define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
2690 #define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
2691 #define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
2692 #define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
2693 #define GPIO_MODER_MODE14                GPIO_MODER_MODER14
2694 #define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
2695 #define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
2696 #define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
2697 #define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
2698 #define GPIO_MODER_MODE15                GPIO_MODER_MODER15
2699 #define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
2700 #define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
2701 
2702 /******************  Bits definition for GPIO_OTYPER register  ****************/
2703 #define GPIO_OTYPER_OT0_Pos              (0U)
2704 #define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
2705 #define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk
2706 #define GPIO_OTYPER_OT1_Pos              (1U)
2707 #define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
2708 #define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk
2709 #define GPIO_OTYPER_OT2_Pos              (2U)
2710 #define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
2711 #define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk
2712 #define GPIO_OTYPER_OT3_Pos              (3U)
2713 #define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
2714 #define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk
2715 #define GPIO_OTYPER_OT4_Pos              (4U)
2716 #define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
2717 #define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk
2718 #define GPIO_OTYPER_OT5_Pos              (5U)
2719 #define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
2720 #define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk
2721 #define GPIO_OTYPER_OT6_Pos              (6U)
2722 #define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
2723 #define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk
2724 #define GPIO_OTYPER_OT7_Pos              (7U)
2725 #define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
2726 #define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk
2727 #define GPIO_OTYPER_OT8_Pos              (8U)
2728 #define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
2729 #define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk
2730 #define GPIO_OTYPER_OT9_Pos              (9U)
2731 #define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
2732 #define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk
2733 #define GPIO_OTYPER_OT10_Pos             (10U)
2734 #define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
2735 #define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk
2736 #define GPIO_OTYPER_OT11_Pos             (11U)
2737 #define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
2738 #define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk
2739 #define GPIO_OTYPER_OT12_Pos             (12U)
2740 #define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
2741 #define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk
2742 #define GPIO_OTYPER_OT13_Pos             (13U)
2743 #define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
2744 #define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk
2745 #define GPIO_OTYPER_OT14_Pos             (14U)
2746 #define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
2747 #define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk
2748 #define GPIO_OTYPER_OT15_Pos             (15U)
2749 #define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
2750 #define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk
2751 
2752 /* Legacy defines */
2753 #define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
2754 #define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
2755 #define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
2756 #define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
2757 #define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
2758 #define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
2759 #define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
2760 #define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
2761 #define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
2762 #define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
2763 #define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
2764 #define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
2765 #define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
2766 #define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
2767 #define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
2768 #define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
2769 
2770 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
2771 #define GPIO_OSPEEDR_OSPEED0_Pos         (0U)
2772 #define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
2773 #define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk
2774 #define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
2775 #define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
2776 #define GPIO_OSPEEDR_OSPEED1_Pos         (2U)
2777 #define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
2778 #define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk
2779 #define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
2780 #define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
2781 #define GPIO_OSPEEDR_OSPEED2_Pos         (4U)
2782 #define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
2783 #define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk
2784 #define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
2785 #define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
2786 #define GPIO_OSPEEDR_OSPEED3_Pos         (6U)
2787 #define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
2788 #define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk
2789 #define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
2790 #define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
2791 #define GPIO_OSPEEDR_OSPEED4_Pos         (8U)
2792 #define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
2793 #define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk
2794 #define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
2795 #define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
2796 #define GPIO_OSPEEDR_OSPEED5_Pos         (10U)
2797 #define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
2798 #define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk
2799 #define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
2800 #define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
2801 #define GPIO_OSPEEDR_OSPEED6_Pos         (12U)
2802 #define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
2803 #define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk
2804 #define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
2805 #define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
2806 #define GPIO_OSPEEDR_OSPEED7_Pos         (14U)
2807 #define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
2808 #define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk
2809 #define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
2810 #define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
2811 #define GPIO_OSPEEDR_OSPEED8_Pos         (16U)
2812 #define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
2813 #define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk
2814 #define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
2815 #define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
2816 #define GPIO_OSPEEDR_OSPEED9_Pos         (18U)
2817 #define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
2818 #define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk
2819 #define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
2820 #define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
2821 #define GPIO_OSPEEDR_OSPEED10_Pos        (20U)
2822 #define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
2823 #define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk
2824 #define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
2825 #define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
2826 #define GPIO_OSPEEDR_OSPEED11_Pos        (22U)
2827 #define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
2828 #define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk
2829 #define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
2830 #define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
2831 #define GPIO_OSPEEDR_OSPEED12_Pos        (24U)
2832 #define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
2833 #define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk
2834 #define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
2835 #define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
2836 #define GPIO_OSPEEDR_OSPEED13_Pos        (26U)
2837 #define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
2838 #define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk
2839 #define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
2840 #define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
2841 #define GPIO_OSPEEDR_OSPEED14_Pos        (28U)
2842 #define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
2843 #define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk
2844 #define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
2845 #define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
2846 #define GPIO_OSPEEDR_OSPEED15_Pos        (30U)
2847 #define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
2848 #define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk
2849 #define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
2850 #define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
2851 
2852 /* Legacy defines */
2853 #define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
2854 #define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
2855 #define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
2856 #define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
2857 #define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
2858 #define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
2859 #define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
2860 #define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
2861 #define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
2862 #define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
2863 #define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
2864 #define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
2865 #define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
2866 #define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
2867 #define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
2868 #define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
2869 #define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
2870 #define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
2871 #define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
2872 #define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
2873 #define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
2874 #define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
2875 #define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
2876 #define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
2877 #define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
2878 #define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
2879 #define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
2880 #define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
2881 #define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
2882 #define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
2883 #define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
2884 #define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
2885 #define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
2886 #define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
2887 #define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
2888 #define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
2889 #define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
2890 #define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
2891 #define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
2892 #define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
2893 #define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
2894 #define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
2895 #define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
2896 #define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
2897 #define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
2898 #define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
2899 #define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
2900 #define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
2901 
2902 /******************  Bits definition for GPIO_PUPDR register  *****************/
2903 #define GPIO_PUPDR_PUPD0_Pos             (0U)
2904 #define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
2905 #define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk
2906 #define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
2907 #define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
2908 #define GPIO_PUPDR_PUPD1_Pos             (2U)
2909 #define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
2910 #define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk
2911 #define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
2912 #define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
2913 #define GPIO_PUPDR_PUPD2_Pos             (4U)
2914 #define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
2915 #define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk
2916 #define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
2917 #define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
2918 #define GPIO_PUPDR_PUPD3_Pos             (6U)
2919 #define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
2920 #define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk
2921 #define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
2922 #define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
2923 #define GPIO_PUPDR_PUPD4_Pos             (8U)
2924 #define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
2925 #define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk
2926 #define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
2927 #define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
2928 #define GPIO_PUPDR_PUPD5_Pos             (10U)
2929 #define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
2930 #define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk
2931 #define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
2932 #define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
2933 #define GPIO_PUPDR_PUPD6_Pos             (12U)
2934 #define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
2935 #define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk
2936 #define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
2937 #define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
2938 #define GPIO_PUPDR_PUPD7_Pos             (14U)
2939 #define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
2940 #define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk
2941 #define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
2942 #define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
2943 #define GPIO_PUPDR_PUPD8_Pos             (16U)
2944 #define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
2945 #define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk
2946 #define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
2947 #define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
2948 #define GPIO_PUPDR_PUPD9_Pos             (18U)
2949 #define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
2950 #define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk
2951 #define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
2952 #define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
2953 #define GPIO_PUPDR_PUPD10_Pos            (20U)
2954 #define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
2955 #define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk
2956 #define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
2957 #define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
2958 #define GPIO_PUPDR_PUPD11_Pos            (22U)
2959 #define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
2960 #define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk
2961 #define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
2962 #define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
2963 #define GPIO_PUPDR_PUPD12_Pos            (24U)
2964 #define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
2965 #define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk
2966 #define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
2967 #define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
2968 #define GPIO_PUPDR_PUPD13_Pos            (26U)
2969 #define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
2970 #define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk
2971 #define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
2972 #define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
2973 #define GPIO_PUPDR_PUPD14_Pos            (28U)
2974 #define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
2975 #define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk
2976 #define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
2977 #define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
2978 #define GPIO_PUPDR_PUPD15_Pos            (30U)
2979 #define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
2980 #define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk
2981 #define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
2982 #define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
2983 
2984 /* Legacy defines */
2985 #define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
2986 #define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
2987 #define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
2988 #define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
2989 #define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
2990 #define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
2991 #define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
2992 #define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
2993 #define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
2994 #define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
2995 #define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
2996 #define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
2997 #define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
2998 #define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
2999 #define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
3000 #define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
3001 #define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
3002 #define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
3003 #define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
3004 #define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
3005 #define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
3006 #define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
3007 #define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
3008 #define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
3009 #define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
3010 #define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
3011 #define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
3012 #define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
3013 #define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
3014 #define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
3015 #define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
3016 #define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
3017 #define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
3018 #define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
3019 #define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
3020 #define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
3021 #define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
3022 #define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
3023 #define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
3024 #define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
3025 #define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
3026 #define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
3027 #define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
3028 #define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
3029 #define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
3030 #define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
3031 #define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
3032 #define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
3033 
3034 /******************  Bits definition for GPIO_IDR register  *******************/
3035 #define GPIO_IDR_ID0_Pos                 (0U)
3036 #define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
3037 #define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk
3038 #define GPIO_IDR_ID1_Pos                 (1U)
3039 #define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
3040 #define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk
3041 #define GPIO_IDR_ID2_Pos                 (2U)
3042 #define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
3043 #define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk
3044 #define GPIO_IDR_ID3_Pos                 (3U)
3045 #define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
3046 #define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk
3047 #define GPIO_IDR_ID4_Pos                 (4U)
3048 #define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
3049 #define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk
3050 #define GPIO_IDR_ID5_Pos                 (5U)
3051 #define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
3052 #define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk
3053 #define GPIO_IDR_ID6_Pos                 (6U)
3054 #define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
3055 #define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk
3056 #define GPIO_IDR_ID7_Pos                 (7U)
3057 #define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
3058 #define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk
3059 #define GPIO_IDR_ID8_Pos                 (8U)
3060 #define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
3061 #define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk
3062 #define GPIO_IDR_ID9_Pos                 (9U)
3063 #define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
3064 #define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk
3065 #define GPIO_IDR_ID10_Pos                (10U)
3066 #define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
3067 #define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk
3068 #define GPIO_IDR_ID11_Pos                (11U)
3069 #define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
3070 #define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk
3071 #define GPIO_IDR_ID12_Pos                (12U)
3072 #define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
3073 #define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk
3074 #define GPIO_IDR_ID13_Pos                (13U)
3075 #define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
3076 #define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk
3077 #define GPIO_IDR_ID14_Pos                (14U)
3078 #define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
3079 #define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk
3080 #define GPIO_IDR_ID15_Pos                (15U)
3081 #define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
3082 #define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk
3083 
3084 /* Legacy defines */
3085 #define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
3086 #define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
3087 #define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
3088 #define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
3089 #define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
3090 #define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
3091 #define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
3092 #define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
3093 #define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
3094 #define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
3095 #define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
3096 #define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
3097 #define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
3098 #define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
3099 #define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
3100 #define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
3101 
3102 /******************  Bits definition for GPIO_ODR register  *******************/
3103 #define GPIO_ODR_OD0_Pos                 (0U)
3104 #define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
3105 #define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk
3106 #define GPIO_ODR_OD1_Pos                 (1U)
3107 #define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
3108 #define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk
3109 #define GPIO_ODR_OD2_Pos                 (2U)
3110 #define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
3111 #define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk
3112 #define GPIO_ODR_OD3_Pos                 (3U)
3113 #define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
3114 #define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk
3115 #define GPIO_ODR_OD4_Pos                 (4U)
3116 #define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
3117 #define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk
3118 #define GPIO_ODR_OD5_Pos                 (5U)
3119 #define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
3120 #define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk
3121 #define GPIO_ODR_OD6_Pos                 (6U)
3122 #define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
3123 #define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk
3124 #define GPIO_ODR_OD7_Pos                 (7U)
3125 #define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
3126 #define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk
3127 #define GPIO_ODR_OD8_Pos                 (8U)
3128 #define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
3129 #define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk
3130 #define GPIO_ODR_OD9_Pos                 (9U)
3131 #define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
3132 #define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk
3133 #define GPIO_ODR_OD10_Pos                (10U)
3134 #define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
3135 #define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk
3136 #define GPIO_ODR_OD11_Pos                (11U)
3137 #define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
3138 #define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk
3139 #define GPIO_ODR_OD12_Pos                (12U)
3140 #define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
3141 #define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk
3142 #define GPIO_ODR_OD13_Pos                (13U)
3143 #define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
3144 #define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk
3145 #define GPIO_ODR_OD14_Pos                (14U)
3146 #define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
3147 #define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk
3148 #define GPIO_ODR_OD15_Pos                (15U)
3149 #define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
3150 #define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk
3151 /* Legacy defines */
3152 #define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
3153 #define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
3154 #define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
3155 #define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
3156 #define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
3157 #define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
3158 #define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
3159 #define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
3160 #define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
3161 #define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
3162 #define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
3163 #define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
3164 #define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
3165 #define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
3166 #define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
3167 #define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
3168 
3169 /******************  Bits definition for GPIO_BSRR register  ******************/
3170 #define GPIO_BSRR_BS0_Pos                (0U)
3171 #define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
3172 #define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk
3173 #define GPIO_BSRR_BS1_Pos                (1U)
3174 #define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
3175 #define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk
3176 #define GPIO_BSRR_BS2_Pos                (2U)
3177 #define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
3178 #define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk
3179 #define GPIO_BSRR_BS3_Pos                (3U)
3180 #define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
3181 #define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk
3182 #define GPIO_BSRR_BS4_Pos                (4U)
3183 #define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
3184 #define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk
3185 #define GPIO_BSRR_BS5_Pos                (5U)
3186 #define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
3187 #define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk
3188 #define GPIO_BSRR_BS6_Pos                (6U)
3189 #define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
3190 #define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk
3191 #define GPIO_BSRR_BS7_Pos                (7U)
3192 #define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
3193 #define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk
3194 #define GPIO_BSRR_BS8_Pos                (8U)
3195 #define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
3196 #define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk
3197 #define GPIO_BSRR_BS9_Pos                (9U)
3198 #define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
3199 #define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk
3200 #define GPIO_BSRR_BS10_Pos               (10U)
3201 #define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
3202 #define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk
3203 #define GPIO_BSRR_BS11_Pos               (11U)
3204 #define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
3205 #define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk
3206 #define GPIO_BSRR_BS12_Pos               (12U)
3207 #define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
3208 #define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk
3209 #define GPIO_BSRR_BS13_Pos               (13U)
3210 #define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
3211 #define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk
3212 #define GPIO_BSRR_BS14_Pos               (14U)
3213 #define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
3214 #define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk
3215 #define GPIO_BSRR_BS15_Pos               (15U)
3216 #define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
3217 #define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk
3218 #define GPIO_BSRR_BR0_Pos                (16U)
3219 #define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
3220 #define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk
3221 #define GPIO_BSRR_BR1_Pos                (17U)
3222 #define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
3223 #define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk
3224 #define GPIO_BSRR_BR2_Pos                (18U)
3225 #define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
3226 #define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk
3227 #define GPIO_BSRR_BR3_Pos                (19U)
3228 #define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
3229 #define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk
3230 #define GPIO_BSRR_BR4_Pos                (20U)
3231 #define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
3232 #define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk
3233 #define GPIO_BSRR_BR5_Pos                (21U)
3234 #define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
3235 #define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk
3236 #define GPIO_BSRR_BR6_Pos                (22U)
3237 #define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
3238 #define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk
3239 #define GPIO_BSRR_BR7_Pos                (23U)
3240 #define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
3241 #define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk
3242 #define GPIO_BSRR_BR8_Pos                (24U)
3243 #define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
3244 #define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk
3245 #define GPIO_BSRR_BR9_Pos                (25U)
3246 #define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
3247 #define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk
3248 #define GPIO_BSRR_BR10_Pos               (26U)
3249 #define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
3250 #define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk
3251 #define GPIO_BSRR_BR11_Pos               (27U)
3252 #define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
3253 #define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk
3254 #define GPIO_BSRR_BR12_Pos               (28U)
3255 #define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
3256 #define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk
3257 #define GPIO_BSRR_BR13_Pos               (29U)
3258 #define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
3259 #define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk
3260 #define GPIO_BSRR_BR14_Pos               (30U)
3261 #define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
3262 #define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk
3263 #define GPIO_BSRR_BR15_Pos               (31U)
3264 #define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
3265 #define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk
3266 
3267 /* Legacy defines */
3268 #define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
3269 #define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
3270 #define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
3271 #define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
3272 #define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
3273 #define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
3274 #define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
3275 #define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
3276 #define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
3277 #define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
3278 #define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
3279 #define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
3280 #define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
3281 #define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
3282 #define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
3283 #define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
3284 #define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
3285 #define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
3286 #define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
3287 #define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
3288 #define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
3289 #define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
3290 #define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
3291 #define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
3292 #define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
3293 #define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
3294 #define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
3295 #define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
3296 #define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
3297 #define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
3298 #define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
3299 #define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
3300 #define GPIO_BRR_BR0                     GPIO_BSRR_BR0
3301 #define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
3302 #define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
3303 #define GPIO_BRR_BR1                     GPIO_BSRR_BR1
3304 #define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
3305 #define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
3306 #define GPIO_BRR_BR2                     GPIO_BSRR_BR2
3307 #define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
3308 #define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
3309 #define GPIO_BRR_BR3                     GPIO_BSRR_BR3
3310 #define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
3311 #define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
3312 #define GPIO_BRR_BR4                     GPIO_BSRR_BR4
3313 #define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
3314 #define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
3315 #define GPIO_BRR_BR5                     GPIO_BSRR_BR5
3316 #define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
3317 #define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
3318 #define GPIO_BRR_BR6                     GPIO_BSRR_BR6
3319 #define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
3320 #define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
3321 #define GPIO_BRR_BR7                     GPIO_BSRR_BR7
3322 #define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
3323 #define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
3324 #define GPIO_BRR_BR8                     GPIO_BSRR_BR8
3325 #define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
3326 #define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
3327 #define GPIO_BRR_BR9                     GPIO_BSRR_BR9
3328 #define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
3329 #define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
3330 #define GPIO_BRR_BR10                    GPIO_BSRR_BR10
3331 #define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
3332 #define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
3333 #define GPIO_BRR_BR11                    GPIO_BSRR_BR11
3334 #define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
3335 #define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
3336 #define GPIO_BRR_BR12                    GPIO_BSRR_BR12
3337 #define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
3338 #define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
3339 #define GPIO_BRR_BR13                    GPIO_BSRR_BR13
3340 #define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
3341 #define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
3342 #define GPIO_BRR_BR14                    GPIO_BSRR_BR14
3343 #define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
3344 #define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
3345 #define GPIO_BRR_BR15                    GPIO_BSRR_BR15
3346 #define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
3347 #define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk
3348 /****************** Bit definition for GPIO_LCKR register *********************/
3349 #define GPIO_LCKR_LCK0_Pos               (0U)
3350 #define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
3351 #define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk
3352 #define GPIO_LCKR_LCK1_Pos               (1U)
3353 #define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
3354 #define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk
3355 #define GPIO_LCKR_LCK2_Pos               (2U)
3356 #define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
3357 #define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk
3358 #define GPIO_LCKR_LCK3_Pos               (3U)
3359 #define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
3360 #define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk
3361 #define GPIO_LCKR_LCK4_Pos               (4U)
3362 #define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
3363 #define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk
3364 #define GPIO_LCKR_LCK5_Pos               (5U)
3365 #define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
3366 #define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk
3367 #define GPIO_LCKR_LCK6_Pos               (6U)
3368 #define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
3369 #define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk
3370 #define GPIO_LCKR_LCK7_Pos               (7U)
3371 #define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
3372 #define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk
3373 #define GPIO_LCKR_LCK8_Pos               (8U)
3374 #define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
3375 #define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk
3376 #define GPIO_LCKR_LCK9_Pos               (9U)
3377 #define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
3378 #define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk
3379 #define GPIO_LCKR_LCK10_Pos              (10U)
3380 #define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
3381 #define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk
3382 #define GPIO_LCKR_LCK11_Pos              (11U)
3383 #define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
3384 #define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk
3385 #define GPIO_LCKR_LCK12_Pos              (12U)
3386 #define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
3387 #define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk
3388 #define GPIO_LCKR_LCK13_Pos              (13U)
3389 #define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
3390 #define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk
3391 #define GPIO_LCKR_LCK14_Pos              (14U)
3392 #define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
3393 #define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk
3394 #define GPIO_LCKR_LCK15_Pos              (15U)
3395 #define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
3396 #define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk
3397 #define GPIO_LCKR_LCKK_Pos               (16U)
3398 #define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
3399 #define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk
3400 /****************** Bit definition for GPIO_AFRL register *********************/
3401 #define GPIO_AFRL_AFSEL0_Pos             (0U)
3402 #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
3403 #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
3404 #define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
3405 #define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
3406 #define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
3407 #define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
3408 #define GPIO_AFRL_AFSEL1_Pos             (4U)
3409 #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
3410 #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
3411 #define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
3412 #define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
3413 #define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
3414 #define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
3415 #define GPIO_AFRL_AFSEL2_Pos             (8U)
3416 #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
3417 #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
3418 #define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
3419 #define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
3420 #define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
3421 #define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
3422 #define GPIO_AFRL_AFSEL3_Pos             (12U)
3423 #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
3424 #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
3425 #define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
3426 #define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
3427 #define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
3428 #define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
3429 #define GPIO_AFRL_AFSEL4_Pos             (16U)
3430 #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
3431 #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
3432 #define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
3433 #define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
3434 #define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
3435 #define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
3436 #define GPIO_AFRL_AFSEL5_Pos             (20U)
3437 #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
3438 #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
3439 #define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
3440 #define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
3441 #define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
3442 #define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
3443 #define GPIO_AFRL_AFSEL6_Pos             (24U)
3444 #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
3445 #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
3446 #define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
3447 #define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
3448 #define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
3449 #define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
3450 #define GPIO_AFRL_AFSEL7_Pos             (28U)
3451 #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
3452 #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
3453 #define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
3454 #define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
3455 #define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
3456 #define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
3457 
3458 /* Legacy defines */
3459 #define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
3460 #define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
3461 #define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
3462 #define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
3463 #define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
3464 #define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
3465 #define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
3466 #define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
3467 #define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
3468 #define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
3469 #define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
3470 #define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
3471 #define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
3472 #define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
3473 #define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
3474 #define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
3475 #define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
3476 #define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
3477 #define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
3478 #define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
3479 #define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
3480 #define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
3481 #define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
3482 #define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
3483 #define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
3484 #define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
3485 #define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
3486 #define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
3487 #define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
3488 #define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
3489 #define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
3490 #define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
3491 #define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
3492 #define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
3493 #define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
3494 #define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
3495 #define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
3496 #define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
3497 #define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
3498 #define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
3499 
3500 /****************** Bit definition for GPIO_AFRH register *********************/
3501 #define GPIO_AFRH_AFSEL8_Pos             (0U)
3502 #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
3503 #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
3504 #define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
3505 #define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
3506 #define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
3507 #define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
3508 #define GPIO_AFRH_AFSEL9_Pos             (4U)
3509 #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
3510 #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
3511 #define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
3512 #define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
3513 #define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
3514 #define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
3515 #define GPIO_AFRH_AFSEL10_Pos            (8U)
3516 #define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
3517 #define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk
3518 #define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
3519 #define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
3520 #define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
3521 #define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
3522 #define GPIO_AFRH_AFSEL11_Pos            (12U)
3523 #define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
3524 #define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk
3525 #define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
3526 #define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
3527 #define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
3528 #define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
3529 #define GPIO_AFRH_AFSEL12_Pos            (16U)
3530 #define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
3531 #define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk
3532 #define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
3533 #define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
3534 #define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
3535 #define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
3536 #define GPIO_AFRH_AFSEL13_Pos            (20U)
3537 #define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
3538 #define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk
3539 #define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
3540 #define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
3541 #define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
3542 #define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
3543 #define GPIO_AFRH_AFSEL14_Pos            (24U)
3544 #define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
3545 #define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk
3546 #define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
3547 #define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
3548 #define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
3549 #define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
3550 #define GPIO_AFRH_AFSEL15_Pos            (28U)
3551 #define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
3552 #define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk
3553 #define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
3554 #define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
3555 #define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
3556 #define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
3557 
3558 /* Legacy defines */
3559 #define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
3560 #define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
3561 #define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
3562 #define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
3563 #define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
3564 #define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
3565 #define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
3566 #define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
3567 #define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
3568 #define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
3569 #define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
3570 #define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
3571 #define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
3572 #define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
3573 #define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
3574 #define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
3575 #define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
3576 #define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
3577 #define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
3578 #define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
3579 #define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
3580 #define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
3581 #define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
3582 #define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
3583 #define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
3584 #define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
3585 #define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
3586 #define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
3587 #define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
3588 #define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
3589 #define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
3590 #define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
3591 #define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
3592 #define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
3593 #define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
3594 #define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
3595 #define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
3596 #define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
3597 #define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
3598 #define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
3599 
3600 
3601 /******************************************************************************/
3602 /*                                                                            */
3603 /*                      Inter-integrated Circuit Interface                    */
3604 /*                                                                            */
3605 /******************************************************************************/
3606 /*******************  Bit definition for I2C_CR1 register  ********************/
3607 #define I2C_CR1_PE_Pos            (0U)
3608 #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
3609 #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
3610 #define I2C_CR1_SMBUS_Pos         (1U)
3611 #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
3612 #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
3613 #define I2C_CR1_SMBTYPE_Pos       (3U)
3614 #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
3615 #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
3616 #define I2C_CR1_ENARP_Pos         (4U)
3617 #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
3618 #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
3619 #define I2C_CR1_ENPEC_Pos         (5U)
3620 #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
3621 #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
3622 #define I2C_CR1_ENGC_Pos          (6U)
3623 #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
3624 #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
3625 #define I2C_CR1_NOSTRETCH_Pos     (7U)
3626 #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
3627 #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
3628 #define I2C_CR1_START_Pos         (8U)
3629 #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
3630 #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
3631 #define I2C_CR1_STOP_Pos          (9U)
3632 #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
3633 #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
3634 #define I2C_CR1_ACK_Pos           (10U)
3635 #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
3636 #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
3637 #define I2C_CR1_POS_Pos           (11U)
3638 #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
3639 #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
3640 #define I2C_CR1_PEC_Pos           (12U)
3641 #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
3642 #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
3643 #define I2C_CR1_ALERT_Pos         (13U)
3644 #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
3645 #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
3646 #define I2C_CR1_SWRST_Pos         (15U)
3647 #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
3648 #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
3649 
3650 /*******************  Bit definition for I2C_CR2 register  ********************/
3651 #define I2C_CR2_FREQ_Pos          (0U)
3652 #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
3653 #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
3654 #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
3655 #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
3656 #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
3657 #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
3658 #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
3659 #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
3660 
3661 #define I2C_CR2_ITERREN_Pos       (8U)
3662 #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
3663 #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
3664 #define I2C_CR2_ITEVTEN_Pos       (9U)
3665 #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
3666 #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
3667 #define I2C_CR2_ITBUFEN_Pos       (10U)
3668 #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
3669 #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
3670 #define I2C_CR2_DMAEN_Pos         (11U)
3671 #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
3672 #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
3673 #define I2C_CR2_LAST_Pos          (12U)
3674 #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
3675 #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
3676 
3677 /*******************  Bit definition for I2C_OAR1 register  *******************/
3678 #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
3679 #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
3680 
3681 #define I2C_OAR1_ADD0_Pos         (0U)
3682 #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
3683 #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
3684 #define I2C_OAR1_ADD1_Pos         (1U)
3685 #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
3686 #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
3687 #define I2C_OAR1_ADD2_Pos         (2U)
3688 #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
3689 #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
3690 #define I2C_OAR1_ADD3_Pos         (3U)
3691 #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
3692 #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
3693 #define I2C_OAR1_ADD4_Pos         (4U)
3694 #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
3695 #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
3696 #define I2C_OAR1_ADD5_Pos         (5U)
3697 #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
3698 #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
3699 #define I2C_OAR1_ADD6_Pos         (6U)
3700 #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
3701 #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
3702 #define I2C_OAR1_ADD7_Pos         (7U)
3703 #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
3704 #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
3705 #define I2C_OAR1_ADD8_Pos         (8U)
3706 #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
3707 #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
3708 #define I2C_OAR1_ADD9_Pos         (9U)
3709 #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
3710 #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
3711 
3712 #define I2C_OAR1_ADDMODE_Pos      (15U)
3713 #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
3714 #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
3715 
3716 /*******************  Bit definition for I2C_OAR2 register  *******************/
3717 #define I2C_OAR2_ENDUAL_Pos       (0U)
3718 #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
3719 #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
3720 #define I2C_OAR2_ADD2_Pos         (1U)
3721 #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
3722 #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
3723 
3724 /********************  Bit definition for I2C_DR register  ********************/
3725 #define I2C_DR_DR_Pos             (0U)
3726 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
3727 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
3728 
3729 /*******************  Bit definition for I2C_SR1 register  ********************/
3730 #define I2C_SR1_SB_Pos            (0U)
3731 #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
3732 #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
3733 #define I2C_SR1_ADDR_Pos          (1U)
3734 #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
3735 #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
3736 #define I2C_SR1_BTF_Pos           (2U)
3737 #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
3738 #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
3739 #define I2C_SR1_ADD10_Pos         (3U)
3740 #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
3741 #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
3742 #define I2C_SR1_STOPF_Pos         (4U)
3743 #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
3744 #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
3745 #define I2C_SR1_RXNE_Pos          (6U)
3746 #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
3747 #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
3748 #define I2C_SR1_TXE_Pos           (7U)
3749 #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
3750 #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
3751 #define I2C_SR1_BERR_Pos          (8U)
3752 #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
3753 #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
3754 #define I2C_SR1_ARLO_Pos          (9U)
3755 #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
3756 #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
3757 #define I2C_SR1_AF_Pos            (10U)
3758 #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
3759 #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
3760 #define I2C_SR1_OVR_Pos           (11U)
3761 #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
3762 #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
3763 #define I2C_SR1_PECERR_Pos        (12U)
3764 #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
3765 #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
3766 #define I2C_SR1_TIMEOUT_Pos       (14U)
3767 #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
3768 #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
3769 #define I2C_SR1_SMBALERT_Pos      (15U)
3770 #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
3771 #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
3772 
3773 /*******************  Bit definition for I2C_SR2 register  ********************/
3774 #define I2C_SR2_MSL_Pos           (0U)
3775 #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
3776 #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
3777 #define I2C_SR2_BUSY_Pos          (1U)
3778 #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
3779 #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
3780 #define I2C_SR2_TRA_Pos           (2U)
3781 #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
3782 #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
3783 #define I2C_SR2_GENCALL_Pos       (4U)
3784 #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
3785 #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
3786 #define I2C_SR2_SMBDEFAULT_Pos    (5U)
3787 #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
3788 #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
3789 #define I2C_SR2_SMBHOST_Pos       (6U)
3790 #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
3791 #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
3792 #define I2C_SR2_DUALF_Pos         (7U)
3793 #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
3794 #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
3795 #define I2C_SR2_PEC_Pos           (8U)
3796 #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
3797 #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
3798 
3799 /*******************  Bit definition for I2C_CCR register  ********************/
3800 #define I2C_CCR_CCR_Pos           (0U)
3801 #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
3802 #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
3803 #define I2C_CCR_DUTY_Pos          (14U)
3804 #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
3805 #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
3806 #define I2C_CCR_FS_Pos            (15U)
3807 #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
3808 #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
3809 
3810 /******************  Bit definition for I2C_TRISE register  *******************/
3811 #define I2C_TRISE_TRISE_Pos       (0U)
3812 #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
3813 #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
3814 
3815 /******************  Bit definition for I2C_FLTR register  *******************/
3816 #define I2C_FLTR_DNF_Pos          (0U)
3817 #define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
3818 #define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
3819 #define I2C_FLTR_ANOFF_Pos        (4U)
3820 #define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
3821 #define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
3822 
3823 /******************************************************************************/
3824 /*                                                                            */
3825 /*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */
3826 /*                                                                            */
3827 /******************************************************************************/
3828 /*******************  Bit definition for I2C_CR1 register  *******************/
3829 #define FMPI2C_CR1_PE_Pos               (0U)
3830 #define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */
3831 #define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */
3832 #define FMPI2C_CR1_TXIE_Pos             (1U)
3833 #define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */
3834 #define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */
3835 #define FMPI2C_CR1_RXIE_Pos             (2U)
3836 #define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */
3837 #define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */
3838 #define FMPI2C_CR1_ADDRIE_Pos           (3U)
3839 #define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */
3840 #define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */
3841 #define FMPI2C_CR1_NACKIE_Pos           (4U)
3842 #define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */
3843 #define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */
3844 #define FMPI2C_CR1_STOPIE_Pos           (5U)
3845 #define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */
3846 #define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */
3847 #define FMPI2C_CR1_TCIE_Pos             (6U)
3848 #define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */
3849 #define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */
3850 #define FMPI2C_CR1_ERRIE_Pos            (7U)
3851 #define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */
3852 #define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */
3853 #define FMPI2C_CR1_DNF_Pos              (8U)
3854 #define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */
3855 #define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */
3856 #define FMPI2C_CR1_ANFOFF_Pos           (12U)
3857 #define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */
3858 #define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */
3859 #define FMPI2C_CR1_TXDMAEN_Pos          (14U)
3860 #define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */
3861 #define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */
3862 #define FMPI2C_CR1_RXDMAEN_Pos          (15U)
3863 #define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */
3864 #define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */
3865 #define FMPI2C_CR1_SBC_Pos              (16U)
3866 #define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */
3867 #define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */
3868 #define FMPI2C_CR1_NOSTRETCH_Pos        (17U)
3869 #define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */
3870 #define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */
3871 #define FMPI2C_CR1_GCEN_Pos             (19U)
3872 #define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */
3873 #define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */
3874 #define FMPI2C_CR1_SMBHEN_Pos           (20U)
3875 #define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */
3876 #define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */
3877 #define FMPI2C_CR1_SMBDEN_Pos           (21U)
3878 #define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */
3879 #define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */
3880 #define FMPI2C_CR1_ALERTEN_Pos          (22U)
3881 #define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */
3882 #define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */
3883 #define FMPI2C_CR1_PECEN_Pos            (23U)
3884 #define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */
3885 #define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */
3886 
3887 /* Legacy Defines */
3888 #define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos
3889 #define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk
3890 #define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF
3891 /******************  Bit definition for I2C_CR2 register  ********************/
3892 #define FMPI2C_CR2_SADD_Pos             (0U)
3893 #define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */
3894 #define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */
3895 #define FMPI2C_CR2_RD_WRN_Pos           (10U)
3896 #define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */
3897 #define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */
3898 #define FMPI2C_CR2_ADD10_Pos            (11U)
3899 #define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */
3900 #define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */
3901 #define FMPI2C_CR2_HEAD10R_Pos          (12U)
3902 #define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */
3903 #define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */
3904 #define FMPI2C_CR2_START_Pos            (13U)
3905 #define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */
3906 #define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */
3907 #define FMPI2C_CR2_STOP_Pos             (14U)
3908 #define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */
3909 #define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */
3910 #define FMPI2C_CR2_NACK_Pos             (15U)
3911 #define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */
3912 #define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */
3913 #define FMPI2C_CR2_NBYTES_Pos           (16U)
3914 #define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */
3915 #define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */
3916 #define FMPI2C_CR2_RELOAD_Pos           (24U)
3917 #define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */
3918 #define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */
3919 #define FMPI2C_CR2_AUTOEND_Pos          (25U)
3920 #define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */
3921 #define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */
3922 #define FMPI2C_CR2_PECBYTE_Pos          (26U)
3923 #define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */
3924 #define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */
3925 
3926 /*******************  Bit definition for I2C_OAR1 register  ******************/
3927 #define FMPI2C_OAR1_OA1_Pos             (0U)
3928 #define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */
3929 #define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */
3930 #define FMPI2C_OAR1_OA1MODE_Pos         (10U)
3931 #define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */
3932 #define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */
3933 #define FMPI2C_OAR1_OA1EN_Pos           (15U)
3934 #define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */
3935 #define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */
3936 
3937 /*******************  Bit definition for I2C_OAR2 register  ******************/
3938 #define FMPI2C_OAR2_OA2_Pos             (1U)
3939 #define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */
3940 #define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */
3941 #define FMPI2C_OAR2_OA2MSK_Pos          (8U)
3942 #define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */
3943 #define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */
3944 #define FMPI2C_OAR2_OA2EN_Pos           (15U)
3945 #define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */
3946 #define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */
3947 
3948 /*******************  Bit definition for I2C_TIMINGR register *******************/
3949 #define FMPI2C_TIMINGR_SCLL_Pos         (0U)
3950 #define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */
3951 #define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */
3952 #define FMPI2C_TIMINGR_SCLH_Pos         (8U)
3953 #define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */
3954 #define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */
3955 #define FMPI2C_TIMINGR_SDADEL_Pos       (16U)
3956 #define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */
3957 #define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */
3958 #define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)
3959 #define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */
3960 #define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */
3961 #define FMPI2C_TIMINGR_PRESC_Pos        (28U)
3962 #define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */
3963 #define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */
3964 
3965 /******************* Bit definition for I2C_TIMEOUTR register *******************/
3966 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
3967 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3968 #define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */
3969 #define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)
3970 #define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */
3971 #define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */
3972 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
3973 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3974 #define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */
3975 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
3976 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3977 #define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */
3978 #define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)
3979 #define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */
3980 #define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */
3981 
3982 /******************  Bit definition for I2C_ISR register  *********************/
3983 #define FMPI2C_ISR_TXE_Pos              (0U)
3984 #define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */
3985 #define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */
3986 #define FMPI2C_ISR_TXIS_Pos             (1U)
3987 #define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */
3988 #define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */
3989 #define FMPI2C_ISR_RXNE_Pos             (2U)
3990 #define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */
3991 #define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */
3992 #define FMPI2C_ISR_ADDR_Pos             (3U)
3993 #define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */
3994 #define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */
3995 #define FMPI2C_ISR_NACKF_Pos            (4U)
3996 #define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */
3997 #define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */
3998 #define FMPI2C_ISR_STOPF_Pos            (5U)
3999 #define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */
4000 #define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */
4001 #define FMPI2C_ISR_TC_Pos               (6U)
4002 #define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */
4003 #define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */
4004 #define FMPI2C_ISR_TCR_Pos              (7U)
4005 #define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */
4006 #define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */
4007 #define FMPI2C_ISR_BERR_Pos             (8U)
4008 #define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */
4009 #define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */
4010 #define FMPI2C_ISR_ARLO_Pos             (9U)
4011 #define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */
4012 #define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */
4013 #define FMPI2C_ISR_OVR_Pos              (10U)
4014 #define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */
4015 #define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */
4016 #define FMPI2C_ISR_PECERR_Pos           (11U)
4017 #define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */
4018 #define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */
4019 #define FMPI2C_ISR_TIMEOUT_Pos          (12U)
4020 #define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */
4021 #define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */
4022 #define FMPI2C_ISR_ALERT_Pos            (13U)
4023 #define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */
4024 #define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */
4025 #define FMPI2C_ISR_BUSY_Pos             (15U)
4026 #define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */
4027 #define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */
4028 #define FMPI2C_ISR_DIR_Pos              (16U)
4029 #define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */
4030 #define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */
4031 #define FMPI2C_ISR_ADDCODE_Pos          (17U)
4032 #define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */
4033 #define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */
4034 
4035 /******************  Bit definition for I2C_ICR register  *********************/
4036 #define FMPI2C_ICR_ADDRCF_Pos           (3U)
4037 #define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */
4038 #define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */
4039 #define FMPI2C_ICR_NACKCF_Pos           (4U)
4040 #define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */
4041 #define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */
4042 #define FMPI2C_ICR_STOPCF_Pos           (5U)
4043 #define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */
4044 #define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */
4045 #define FMPI2C_ICR_BERRCF_Pos           (8U)
4046 #define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */
4047 #define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */
4048 #define FMPI2C_ICR_ARLOCF_Pos           (9U)
4049 #define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */
4050 #define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */
4051 #define FMPI2C_ICR_OVRCF_Pos            (10U)
4052 #define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */
4053 #define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */
4054 #define FMPI2C_ICR_PECCF_Pos            (11U)
4055 #define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */
4056 #define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */
4057 #define FMPI2C_ICR_TIMOUTCF_Pos         (12U)
4058 #define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */
4059 #define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */
4060 #define FMPI2C_ICR_ALERTCF_Pos          (13U)
4061 #define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */
4062 #define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */
4063 
4064 /******************  Bit definition for I2C_PECR register  *********************/
4065 #define FMPI2C_PECR_PEC_Pos             (0U)
4066 #define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */
4067 #define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */
4068 
4069 /******************  Bit definition for I2C_RXDR register  *********************/
4070 #define FMPI2C_RXDR_RXDATA_Pos          (0U)
4071 #define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */
4072 #define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */
4073 
4074 /******************  Bit definition for I2C_TXDR register  *********************/
4075 #define FMPI2C_TXDR_TXDATA_Pos          (0U)
4076 #define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */
4077 #define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */
4078 
4079 
4080 
4081 /******************************************************************************/
4082 /*                                                                            */
4083 /*                           Independent WATCHDOG                             */
4084 /*                                                                            */
4085 /******************************************************************************/
4086 /*******************  Bit definition for IWDG_KR register  ********************/
4087 #define IWDG_KR_KEY_Pos     (0U)
4088 #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
4089 #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
4090 
4091 /*******************  Bit definition for IWDG_PR register  ********************/
4092 #define IWDG_PR_PR_Pos      (0U)
4093 #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
4094 #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
4095 #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
4096 #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
4097 #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
4098 
4099 /*******************  Bit definition for IWDG_RLR register  *******************/
4100 #define IWDG_RLR_RL_Pos     (0U)
4101 #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
4102 #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
4103 
4104 /*******************  Bit definition for IWDG_SR register  ********************/
4105 #define IWDG_SR_PVU_Pos     (0U)
4106 #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
4107 #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
4108 #define IWDG_SR_RVU_Pos     (1U)
4109 #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
4110 #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
4111 
4112 
4113 
4114 /******************************************************************************/
4115 /*                                                                            */
4116 /*                             Power Control                                  */
4117 /*                                                                            */
4118 /******************************************************************************/
4119 /********************  Bit definition for PWR_CR register  ********************/
4120 #define PWR_CR_LPDS_Pos        (0U)
4121 #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
4122 #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
4123 #define PWR_CR_PDDS_Pos        (1U)
4124 #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
4125 #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
4126 #define PWR_CR_CWUF_Pos        (2U)
4127 #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
4128 #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
4129 #define PWR_CR_CSBF_Pos        (3U)
4130 #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
4131 #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
4132 #define PWR_CR_PVDE_Pos        (4U)
4133 #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
4134 #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
4135 
4136 #define PWR_CR_PLS_Pos         (5U)
4137 #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
4138 #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
4139 #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
4140 #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
4141 #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
4142 
4143 /*!< PVD level configuration */
4144 #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
4145 #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
4146 #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
4147 #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
4148 #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
4149 #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
4150 #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
4151 #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
4152 #define PWR_CR_DBP_Pos         (8U)
4153 #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
4154 #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
4155 #define PWR_CR_FPDS_Pos        (9U)
4156 #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
4157 #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
4158 #define PWR_CR_LPLVDS_Pos      (10U)
4159 #define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
4160 #define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */
4161 #define PWR_CR_MRLVDS_Pos      (11U)
4162 #define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
4163 #define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */
4164 #define PWR_CR_ADCDC1_Pos      (13U)
4165 #define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
4166 #define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */
4167 #define PWR_CR_VOS_Pos         (14U)
4168 #define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
4169 #define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4170 #define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
4171 #define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
4172 #define PWR_CR_FMSSR_Pos       (20U)
4173 #define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */
4174 #define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */
4175 #define PWR_CR_FISSR_Pos       (21U)
4176 #define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */
4177 #define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */
4178 
4179 /* Legacy define */
4180 #define  PWR_CR_PMODE                        PWR_CR_VOS
4181 
4182 /*******************  Bit definition for PWR_CSR register  ********************/
4183 #define PWR_CSR_WUF_Pos        (0U)
4184 #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
4185 #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
4186 #define PWR_CSR_SBF_Pos        (1U)
4187 #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
4188 #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
4189 #define PWR_CSR_PVDO_Pos       (2U)
4190 #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
4191 #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
4192 #define PWR_CSR_BRR_Pos        (3U)
4193 #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
4194 #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
4195 #define PWR_CSR_EWUP3_Pos      (6U)
4196 #define PWR_CSR_EWUP3_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000040 */
4197 #define PWR_CSR_EWUP3          PWR_CSR_EWUP3_Msk                               /*!< Enable WKUP pin 3                                */
4198 #define PWR_CSR_EWUP2_Pos      (7U)
4199 #define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */
4200 #define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */
4201 #define PWR_CSR_EWUP1_Pos      (8U)
4202 #define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */
4203 #define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */
4204 #define PWR_CSR_BRE_Pos        (9U)
4205 #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
4206 #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
4207 #define PWR_CSR_VOSRDY_Pos     (14U)
4208 #define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
4209 #define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
4210 
4211 /* Legacy define */
4212 #define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
4213 
4214 /******************************************************************************/
4215 /*                                                                            */
4216 /*                         Reset and Clock Control                            */
4217 /*                                                                            */
4218 /******************************************************************************/
4219 /********************  Bit definition for RCC_CR register  ********************/
4220 #define RCC_CR_HSION_Pos                   (0U)
4221 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
4222 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
4223 #define RCC_CR_HSIRDY_Pos                  (1U)
4224 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
4225 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
4226 
4227 #define RCC_CR_HSITRIM_Pos                 (3U)
4228 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
4229 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
4230 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
4231 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
4232 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
4233 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
4234 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
4235 
4236 #define RCC_CR_HSICAL_Pos                  (8U)
4237 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
4238 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
4239 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
4240 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
4241 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
4242 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
4243 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
4244 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
4245 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
4246 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
4247 
4248 #define RCC_CR_HSEON_Pos                   (16U)
4249 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
4250 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
4251 #define RCC_CR_HSERDY_Pos                  (17U)
4252 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
4253 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
4254 #define RCC_CR_HSEBYP_Pos                  (18U)
4255 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
4256 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
4257 #define RCC_CR_CSSON_Pos                   (19U)
4258 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
4259 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
4260 #define RCC_CR_PLLON_Pos                   (24U)
4261 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
4262 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
4263 #define RCC_CR_PLLRDY_Pos                  (25U)
4264 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
4265 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
4266 
4267 /********************  Bit definition for RCC_PLLCFGR register  ***************/
4268 #define RCC_PLLCFGR_PLLM_Pos               (0U)
4269 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
4270 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
4271 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
4272 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
4273 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
4274 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
4275 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
4276 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
4277 
4278 #define RCC_PLLCFGR_PLLN_Pos               (6U)
4279 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
4280 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
4281 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
4282 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
4283 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
4284 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
4285 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
4286 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
4287 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
4288 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
4289 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
4290 
4291 #define RCC_PLLCFGR_PLLP_Pos               (16U)
4292 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
4293 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
4294 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
4295 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
4296 
4297 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
4298 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
4299 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
4300 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
4301 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
4302 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
4303 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
4304 
4305 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
4306 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
4307 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
4308 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
4309 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
4310 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
4311 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
4312 /*
4313  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4314  */
4315 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */
4316 
4317 #define RCC_PLLCFGR_PLLR_Pos               (28U)
4318 #define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */
4319 #define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk
4320 #define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */
4321 #define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */
4322 #define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */
4323 
4324 /********************  Bit definition for RCC_CFGR register  ******************/
4325 /*!< SW configuration */
4326 #define RCC_CFGR_SW_Pos                    (0U)
4327 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
4328 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
4329 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
4330 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
4331 
4332 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
4333 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
4334 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
4335 
4336 /*!< SWS configuration */
4337 #define RCC_CFGR_SWS_Pos                   (2U)
4338 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
4339 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
4340 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
4341 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
4342 
4343 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
4344 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
4345 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
4346 
4347 /*!< HPRE configuration */
4348 #define RCC_CFGR_HPRE_Pos                  (4U)
4349 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
4350 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
4351 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
4352 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
4353 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
4354 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
4355 
4356 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
4357 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
4358 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
4359 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
4360 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
4361 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
4362 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
4363 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
4364 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
4365 /*!< MCO1EN configuration */
4366 #define RCC_CFGR_MCO1EN_Pos                (8U)
4367 #define RCC_CFGR_MCO1EN_Msk                (0x1UL << RCC_CFGR_MCO1EN_Pos)       /*!< 0x00000100 */
4368 #define RCC_CFGR_MCO1EN                    RCC_CFGR_MCO1EN_Msk                 /*!< MCO1EN bit */
4369 
4370 /*!< MCO2EN configuration */
4371 #define RCC_CFGR_MCO2EN_Pos                (9U)
4372 #define RCC_CFGR_MCO2EN_Msk                (0x1UL << RCC_CFGR_MCO2EN_Pos)       /*!< 0x00000200 */
4373 #define RCC_CFGR_MCO2EN                    RCC_CFGR_MCO2EN_Msk                 /*!< MCO2EN bit */
4374 /*!< PPRE1 configuration */
4375 #define RCC_CFGR_PPRE1_Pos                 (10U)
4376 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
4377 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
4378 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
4379 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
4380 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
4381 
4382 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
4383 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
4384 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
4385 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
4386 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
4387 
4388 /*!< PPRE2 configuration */
4389 #define RCC_CFGR_PPRE2_Pos                 (13U)
4390 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
4391 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
4392 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
4393 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
4394 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
4395 
4396 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
4397 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
4398 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
4399 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
4400 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
4401 
4402 /*!< RTCPRE configuration */
4403 #define RCC_CFGR_RTCPRE_Pos                (16U)
4404 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
4405 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
4406 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
4407 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
4408 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
4409 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
4410 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
4411 
4412 /*!< MCO1 configuration */
4413 #define RCC_CFGR_MCO1_Pos                  (21U)
4414 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
4415 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
4416 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
4417 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
4418 
4419 
4420 #define RCC_CFGR_MCO1PRE_Pos               (24U)
4421 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
4422 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
4423 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
4424 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
4425 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
4426 
4427 #define RCC_CFGR_MCO2PRE_Pos               (27U)
4428 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
4429 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
4430 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
4431 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
4432 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
4433 
4434 #define RCC_CFGR_MCO2_Pos                  (30U)
4435 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
4436 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
4437 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
4438 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
4439 
4440 /********************  Bit definition for RCC_CIR register  *******************/
4441 #define RCC_CIR_LSIRDYF_Pos                (0U)
4442 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
4443 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
4444 #define RCC_CIR_LSERDYF_Pos                (1U)
4445 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
4446 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
4447 #define RCC_CIR_HSIRDYF_Pos                (2U)
4448 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
4449 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
4450 #define RCC_CIR_HSERDYF_Pos                (3U)
4451 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
4452 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
4453 #define RCC_CIR_PLLRDYF_Pos                (4U)
4454 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
4455 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
4456 
4457 #define RCC_CIR_CSSF_Pos                   (7U)
4458 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
4459 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
4460 #define RCC_CIR_LSIRDYIE_Pos               (8U)
4461 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
4462 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
4463 #define RCC_CIR_LSERDYIE_Pos               (9U)
4464 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
4465 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
4466 #define RCC_CIR_HSIRDYIE_Pos               (10U)
4467 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
4468 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
4469 #define RCC_CIR_HSERDYIE_Pos               (11U)
4470 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
4471 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
4472 #define RCC_CIR_PLLRDYIE_Pos               (12U)
4473 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
4474 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
4475 
4476 #define RCC_CIR_LSIRDYC_Pos                (16U)
4477 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
4478 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
4479 #define RCC_CIR_LSERDYC_Pos                (17U)
4480 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
4481 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
4482 #define RCC_CIR_HSIRDYC_Pos                (18U)
4483 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
4484 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
4485 #define RCC_CIR_HSERDYC_Pos                (19U)
4486 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
4487 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
4488 #define RCC_CIR_PLLRDYC_Pos                (20U)
4489 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
4490 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
4491 
4492 #define RCC_CIR_CSSC_Pos                   (23U)
4493 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
4494 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
4495 
4496 /********************  Bit definition for RCC_AHB1RSTR register  **************/
4497 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
4498 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
4499 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
4500 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
4501 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4502 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
4503 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
4504 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4505 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
4506 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
4507 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
4508 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
4509 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
4510 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
4511 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
4512 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
4513 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
4514 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
4515 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
4516 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
4517 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
4518 #define RCC_AHB1RSTR_RNGRST_Pos            (31U)
4519 #define RCC_AHB1RSTR_RNGRST_Msk            (0x1UL << RCC_AHB1RSTR_RNGRST_Pos)   /*!< 0x80000000 */
4520 #define RCC_AHB1RSTR_RNGRST                RCC_AHB1RSTR_RNGRST_Msk
4521 
4522 
4523 /********************  Bit definition for RCC_APB1RSTR register  **************/
4524 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
4525 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
4526 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
4527 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
4528 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
4529 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
4530 #define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)
4531 #define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
4532 #define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk
4533 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
4534 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
4535 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
4536 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
4537 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
4538 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
4539 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
4540 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4541 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
4542 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
4543 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
4544 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
4545 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
4546 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
4547 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
4548 #define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)
4549 #define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
4550 #define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk
4551 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
4552 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
4553 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
4554 #define RCC_APB1RSTR_DACRST_Pos            (29U)
4555 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
4556 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
4557 
4558 /********************  Bit definition for RCC_APB2RSTR register  **************/
4559 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
4560 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
4561 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
4562 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
4563 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
4564 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
4565 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
4566 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
4567 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
4568 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
4569 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
4570 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
4571 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
4572 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
4573 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
4574 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
4575 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
4576 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
4577 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
4578 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
4579 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
4580 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
4581 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
4582 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
4583 #define RCC_APB2RSTR_SPI5RST_Pos           (20U)
4584 #define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
4585 #define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk
4586 
4587 /********************  Bit definition for RCC_AHB1ENR register  ***************/
4588 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
4589 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
4590 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
4591 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
4592 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
4593 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
4594 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
4595 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
4596 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
4597 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
4598 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
4599 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
4600 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
4601 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
4602 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
4603 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
4604 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
4605 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
4606 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
4607 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
4608 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
4609 #define RCC_AHB1ENR_RNGEN_Pos              (31U)
4610 #define RCC_AHB1ENR_RNGEN_Msk              (0x1UL << RCC_AHB1ENR_RNGEN_Pos)     /*!< 0x80000000 */
4611 #define RCC_AHB1ENR_RNGEN                  RCC_AHB1ENR_RNGEN_Msk
4612 
4613 /********************  Bit definition for RCC_APB1ENR register  ***************/
4614 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
4615 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
4616 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
4617 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
4618 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
4619 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
4620 #define RCC_APB1ENR_LPTIM1EN_Pos           (9U)
4621 #define RCC_APB1ENR_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */
4622 #define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk
4623 #define RCC_APB1ENR_RTCAPBEN_Pos           (10U)
4624 #define RCC_APB1ENR_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */
4625 #define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk
4626 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
4627 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
4628 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
4629 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
4630 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
4631 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
4632 #define RCC_APB1ENR_USART2EN_Pos           (17U)
4633 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
4634 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
4635 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
4636 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
4637 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
4638 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
4639 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
4640 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
4641 #define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)
4642 #define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
4643 #define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk
4644 #define RCC_APB1ENR_PWREN_Pos              (28U)
4645 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
4646 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
4647 #define RCC_APB1ENR_DACEN_Pos              (29U)
4648 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
4649 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
4650 
4651 /********************  Bit definition for RCC_APB2ENR register  ***************/
4652 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
4653 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
4654 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
4655 #define RCC_APB2ENR_USART1EN_Pos           (4U)
4656 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
4657 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
4658 #define RCC_APB2ENR_USART6EN_Pos           (5U)
4659 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
4660 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
4661 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
4662 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
4663 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
4664 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
4665 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
4666 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
4667 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
4668 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
4669 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
4670 #define RCC_APB2ENR_EXTITEN_Pos            (15U)
4671 #define RCC_APB2ENR_EXTITEN_Msk            (0x1UL << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */
4672 #define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk
4673 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
4674 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
4675 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
4676 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
4677 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
4678 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
4679 #define RCC_APB2ENR_SPI5EN_Pos             (20U)
4680 #define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
4681 #define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk
4682 
4683 /********************  Bit definition for RCC_AHB1LPENR register  *************/
4684 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
4685 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
4686 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
4687 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
4688 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
4689 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
4690 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
4691 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
4692 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
4693 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
4694 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
4695 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
4696 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
4697 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
4698 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
4699 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
4700 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
4701 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
4702 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
4703 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
4704 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
4705 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
4706 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
4707 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
4708 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
4709 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
4710 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
4711 #define RCC_AHB1LPENR_RNGLPEN_Pos          (31U)
4712 #define RCC_AHB1LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB1LPENR_RNGLPEN_Pos) /*!< 0x80000000 */
4713 #define RCC_AHB1LPENR_RNGLPEN              RCC_AHB1LPENR_RNGLPEN_Msk
4714 
4715 /********************  Bit definition for RCC_APB1LPENR register  *************/
4716 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
4717 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
4718 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
4719 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
4720 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
4721 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
4722 #define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)
4723 #define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
4724 #define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk
4725 #define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)
4726 #define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */
4727 #define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk
4728 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
4729 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
4730 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
4731 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
4732 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
4733 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
4734 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
4735 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
4736 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
4737 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
4738 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
4739 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
4740 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
4741 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
4742 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
4743 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)
4744 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
4745 #define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk
4746 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
4747 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
4748 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
4749 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
4750 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
4751 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
4752 
4753 /********************  Bit definition for RCC_APB2LPENR register  *************/
4754 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
4755 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
4756 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
4757 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
4758 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
4759 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
4760 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
4761 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
4762 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
4763 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
4764 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
4765 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
4766 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
4767 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
4768 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
4769 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
4770 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
4771 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
4772 #define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)
4773 #define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */
4774 #define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk
4775 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
4776 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
4777 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
4778 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
4779 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
4780 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
4781 #define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)
4782 #define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
4783 #define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk
4784 
4785 /********************  Bit definition for RCC_BDCR register  ******************/
4786 #define RCC_BDCR_LSEON_Pos                 (0U)
4787 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
4788 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
4789 #define RCC_BDCR_LSERDY_Pos                (1U)
4790 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
4791 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
4792 #define RCC_BDCR_LSEBYP_Pos                (2U)
4793 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
4794 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
4795 #define RCC_BDCR_LSEMOD_Pos                (3U)
4796 #define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */
4797 #define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk
4798 
4799 #define RCC_BDCR_RTCSEL_Pos                (8U)
4800 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
4801 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
4802 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
4803 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
4804 
4805 #define RCC_BDCR_RTCEN_Pos                 (15U)
4806 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
4807 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
4808 #define RCC_BDCR_BDRST_Pos                 (16U)
4809 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
4810 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
4811 
4812 /********************  Bit definition for RCC_CSR register  *******************/
4813 #define RCC_CSR_LSION_Pos                  (0U)
4814 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
4815 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
4816 #define RCC_CSR_LSIRDY_Pos                 (1U)
4817 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
4818 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
4819 #define RCC_CSR_RMVF_Pos                   (24U)
4820 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
4821 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
4822 #define RCC_CSR_BORRSTF_Pos                (25U)
4823 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
4824 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
4825 #define RCC_CSR_PINRSTF_Pos                (26U)
4826 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
4827 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
4828 #define RCC_CSR_PORRSTF_Pos                (27U)
4829 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
4830 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
4831 #define RCC_CSR_SFTRSTF_Pos                (28U)
4832 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
4833 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
4834 #define RCC_CSR_IWDGRSTF_Pos               (29U)
4835 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
4836 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
4837 #define RCC_CSR_WWDGRSTF_Pos               (30U)
4838 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
4839 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
4840 #define RCC_CSR_LPWRRSTF_Pos               (31U)
4841 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
4842 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
4843 /* Legacy defines */
4844 #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
4845 #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
4846 
4847 /********************  Bit definition for RCC_SSCGR register  *****************/
4848 #define RCC_SSCGR_MODPER_Pos               (0U)
4849 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
4850 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
4851 #define RCC_SSCGR_INCSTEP_Pos              (13U)
4852 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
4853 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
4854 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
4855 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
4856 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
4857 #define RCC_SSCGR_SSCGEN_Pos               (31U)
4858 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
4859 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
4860 
4861 /********************  Bit definition for RCC_DCKCFGR register  ***************/
4862 
4863 #define RCC_DCKCFGR_TIMPRE_Pos             (24U)
4864 #define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
4865 #define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk
4866 #define RCC_DCKCFGR_I2SSRC_Pos             (25U)
4867 #define RCC_DCKCFGR_I2SSRC_Msk             (0x3UL << RCC_DCKCFGR_I2SSRC_Pos)    /*!< 0x06000000 */
4868 #define RCC_DCKCFGR_I2SSRC                 RCC_DCKCFGR_I2SSRC_Msk
4869 #define RCC_DCKCFGR_I2SSRC_0               (0x1UL << RCC_DCKCFGR_I2SSRC_Pos)    /*!< 0x02000000 */
4870 #define RCC_DCKCFGR_I2SSRC_1               (0x2UL << RCC_DCKCFGR_I2SSRC_Pos)    /*!< 0x04000000 */
4871 
4872 /********************  Bit definition for RCC_DCKCFGR2 register  ***************/
4873 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)
4874 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
4875 #define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk
4876 #define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
4877 #define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
4878 #define RCC_DCKCFGR2_LPTIM1SEL_Pos         (30U)
4879 #define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */
4880 #define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk
4881 #define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */
4882 #define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */
4883 
4884 
4885 /******************************************************************************/
4886 /*                                                                            */
4887 /*                                    RNG                                     */
4888 /*                                                                            */
4889 /******************************************************************************/
4890 /********************  Bits definition for RNG_CR register  *******************/
4891 #define RNG_CR_RNGEN_Pos    (2U)
4892 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
4893 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
4894 #define RNG_CR_IE_Pos       (3U)
4895 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
4896 #define RNG_CR_IE           RNG_CR_IE_Msk
4897 
4898 /********************  Bits definition for RNG_SR register  *******************/
4899 #define RNG_SR_DRDY_Pos     (0U)
4900 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
4901 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
4902 #define RNG_SR_CECS_Pos     (1U)
4903 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
4904 #define RNG_SR_CECS         RNG_SR_CECS_Msk
4905 #define RNG_SR_SECS_Pos     (2U)
4906 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
4907 #define RNG_SR_SECS         RNG_SR_SECS_Msk
4908 #define RNG_SR_CEIS_Pos     (5U)
4909 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
4910 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
4911 #define RNG_SR_SEIS_Pos     (6U)
4912 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
4913 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
4914 
4915 /******************************************************************************/
4916 /*                                                                            */
4917 /*                           Real-Time Clock (RTC)                            */
4918 /*                                                                            */
4919 /******************************************************************************/
4920 /*
4921  * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
4922  */
4923 #define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
4924 /********************  Bits definition for RTC_TR register  *******************/
4925 #define RTC_TR_PM_Pos                 (22U)
4926 #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
4927 #define RTC_TR_PM                     RTC_TR_PM_Msk
4928 #define RTC_TR_HT_Pos                 (20U)
4929 #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
4930 #define RTC_TR_HT                     RTC_TR_HT_Msk
4931 #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
4932 #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
4933 #define RTC_TR_HU_Pos                 (16U)
4934 #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
4935 #define RTC_TR_HU                     RTC_TR_HU_Msk
4936 #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
4937 #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
4938 #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
4939 #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
4940 #define RTC_TR_MNT_Pos                (12U)
4941 #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
4942 #define RTC_TR_MNT                    RTC_TR_MNT_Msk
4943 #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
4944 #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
4945 #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
4946 #define RTC_TR_MNU_Pos                (8U)
4947 #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
4948 #define RTC_TR_MNU                    RTC_TR_MNU_Msk
4949 #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
4950 #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
4951 #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
4952 #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
4953 #define RTC_TR_ST_Pos                 (4U)
4954 #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
4955 #define RTC_TR_ST                     RTC_TR_ST_Msk
4956 #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
4957 #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
4958 #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
4959 #define RTC_TR_SU_Pos                 (0U)
4960 #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
4961 #define RTC_TR_SU                     RTC_TR_SU_Msk
4962 #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
4963 #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
4964 #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
4965 #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
4966 
4967 /********************  Bits definition for RTC_DR register  *******************/
4968 #define RTC_DR_YT_Pos                 (20U)
4969 #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
4970 #define RTC_DR_YT                     RTC_DR_YT_Msk
4971 #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
4972 #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
4973 #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
4974 #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
4975 #define RTC_DR_YU_Pos                 (16U)
4976 #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
4977 #define RTC_DR_YU                     RTC_DR_YU_Msk
4978 #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
4979 #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
4980 #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
4981 #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
4982 #define RTC_DR_WDU_Pos                (13U)
4983 #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
4984 #define RTC_DR_WDU                    RTC_DR_WDU_Msk
4985 #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
4986 #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
4987 #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
4988 #define RTC_DR_MT_Pos                 (12U)
4989 #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
4990 #define RTC_DR_MT                     RTC_DR_MT_Msk
4991 #define RTC_DR_MU_Pos                 (8U)
4992 #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
4993 #define RTC_DR_MU                     RTC_DR_MU_Msk
4994 #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
4995 #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
4996 #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
4997 #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
4998 #define RTC_DR_DT_Pos                 (4U)
4999 #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
5000 #define RTC_DR_DT                     RTC_DR_DT_Msk
5001 #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
5002 #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
5003 #define RTC_DR_DU_Pos                 (0U)
5004 #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
5005 #define RTC_DR_DU                     RTC_DR_DU_Msk
5006 #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
5007 #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
5008 #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
5009 #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
5010 
5011 /********************  Bits definition for RTC_CR register  *******************/
5012 #define RTC_CR_COE_Pos                (23U)
5013 #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
5014 #define RTC_CR_COE                    RTC_CR_COE_Msk
5015 #define RTC_CR_OSEL_Pos               (21U)
5016 #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
5017 #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
5018 #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
5019 #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
5020 #define RTC_CR_POL_Pos                (20U)
5021 #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
5022 #define RTC_CR_POL                    RTC_CR_POL_Msk
5023 #define RTC_CR_COSEL_Pos              (19U)
5024 #define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
5025 #define RTC_CR_COSEL                  RTC_CR_COSEL_Msk
5026 #define RTC_CR_BKP_Pos                 (18U)
5027 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
5028 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
5029 #define RTC_CR_SUB1H_Pos              (17U)
5030 #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
5031 #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
5032 #define RTC_CR_ADD1H_Pos              (16U)
5033 #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
5034 #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
5035 #define RTC_CR_TSIE_Pos               (15U)
5036 #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
5037 #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
5038 #define RTC_CR_WUTIE_Pos              (14U)
5039 #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
5040 #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
5041 #define RTC_CR_ALRBIE_Pos             (13U)
5042 #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
5043 #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
5044 #define RTC_CR_ALRAIE_Pos             (12U)
5045 #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
5046 #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
5047 #define RTC_CR_TSE_Pos                (11U)
5048 #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
5049 #define RTC_CR_TSE                    RTC_CR_TSE_Msk
5050 #define RTC_CR_WUTE_Pos               (10U)
5051 #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
5052 #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
5053 #define RTC_CR_ALRBE_Pos              (9U)
5054 #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
5055 #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
5056 #define RTC_CR_ALRAE_Pos              (8U)
5057 #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
5058 #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
5059 #define RTC_CR_DCE_Pos                (7U)
5060 #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
5061 #define RTC_CR_DCE                    RTC_CR_DCE_Msk
5062 #define RTC_CR_FMT_Pos                (6U)
5063 #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
5064 #define RTC_CR_FMT                    RTC_CR_FMT_Msk
5065 #define RTC_CR_BYPSHAD_Pos            (5U)
5066 #define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
5067 #define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk
5068 #define RTC_CR_REFCKON_Pos            (4U)
5069 #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
5070 #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
5071 #define RTC_CR_TSEDGE_Pos             (3U)
5072 #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
5073 #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
5074 #define RTC_CR_WUCKSEL_Pos            (0U)
5075 #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
5076 #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
5077 #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
5078 #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
5079 #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
5080 
5081 /* Legacy defines */
5082 #define RTC_CR_BCK                     RTC_CR_BKP
5083 
5084 /********************  Bits definition for RTC_ISR register  ******************/
5085 #define RTC_ISR_RECALPF_Pos           (16U)
5086 #define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
5087 #define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk
5088 #define RTC_ISR_TAMP1F_Pos            (13U)
5089 #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
5090 #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
5091 #define RTC_ISR_TAMP2F_Pos            (14U)
5092 #define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
5093 #define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk
5094 #define RTC_ISR_TSOVF_Pos             (12U)
5095 #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
5096 #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
5097 #define RTC_ISR_TSF_Pos               (11U)
5098 #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
5099 #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
5100 #define RTC_ISR_WUTF_Pos              (10U)
5101 #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
5102 #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
5103 #define RTC_ISR_ALRBF_Pos             (9U)
5104 #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
5105 #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
5106 #define RTC_ISR_ALRAF_Pos             (8U)
5107 #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
5108 #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
5109 #define RTC_ISR_INIT_Pos              (7U)
5110 #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
5111 #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
5112 #define RTC_ISR_INITF_Pos             (6U)
5113 #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
5114 #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
5115 #define RTC_ISR_RSF_Pos               (5U)
5116 #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
5117 #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
5118 #define RTC_ISR_INITS_Pos             (4U)
5119 #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
5120 #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
5121 #define RTC_ISR_SHPF_Pos              (3U)
5122 #define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
5123 #define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk
5124 #define RTC_ISR_WUTWF_Pos             (2U)
5125 #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
5126 #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
5127 #define RTC_ISR_ALRBWF_Pos            (1U)
5128 #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
5129 #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
5130 #define RTC_ISR_ALRAWF_Pos            (0U)
5131 #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
5132 #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
5133 
5134 /********************  Bits definition for RTC_PRER register  *****************/
5135 #define RTC_PRER_PREDIV_A_Pos         (16U)
5136 #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
5137 #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
5138 #define RTC_PRER_PREDIV_S_Pos         (0U)
5139 #define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
5140 #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
5141 
5142 /********************  Bits definition for RTC_WUTR register  *****************/
5143 #define RTC_WUTR_WUT_Pos              (0U)
5144 #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
5145 #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
5146 
5147 /********************  Bits definition for RTC_CALIBR register  ***************/
5148 #define RTC_CALIBR_DCS_Pos            (7U)
5149 #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
5150 #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
5151 #define RTC_CALIBR_DC_Pos             (0U)
5152 #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
5153 #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
5154 
5155 /********************  Bits definition for RTC_ALRMAR register  ***************/
5156 #define RTC_ALRMAR_MSK4_Pos           (31U)
5157 #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
5158 #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
5159 #define RTC_ALRMAR_WDSEL_Pos          (30U)
5160 #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
5161 #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
5162 #define RTC_ALRMAR_DT_Pos             (28U)
5163 #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
5164 #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
5165 #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
5166 #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
5167 #define RTC_ALRMAR_DU_Pos             (24U)
5168 #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
5169 #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
5170 #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
5171 #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
5172 #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
5173 #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
5174 #define RTC_ALRMAR_MSK3_Pos           (23U)
5175 #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
5176 #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
5177 #define RTC_ALRMAR_PM_Pos             (22U)
5178 #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
5179 #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
5180 #define RTC_ALRMAR_HT_Pos             (20U)
5181 #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
5182 #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
5183 #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
5184 #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
5185 #define RTC_ALRMAR_HU_Pos             (16U)
5186 #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
5187 #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
5188 #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
5189 #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
5190 #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
5191 #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
5192 #define RTC_ALRMAR_MSK2_Pos           (15U)
5193 #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
5194 #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
5195 #define RTC_ALRMAR_MNT_Pos            (12U)
5196 #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
5197 #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
5198 #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
5199 #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
5200 #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
5201 #define RTC_ALRMAR_MNU_Pos            (8U)
5202 #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
5203 #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
5204 #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
5205 #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
5206 #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
5207 #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
5208 #define RTC_ALRMAR_MSK1_Pos           (7U)
5209 #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
5210 #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
5211 #define RTC_ALRMAR_ST_Pos             (4U)
5212 #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
5213 #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
5214 #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
5215 #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
5216 #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
5217 #define RTC_ALRMAR_SU_Pos             (0U)
5218 #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
5219 #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
5220 #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
5221 #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
5222 #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
5223 #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
5224 
5225 /********************  Bits definition for RTC_ALRMBR register  ***************/
5226 #define RTC_ALRMBR_MSK4_Pos           (31U)
5227 #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
5228 #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
5229 #define RTC_ALRMBR_WDSEL_Pos          (30U)
5230 #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
5231 #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
5232 #define RTC_ALRMBR_DT_Pos             (28U)
5233 #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
5234 #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
5235 #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
5236 #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
5237 #define RTC_ALRMBR_DU_Pos             (24U)
5238 #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
5239 #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
5240 #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
5241 #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
5242 #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
5243 #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
5244 #define RTC_ALRMBR_MSK3_Pos           (23U)
5245 #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
5246 #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
5247 #define RTC_ALRMBR_PM_Pos             (22U)
5248 #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
5249 #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
5250 #define RTC_ALRMBR_HT_Pos             (20U)
5251 #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
5252 #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
5253 #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
5254 #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
5255 #define RTC_ALRMBR_HU_Pos             (16U)
5256 #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
5257 #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
5258 #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
5259 #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
5260 #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
5261 #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
5262 #define RTC_ALRMBR_MSK2_Pos           (15U)
5263 #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
5264 #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
5265 #define RTC_ALRMBR_MNT_Pos            (12U)
5266 #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
5267 #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
5268 #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
5269 #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
5270 #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
5271 #define RTC_ALRMBR_MNU_Pos            (8U)
5272 #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
5273 #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
5274 #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
5275 #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
5276 #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
5277 #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
5278 #define RTC_ALRMBR_MSK1_Pos           (7U)
5279 #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
5280 #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
5281 #define RTC_ALRMBR_ST_Pos             (4U)
5282 #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
5283 #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
5284 #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
5285 #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
5286 #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
5287 #define RTC_ALRMBR_SU_Pos             (0U)
5288 #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
5289 #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
5290 #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
5291 #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
5292 #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
5293 #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
5294 
5295 /********************  Bits definition for RTC_WPR register  ******************/
5296 #define RTC_WPR_KEY_Pos               (0U)
5297 #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
5298 #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
5299 
5300 /********************  Bits definition for RTC_SSR register  ******************/
5301 #define RTC_SSR_SS_Pos                (0U)
5302 #define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
5303 #define RTC_SSR_SS                    RTC_SSR_SS_Msk
5304 
5305 /********************  Bits definition for RTC_SHIFTR register  ***************/
5306 #define RTC_SHIFTR_SUBFS_Pos          (0U)
5307 #define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
5308 #define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk
5309 #define RTC_SHIFTR_ADD1S_Pos          (31U)
5310 #define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
5311 #define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk
5312 
5313 /********************  Bits definition for RTC_TSTR register  *****************/
5314 #define RTC_TSTR_PM_Pos               (22U)
5315 #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
5316 #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
5317 #define RTC_TSTR_HT_Pos               (20U)
5318 #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
5319 #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
5320 #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
5321 #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
5322 #define RTC_TSTR_HU_Pos               (16U)
5323 #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
5324 #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
5325 #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
5326 #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
5327 #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
5328 #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
5329 #define RTC_TSTR_MNT_Pos              (12U)
5330 #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
5331 #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
5332 #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
5333 #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
5334 #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
5335 #define RTC_TSTR_MNU_Pos              (8U)
5336 #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
5337 #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
5338 #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
5339 #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
5340 #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
5341 #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
5342 #define RTC_TSTR_ST_Pos               (4U)
5343 #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
5344 #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
5345 #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
5346 #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
5347 #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
5348 #define RTC_TSTR_SU_Pos               (0U)
5349 #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
5350 #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
5351 #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
5352 #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
5353 #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
5354 #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
5355 
5356 /********************  Bits definition for RTC_TSDR register  *****************/
5357 #define RTC_TSDR_WDU_Pos              (13U)
5358 #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
5359 #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
5360 #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
5361 #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
5362 #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
5363 #define RTC_TSDR_MT_Pos               (12U)
5364 #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
5365 #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
5366 #define RTC_TSDR_MU_Pos               (8U)
5367 #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
5368 #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
5369 #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
5370 #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
5371 #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
5372 #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
5373 #define RTC_TSDR_DT_Pos               (4U)
5374 #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
5375 #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
5376 #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
5377 #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
5378 #define RTC_TSDR_DU_Pos               (0U)
5379 #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
5380 #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
5381 #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
5382 #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
5383 #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
5384 #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
5385 
5386 /********************  Bits definition for RTC_TSSSR register  ****************/
5387 #define RTC_TSSSR_SS_Pos              (0U)
5388 #define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
5389 #define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk
5390 
5391 /********************  Bits definition for RTC_CAL register  *****************/
5392 #define RTC_CALR_CALP_Pos             (15U)
5393 #define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
5394 #define RTC_CALR_CALP                 RTC_CALR_CALP_Msk
5395 #define RTC_CALR_CALW8_Pos            (14U)
5396 #define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
5397 #define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk
5398 #define RTC_CALR_CALW16_Pos           (13U)
5399 #define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
5400 #define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk
5401 #define RTC_CALR_CALM_Pos             (0U)
5402 #define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
5403 #define RTC_CALR_CALM                 RTC_CALR_CALM_Msk
5404 #define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
5405 #define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
5406 #define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
5407 #define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
5408 #define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
5409 #define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
5410 #define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
5411 #define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
5412 #define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
5413 
5414 /********************  Bits definition for RTC_TAFCR register  ****************/
5415 #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
5416 #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
5417 #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
5418 #define RTC_TAFCR_TSINSEL_Pos         (17U)
5419 #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
5420 #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
5421 #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
5422 #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
5423 #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
5424 #define RTC_TAFCR_TAMPPUDIS_Pos       (15U)
5425 #define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
5426 #define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk
5427 #define RTC_TAFCR_TAMPPRCH_Pos        (13U)
5428 #define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
5429 #define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk
5430 #define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
5431 #define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
5432 #define RTC_TAFCR_TAMPFLT_Pos         (11U)
5433 #define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
5434 #define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk
5435 #define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
5436 #define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
5437 #define RTC_TAFCR_TAMPFREQ_Pos        (8U)
5438 #define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
5439 #define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk
5440 #define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
5441 #define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
5442 #define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
5443 #define RTC_TAFCR_TAMPTS_Pos          (7U)
5444 #define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
5445 #define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk
5446 #define RTC_TAFCR_TAMP2TRG_Pos        (4U)
5447 #define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
5448 #define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk
5449 #define RTC_TAFCR_TAMP2E_Pos          (3U)
5450 #define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
5451 #define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk
5452 #define RTC_TAFCR_TAMPIE_Pos          (2U)
5453 #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
5454 #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
5455 #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
5456 #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
5457 #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
5458 #define RTC_TAFCR_TAMP1E_Pos          (0U)
5459 #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
5460 #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
5461 
5462 /* Legacy defines */
5463 #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
5464 
5465 /********************  Bits definition for RTC_ALRMASSR register  *************/
5466 #define RTC_ALRMASSR_MASKSS_Pos       (24U)
5467 #define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
5468 #define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk
5469 #define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
5470 #define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
5471 #define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
5472 #define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
5473 #define RTC_ALRMASSR_SS_Pos           (0U)
5474 #define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
5475 #define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk
5476 
5477 /********************  Bits definition for RTC_ALRMBSSR register  *************/
5478 #define RTC_ALRMBSSR_MASKSS_Pos       (24U)
5479 #define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
5480 #define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk
5481 #define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
5482 #define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
5483 #define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
5484 #define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
5485 #define RTC_ALRMBSSR_SS_Pos           (0U)
5486 #define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
5487 #define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk
5488 
5489 /********************  Bits definition for RTC_BKP0R register  ****************/
5490 #define RTC_BKP0R_Pos                 (0U)
5491 #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
5492 #define RTC_BKP0R                     RTC_BKP0R_Msk
5493 
5494 /********************  Bits definition for RTC_BKP1R register  ****************/
5495 #define RTC_BKP1R_Pos                 (0U)
5496 #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
5497 #define RTC_BKP1R                     RTC_BKP1R_Msk
5498 
5499 /********************  Bits definition for RTC_BKP2R register  ****************/
5500 #define RTC_BKP2R_Pos                 (0U)
5501 #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
5502 #define RTC_BKP2R                     RTC_BKP2R_Msk
5503 
5504 /********************  Bits definition for RTC_BKP3R register  ****************/
5505 #define RTC_BKP3R_Pos                 (0U)
5506 #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
5507 #define RTC_BKP3R                     RTC_BKP3R_Msk
5508 
5509 /********************  Bits definition for RTC_BKP4R register  ****************/
5510 #define RTC_BKP4R_Pos                 (0U)
5511 #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
5512 #define RTC_BKP4R                     RTC_BKP4R_Msk
5513 
5514 /********************  Bits definition for RTC_BKP5R register  ****************/
5515 #define RTC_BKP5R_Pos                 (0U)
5516 #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
5517 #define RTC_BKP5R                     RTC_BKP5R_Msk
5518 
5519 /********************  Bits definition for RTC_BKP6R register  ****************/
5520 #define RTC_BKP6R_Pos                 (0U)
5521 #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
5522 #define RTC_BKP6R                     RTC_BKP6R_Msk
5523 
5524 /********************  Bits definition for RTC_BKP7R register  ****************/
5525 #define RTC_BKP7R_Pos                 (0U)
5526 #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
5527 #define RTC_BKP7R                     RTC_BKP7R_Msk
5528 
5529 /********************  Bits definition for RTC_BKP8R register  ****************/
5530 #define RTC_BKP8R_Pos                 (0U)
5531 #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
5532 #define RTC_BKP8R                     RTC_BKP8R_Msk
5533 
5534 /********************  Bits definition for RTC_BKP9R register  ****************/
5535 #define RTC_BKP9R_Pos                 (0U)
5536 #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
5537 #define RTC_BKP9R                     RTC_BKP9R_Msk
5538 
5539 /********************  Bits definition for RTC_BKP10R register  ***************/
5540 #define RTC_BKP10R_Pos                (0U)
5541 #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
5542 #define RTC_BKP10R                    RTC_BKP10R_Msk
5543 
5544 /********************  Bits definition for RTC_BKP11R register  ***************/
5545 #define RTC_BKP11R_Pos                (0U)
5546 #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
5547 #define RTC_BKP11R                    RTC_BKP11R_Msk
5548 
5549 /********************  Bits definition for RTC_BKP12R register  ***************/
5550 #define RTC_BKP12R_Pos                (0U)
5551 #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
5552 #define RTC_BKP12R                    RTC_BKP12R_Msk
5553 
5554 /********************  Bits definition for RTC_BKP13R register  ***************/
5555 #define RTC_BKP13R_Pos                (0U)
5556 #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
5557 #define RTC_BKP13R                    RTC_BKP13R_Msk
5558 
5559 /********************  Bits definition for RTC_BKP14R register  ***************/
5560 #define RTC_BKP14R_Pos                (0U)
5561 #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
5562 #define RTC_BKP14R                    RTC_BKP14R_Msk
5563 
5564 /********************  Bits definition for RTC_BKP15R register  ***************/
5565 #define RTC_BKP15R_Pos                (0U)
5566 #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
5567 #define RTC_BKP15R                    RTC_BKP15R_Msk
5568 
5569 /********************  Bits definition for RTC_BKP16R register  ***************/
5570 #define RTC_BKP16R_Pos                (0U)
5571 #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
5572 #define RTC_BKP16R                    RTC_BKP16R_Msk
5573 
5574 /********************  Bits definition for RTC_BKP17R register  ***************/
5575 #define RTC_BKP17R_Pos                (0U)
5576 #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
5577 #define RTC_BKP17R                    RTC_BKP17R_Msk
5578 
5579 /********************  Bits definition for RTC_BKP18R register  ***************/
5580 #define RTC_BKP18R_Pos                (0U)
5581 #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
5582 #define RTC_BKP18R                    RTC_BKP18R_Msk
5583 
5584 /********************  Bits definition for RTC_BKP19R register  ***************/
5585 #define RTC_BKP19R_Pos                (0U)
5586 #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
5587 #define RTC_BKP19R                    RTC_BKP19R_Msk
5588 
5589 /******************** Number of backup registers ******************************/
5590 #define RTC_BKP_NUMBER                       0x000000014U
5591 
5592 /******************************************************************************/
5593 /*                                                                            */
5594 /*                        Serial Peripheral Interface                         */
5595 /*                                                                            */
5596 /******************************************************************************/
5597 
5598 /*******************  Bit definition for SPI_CR1 register  ********************/
5599 #define SPI_CR1_CPHA_Pos            (0U)
5600 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
5601 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
5602 #define SPI_CR1_CPOL_Pos            (1U)
5603 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
5604 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
5605 #define SPI_CR1_MSTR_Pos            (2U)
5606 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
5607 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
5608 
5609 #define SPI_CR1_BR_Pos              (3U)
5610 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
5611 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
5612 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
5613 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
5614 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
5615 
5616 #define SPI_CR1_SPE_Pos             (6U)
5617 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
5618 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
5619 #define SPI_CR1_LSBFIRST_Pos        (7U)
5620 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
5621 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
5622 #define SPI_CR1_SSI_Pos             (8U)
5623 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
5624 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
5625 #define SPI_CR1_SSM_Pos             (9U)
5626 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
5627 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
5628 #define SPI_CR1_RXONLY_Pos          (10U)
5629 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
5630 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
5631 #define SPI_CR1_DFF_Pos             (11U)
5632 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
5633 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
5634 #define SPI_CR1_CRCNEXT_Pos         (12U)
5635 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
5636 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
5637 #define SPI_CR1_CRCEN_Pos           (13U)
5638 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
5639 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
5640 #define SPI_CR1_BIDIOE_Pos          (14U)
5641 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
5642 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
5643 #define SPI_CR1_BIDIMODE_Pos        (15U)
5644 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
5645 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
5646 
5647 /*******************  Bit definition for SPI_CR2 register  ********************/
5648 #define SPI_CR2_RXDMAEN_Pos         (0U)
5649 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
5650 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
5651 #define SPI_CR2_TXDMAEN_Pos         (1U)
5652 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
5653 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
5654 #define SPI_CR2_SSOE_Pos            (2U)
5655 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
5656 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
5657 #define SPI_CR2_FRF_Pos             (4U)
5658 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
5659 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
5660 #define SPI_CR2_ERRIE_Pos           (5U)
5661 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
5662 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
5663 #define SPI_CR2_RXNEIE_Pos          (6U)
5664 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
5665 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
5666 #define SPI_CR2_TXEIE_Pos           (7U)
5667 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
5668 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
5669 
5670 /********************  Bit definition for SPI_SR register  ********************/
5671 #define SPI_SR_RXNE_Pos             (0U)
5672 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
5673 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
5674 #define SPI_SR_TXE_Pos              (1U)
5675 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
5676 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
5677 #define SPI_SR_CHSIDE_Pos           (2U)
5678 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
5679 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
5680 #define SPI_SR_UDR_Pos              (3U)
5681 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
5682 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
5683 #define SPI_SR_CRCERR_Pos           (4U)
5684 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
5685 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
5686 #define SPI_SR_MODF_Pos             (5U)
5687 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
5688 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
5689 #define SPI_SR_OVR_Pos              (6U)
5690 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
5691 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
5692 #define SPI_SR_BSY_Pos              (7U)
5693 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
5694 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
5695 #define SPI_SR_FRE_Pos              (8U)
5696 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
5697 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
5698 
5699 /********************  Bit definition for SPI_DR register  ********************/
5700 #define SPI_DR_DR_Pos               (0U)
5701 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
5702 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
5703 
5704 /*******************  Bit definition for SPI_CRCPR register  ******************/
5705 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
5706 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
5707 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
5708 
5709 /******************  Bit definition for SPI_RXCRCR register  ******************/
5710 #define SPI_RXCRCR_RXCRC_Pos        (0U)
5711 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
5712 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
5713 
5714 /******************  Bit definition for SPI_TXCRCR register  ******************/
5715 #define SPI_TXCRCR_TXCRC_Pos        (0U)
5716 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
5717 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
5718 
5719 /******************  Bit definition for SPI_I2SCFGR register  *****************/
5720 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
5721 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
5722 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
5723 
5724 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
5725 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
5726 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
5727 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
5728 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
5729 
5730 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
5731 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
5732 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
5733 
5734 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
5735 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
5736 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
5737 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
5738 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
5739 
5740 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
5741 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
5742 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
5743 
5744 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
5745 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
5746 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5747 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
5748 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
5749 
5750 #define SPI_I2SCFGR_I2SE_Pos        (10U)
5751 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
5752 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
5753 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
5754 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
5755 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
5756 
5757 /******************  Bit definition for SPI_I2SPR register  *******************/
5758 #define SPI_I2SPR_I2SDIV_Pos        (0U)
5759 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
5760 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
5761 #define SPI_I2SPR_ODD_Pos           (8U)
5762 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
5763 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
5764 #define SPI_I2SPR_MCKOE_Pos         (9U)
5765 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
5766 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
5767 
5768 /******************************************************************************/
5769 /*                                                                            */
5770 /*                                 SYSCFG                                     */
5771 /*                                                                            */
5772 /******************************************************************************/
5773 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
5774 #define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)
5775 #define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
5776 #define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
5777 #define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
5778 #define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
5779 /******************  Bit definition for SYSCFG_PMC register  ******************/
5780 #define SYSCFG_PMC_ADC1DC2_Pos               (16U)
5781 #define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
5782 #define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
5783 
5784 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
5785 #define SYSCFG_EXTICR1_EXTI0_Pos             (0U)
5786 #define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5787 #define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
5788 #define SYSCFG_EXTICR1_EXTI1_Pos             (4U)
5789 #define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5790 #define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
5791 #define SYSCFG_EXTICR1_EXTI2_Pos             (8U)
5792 #define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5793 #define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
5794 #define SYSCFG_EXTICR1_EXTI3_Pos             (12U)
5795 #define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5796 #define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
5797 /**
5798   * @brief   EXTI0 configuration
5799   */
5800 #define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
5801 #define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
5802 #define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
5803 #define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
5804 
5805 /**
5806   * @brief   EXTI1 configuration
5807   */
5808 #define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
5809 #define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
5810 #define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
5811 #define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
5812 
5813 /**
5814   * @brief   EXTI2 configuration
5815   */
5816 #define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
5817 #define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
5818 #define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
5819 #define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
5820 
5821 /**
5822   * @brief   EXTI3 configuration
5823   */
5824 #define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
5825 #define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
5826 #define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
5827 #define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
5828 
5829 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
5830 #define SYSCFG_EXTICR2_EXTI4_Pos             (0U)
5831 #define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5832 #define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
5833 #define SYSCFG_EXTICR2_EXTI5_Pos             (4U)
5834 #define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5835 #define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
5836 #define SYSCFG_EXTICR2_EXTI6_Pos             (8U)
5837 #define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5838 #define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
5839 #define SYSCFG_EXTICR2_EXTI7_Pos             (12U)
5840 #define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5841 #define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
5842 
5843 /**
5844   * @brief   EXTI4 configuration
5845   */
5846 #define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
5847 #define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
5848 #define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
5849 #define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
5850 
5851 /**
5852   * @brief   EXTI5 configuration
5853   */
5854 #define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
5855 #define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
5856 #define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
5857 #define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
5858 
5859 /**
5860   * @brief   EXTI6 configuration
5861   */
5862 #define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
5863 #define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
5864 #define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
5865 #define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
5866 
5867 /**
5868   * @brief   EXTI7 configuration
5869   */
5870 #define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
5871 #define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
5872 #define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
5873 #define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
5874 
5875 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
5876 #define SYSCFG_EXTICR3_EXTI8_Pos             (0U)
5877 #define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5878 #define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
5879 #define SYSCFG_EXTICR3_EXTI9_Pos             (4U)
5880 #define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5881 #define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
5882 #define SYSCFG_EXTICR3_EXTI10_Pos            (8U)
5883 #define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5884 #define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
5885 #define SYSCFG_EXTICR3_EXTI11_Pos            (12U)
5886 #define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5887 #define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
5888 
5889 /**
5890   * @brief   EXTI8 configuration
5891   */
5892 #define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
5893 #define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
5894 #define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
5895 #define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
5896 
5897 /**
5898   * @brief   EXTI9 configuration
5899   */
5900 #define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
5901 #define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
5902 #define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
5903 #define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
5904 
5905 /**
5906   * @brief   EXTI10 configuration
5907   */
5908 #define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
5909 #define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
5910 #define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
5911 #define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
5912 
5913 /**
5914   * @brief   EXTI11 configuration
5915   */
5916 #define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
5917 #define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
5918 #define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
5919 #define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
5920 
5921 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
5922 #define SYSCFG_EXTICR4_EXTI12_Pos            (0U)
5923 #define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5924 #define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
5925 #define SYSCFG_EXTICR4_EXTI13_Pos            (4U)
5926 #define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5927 #define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
5928 #define SYSCFG_EXTICR4_EXTI14_Pos            (8U)
5929 #define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5930 #define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
5931 #define SYSCFG_EXTICR4_EXTI15_Pos            (12U)
5932 #define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5933 #define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
5934 
5935 /**
5936   * @brief   EXTI12 configuration
5937   */
5938 #define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
5939 #define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
5940 #define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
5941 #define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
5942 
5943 /**
5944   * @brief   EXTI13 configuration
5945   */
5946 #define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
5947 #define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
5948 #define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
5949 #define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
5950 
5951 /**
5952   * @brief   EXTI14 configuration
5953   */
5954 #define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
5955 #define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
5956 #define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
5957 #define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
5958 
5959 /**
5960   * @brief   EXTI15 configuration
5961   */
5962 #define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
5963 #define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
5964 #define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
5965 #define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
5966 
5967 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
5968 #define SYSCFG_CMPCR_CMP_PD_Pos              (0U)
5969 #define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
5970 #define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
5971 #define SYSCFG_CMPCR_READY_Pos               (8U)
5972 #define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
5973 #define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
5974 /******************  Bit definition for SYSCFG_CFGR register  *****************/
5975 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)
5976 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
5977 #define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */
5978 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)
5979 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
5980 #define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */
5981 
5982 /******************  Bit definition for SYSCFG_CFGR2 register  *****************/
5983 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)
5984 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
5985 #define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!<Core Lockup lock */
5986 #define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)
5987 #define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
5988 #define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!<PVD Lock         */
5989 
5990 /******************************************************************************/
5991 /*                                                                            */
5992 /*                                    TIM                                     */
5993 /*                                                                            */
5994 /******************************************************************************/
5995 /*******************  Bit definition for TIM_CR1 register  ********************/
5996 #define TIM_CR1_CEN_Pos           (0U)
5997 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
5998 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
5999 #define TIM_CR1_UDIS_Pos          (1U)
6000 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
6001 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
6002 #define TIM_CR1_URS_Pos           (2U)
6003 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
6004 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
6005 #define TIM_CR1_OPM_Pos           (3U)
6006 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
6007 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
6008 #define TIM_CR1_DIR_Pos           (4U)
6009 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
6010 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
6011 
6012 #define TIM_CR1_CMS_Pos           (5U)
6013 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
6014 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
6015 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
6016 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
6017 
6018 #define TIM_CR1_ARPE_Pos          (7U)
6019 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
6020 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
6021 
6022 #define TIM_CR1_CKD_Pos           (8U)
6023 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
6024 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
6025 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
6026 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
6027 
6028 /*******************  Bit definition for TIM_CR2 register  ********************/
6029 #define TIM_CR2_CCPC_Pos          (0U)
6030 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
6031 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
6032 #define TIM_CR2_CCUS_Pos          (2U)
6033 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
6034 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
6035 #define TIM_CR2_CCDS_Pos          (3U)
6036 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
6037 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
6038 
6039 #define TIM_CR2_MMS_Pos           (4U)
6040 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
6041 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
6042 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
6043 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
6044 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
6045 
6046 #define TIM_CR2_TI1S_Pos          (7U)
6047 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
6048 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
6049 #define TIM_CR2_OIS1_Pos          (8U)
6050 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
6051 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
6052 #define TIM_CR2_OIS1N_Pos         (9U)
6053 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
6054 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
6055 #define TIM_CR2_OIS2_Pos          (10U)
6056 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
6057 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
6058 #define TIM_CR2_OIS2N_Pos         (11U)
6059 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
6060 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
6061 #define TIM_CR2_OIS3_Pos          (12U)
6062 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
6063 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
6064 #define TIM_CR2_OIS3N_Pos         (13U)
6065 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
6066 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
6067 #define TIM_CR2_OIS4_Pos          (14U)
6068 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
6069 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
6070 
6071 /*******************  Bit definition for TIM_SMCR register  *******************/
6072 #define TIM_SMCR_SMS_Pos          (0U)
6073 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
6074 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
6075 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
6076 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
6077 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
6078 
6079 #define TIM_SMCR_TS_Pos           (4U)
6080 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
6081 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
6082 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
6083 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
6084 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
6085 
6086 #define TIM_SMCR_MSM_Pos          (7U)
6087 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
6088 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
6089 
6090 #define TIM_SMCR_ETF_Pos          (8U)
6091 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
6092 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
6093 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
6094 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
6095 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
6096 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
6097 
6098 #define TIM_SMCR_ETPS_Pos         (12U)
6099 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
6100 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
6101 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
6102 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
6103 
6104 #define TIM_SMCR_ECE_Pos          (14U)
6105 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
6106 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
6107 #define TIM_SMCR_ETP_Pos          (15U)
6108 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
6109 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
6110 
6111 /*******************  Bit definition for TIM_DIER register  *******************/
6112 #define TIM_DIER_UIE_Pos          (0U)
6113 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
6114 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
6115 #define TIM_DIER_CC1IE_Pos        (1U)
6116 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
6117 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
6118 #define TIM_DIER_CC2IE_Pos        (2U)
6119 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
6120 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
6121 #define TIM_DIER_CC3IE_Pos        (3U)
6122 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
6123 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
6124 #define TIM_DIER_CC4IE_Pos        (4U)
6125 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
6126 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
6127 #define TIM_DIER_COMIE_Pos        (5U)
6128 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
6129 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
6130 #define TIM_DIER_TIE_Pos          (6U)
6131 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
6132 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
6133 #define TIM_DIER_BIE_Pos          (7U)
6134 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
6135 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
6136 #define TIM_DIER_UDE_Pos          (8U)
6137 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
6138 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
6139 #define TIM_DIER_CC1DE_Pos        (9U)
6140 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
6141 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
6142 #define TIM_DIER_CC2DE_Pos        (10U)
6143 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
6144 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
6145 #define TIM_DIER_CC3DE_Pos        (11U)
6146 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
6147 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
6148 #define TIM_DIER_CC4DE_Pos        (12U)
6149 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
6150 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
6151 #define TIM_DIER_COMDE_Pos        (13U)
6152 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
6153 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
6154 #define TIM_DIER_TDE_Pos          (14U)
6155 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
6156 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
6157 
6158 /********************  Bit definition for TIM_SR register  ********************/
6159 #define TIM_SR_UIF_Pos            (0U)
6160 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
6161 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
6162 #define TIM_SR_CC1IF_Pos          (1U)
6163 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
6164 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
6165 #define TIM_SR_CC2IF_Pos          (2U)
6166 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
6167 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
6168 #define TIM_SR_CC3IF_Pos          (3U)
6169 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
6170 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
6171 #define TIM_SR_CC4IF_Pos          (4U)
6172 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
6173 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
6174 #define TIM_SR_COMIF_Pos          (5U)
6175 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
6176 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
6177 #define TIM_SR_TIF_Pos            (6U)
6178 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
6179 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
6180 #define TIM_SR_BIF_Pos            (7U)
6181 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
6182 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
6183 #define TIM_SR_CC1OF_Pos          (9U)
6184 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
6185 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
6186 #define TIM_SR_CC2OF_Pos          (10U)
6187 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
6188 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
6189 #define TIM_SR_CC3OF_Pos          (11U)
6190 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
6191 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
6192 #define TIM_SR_CC4OF_Pos          (12U)
6193 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
6194 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
6195 
6196 /*******************  Bit definition for TIM_EGR register  ********************/
6197 #define TIM_EGR_UG_Pos            (0U)
6198 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
6199 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
6200 #define TIM_EGR_CC1G_Pos          (1U)
6201 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
6202 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
6203 #define TIM_EGR_CC2G_Pos          (2U)
6204 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
6205 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
6206 #define TIM_EGR_CC3G_Pos          (3U)
6207 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
6208 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
6209 #define TIM_EGR_CC4G_Pos          (4U)
6210 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
6211 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
6212 #define TIM_EGR_COMG_Pos          (5U)
6213 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
6214 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
6215 #define TIM_EGR_TG_Pos            (6U)
6216 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
6217 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
6218 #define TIM_EGR_BG_Pos            (7U)
6219 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
6220 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
6221 
6222 /******************  Bit definition for TIM_CCMR1 register  *******************/
6223 #define TIM_CCMR1_CC1S_Pos        (0U)
6224 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
6225 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6226 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
6227 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
6228 
6229 #define TIM_CCMR1_OC1FE_Pos       (2U)
6230 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
6231 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
6232 #define TIM_CCMR1_OC1PE_Pos       (3U)
6233 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
6234 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
6235 
6236 #define TIM_CCMR1_OC1M_Pos        (4U)
6237 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
6238 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
6239 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
6240 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
6241 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
6242 
6243 #define TIM_CCMR1_OC1CE_Pos       (7U)
6244 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
6245 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
6246 
6247 #define TIM_CCMR1_CC2S_Pos        (8U)
6248 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
6249 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6250 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
6251 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
6252 
6253 #define TIM_CCMR1_OC2FE_Pos       (10U)
6254 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
6255 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
6256 #define TIM_CCMR1_OC2PE_Pos       (11U)
6257 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
6258 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
6259 
6260 #define TIM_CCMR1_OC2M_Pos        (12U)
6261 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
6262 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
6263 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
6264 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
6265 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
6266 
6267 #define TIM_CCMR1_OC2CE_Pos       (15U)
6268 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
6269 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
6270 
6271 /*----------------------------------------------------------------------------*/
6272 
6273 #define TIM_CCMR1_IC1PSC_Pos      (2U)
6274 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
6275 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6276 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
6277 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
6278 
6279 #define TIM_CCMR1_IC1F_Pos        (4U)
6280 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
6281 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
6282 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
6283 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
6284 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
6285 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
6286 
6287 #define TIM_CCMR1_IC2PSC_Pos      (10U)
6288 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
6289 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
6290 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
6291 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
6292 
6293 #define TIM_CCMR1_IC2F_Pos        (12U)
6294 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
6295 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
6296 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
6297 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
6298 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
6299 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
6300 
6301 /******************  Bit definition for TIM_CCMR2 register  *******************/
6302 #define TIM_CCMR2_CC3S_Pos        (0U)
6303 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
6304 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
6305 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
6306 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
6307 
6308 #define TIM_CCMR2_OC3FE_Pos       (2U)
6309 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
6310 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
6311 #define TIM_CCMR2_OC3PE_Pos       (3U)
6312 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
6313 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
6314 
6315 #define TIM_CCMR2_OC3M_Pos        (4U)
6316 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
6317 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6318 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
6319 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
6320 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
6321 
6322 #define TIM_CCMR2_OC3CE_Pos       (7U)
6323 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
6324 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
6325 
6326 #define TIM_CCMR2_CC4S_Pos        (8U)
6327 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
6328 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6329 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
6330 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
6331 
6332 #define TIM_CCMR2_OC4FE_Pos       (10U)
6333 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
6334 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
6335 #define TIM_CCMR2_OC4PE_Pos       (11U)
6336 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
6337 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
6338 
6339 #define TIM_CCMR2_OC4M_Pos        (12U)
6340 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
6341 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6342 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
6343 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
6344 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
6345 
6346 #define TIM_CCMR2_OC4CE_Pos       (15U)
6347 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
6348 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
6349 
6350 /*----------------------------------------------------------------------------*/
6351 
6352 #define TIM_CCMR2_IC3PSC_Pos      (2U)
6353 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
6354 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6355 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
6356 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
6357 
6358 #define TIM_CCMR2_IC3F_Pos        (4U)
6359 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
6360 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6361 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
6362 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
6363 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
6364 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
6365 
6366 #define TIM_CCMR2_IC4PSC_Pos      (10U)
6367 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
6368 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6369 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
6370 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
6371 
6372 #define TIM_CCMR2_IC4F_Pos        (12U)
6373 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
6374 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6375 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
6376 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
6377 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
6378 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
6379 
6380 /*******************  Bit definition for TIM_CCER register  *******************/
6381 #define TIM_CCER_CC1E_Pos         (0U)
6382 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
6383 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
6384 #define TIM_CCER_CC1P_Pos         (1U)
6385 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
6386 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
6387 #define TIM_CCER_CC1NE_Pos        (2U)
6388 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
6389 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
6390 #define TIM_CCER_CC1NP_Pos        (3U)
6391 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
6392 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
6393 #define TIM_CCER_CC2E_Pos         (4U)
6394 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
6395 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
6396 #define TIM_CCER_CC2P_Pos         (5U)
6397 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
6398 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
6399 #define TIM_CCER_CC2NE_Pos        (6U)
6400 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
6401 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
6402 #define TIM_CCER_CC2NP_Pos        (7U)
6403 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
6404 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
6405 #define TIM_CCER_CC3E_Pos         (8U)
6406 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
6407 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
6408 #define TIM_CCER_CC3P_Pos         (9U)
6409 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
6410 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
6411 #define TIM_CCER_CC3NE_Pos        (10U)
6412 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
6413 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
6414 #define TIM_CCER_CC3NP_Pos        (11U)
6415 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
6416 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
6417 #define TIM_CCER_CC4E_Pos         (12U)
6418 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
6419 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
6420 #define TIM_CCER_CC4P_Pos         (13U)
6421 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
6422 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
6423 #define TIM_CCER_CC4NP_Pos        (15U)
6424 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
6425 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
6426 
6427 /*******************  Bit definition for TIM_CNT register  ********************/
6428 #define TIM_CNT_CNT_Pos           (0U)
6429 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
6430 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
6431 
6432 /*******************  Bit definition for TIM_PSC register  ********************/
6433 #define TIM_PSC_PSC_Pos           (0U)
6434 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
6435 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
6436 
6437 /*******************  Bit definition for TIM_ARR register  ********************/
6438 #define TIM_ARR_ARR_Pos           (0U)
6439 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
6440 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
6441 
6442 /*******************  Bit definition for TIM_RCR register  ********************/
6443 #define TIM_RCR_REP_Pos           (0U)
6444 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
6445 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
6446 
6447 /*******************  Bit definition for TIM_CCR1 register  *******************/
6448 #define TIM_CCR1_CCR1_Pos         (0U)
6449 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
6450 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
6451 
6452 /*******************  Bit definition for TIM_CCR2 register  *******************/
6453 #define TIM_CCR2_CCR2_Pos         (0U)
6454 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
6455 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
6456 
6457 /*******************  Bit definition for TIM_CCR3 register  *******************/
6458 #define TIM_CCR3_CCR3_Pos         (0U)
6459 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
6460 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
6461 
6462 /*******************  Bit definition for TIM_CCR4 register  *******************/
6463 #define TIM_CCR4_CCR4_Pos         (0U)
6464 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
6465 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
6466 
6467 /*******************  Bit definition for TIM_BDTR register  *******************/
6468 #define TIM_BDTR_DTG_Pos          (0U)
6469 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
6470 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6471 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
6472 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
6473 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
6474 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
6475 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
6476 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
6477 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
6478 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
6479 
6480 #define TIM_BDTR_LOCK_Pos         (8U)
6481 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
6482 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
6483 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
6484 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
6485 
6486 #define TIM_BDTR_OSSI_Pos         (10U)
6487 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
6488 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
6489 #define TIM_BDTR_OSSR_Pos         (11U)
6490 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
6491 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
6492 #define TIM_BDTR_BKE_Pos          (12U)
6493 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
6494 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
6495 #define TIM_BDTR_BKP_Pos          (13U)
6496 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
6497 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
6498 #define TIM_BDTR_AOE_Pos          (14U)
6499 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
6500 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
6501 #define TIM_BDTR_MOE_Pos          (15U)
6502 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
6503 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
6504 
6505 /*******************  Bit definition for TIM_DCR register  ********************/
6506 #define TIM_DCR_DBA_Pos           (0U)
6507 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
6508 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
6509 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
6510 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
6511 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
6512 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
6513 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
6514 
6515 #define TIM_DCR_DBL_Pos           (8U)
6516 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
6517 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
6518 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
6519 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
6520 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
6521 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
6522 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
6523 
6524 /*******************  Bit definition for TIM_DMAR register  *******************/
6525 #define TIM_DMAR_DMAB_Pos         (0U)
6526 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
6527 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
6528 
6529 /*******************  Bit definition for TIM_OR register  *********************/
6530 #define TIM_OR_TI1_RMP_Pos        (0U)
6531 #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
6532 #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
6533 #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
6534 #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
6535 
6536 #define TIM_OR_TI4_RMP_Pos        (6U)
6537 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
6538 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
6539 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
6540 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
6541 
6542 /******************************************************************************/
6543 /*                                                                            */
6544 /*                         Low Power Timer (LPTIM)                            */
6545 /*                                                                            */
6546 /******************************************************************************/
6547 /******************  Bit definition for LPTIM_ISR register  *******************/
6548 #define LPTIM_ISR_CMPM_Pos            (0U)
6549 #define LPTIM_ISR_CMPM_Msk            (0x1UL << LPTIM_ISR_CMPM_Pos)             /*!< 0x00000001 */
6550 #define LPTIM_ISR_CMPM                LPTIM_ISR_CMPM_Msk                       /*!< Compare match                       */
6551 #define LPTIM_ISR_ARRM_Pos            (1U)
6552 #define LPTIM_ISR_ARRM_Msk            (0x1UL << LPTIM_ISR_ARRM_Pos)             /*!< 0x00000002 */
6553 #define LPTIM_ISR_ARRM                LPTIM_ISR_ARRM_Msk                       /*!< Autoreload match                    */
6554 #define LPTIM_ISR_EXTTRIG_Pos         (2U)
6555 #define LPTIM_ISR_EXTTRIG_Msk         (0x1UL << LPTIM_ISR_EXTTRIG_Pos)          /*!< 0x00000004 */
6556 #define LPTIM_ISR_EXTTRIG             LPTIM_ISR_EXTTRIG_Msk                    /*!< External trigger edge event         */
6557 #define LPTIM_ISR_CMPOK_Pos           (3U)
6558 #define LPTIM_ISR_CMPOK_Msk           (0x1UL << LPTIM_ISR_CMPOK_Pos)            /*!< 0x00000008 */
6559 #define LPTIM_ISR_CMPOK               LPTIM_ISR_CMPOK_Msk                      /*!< Compare register update OK          */
6560 #define LPTIM_ISR_ARROK_Pos           (4U)
6561 #define LPTIM_ISR_ARROK_Msk           (0x1UL << LPTIM_ISR_ARROK_Pos)            /*!< 0x00000010 */
6562 #define LPTIM_ISR_ARROK               LPTIM_ISR_ARROK_Msk                      /*!< Autoreload register update OK       */
6563 #define LPTIM_ISR_UP_Pos              (5U)
6564 #define LPTIM_ISR_UP_Msk              (0x1UL << LPTIM_ISR_UP_Pos)               /*!< 0x00000020 */
6565 #define LPTIM_ISR_UP                  LPTIM_ISR_UP_Msk                         /*!< Counter direction change down to up */
6566 #define LPTIM_ISR_DOWN_Pos            (6U)
6567 #define LPTIM_ISR_DOWN_Msk            (0x1UL << LPTIM_ISR_DOWN_Pos)             /*!< 0x00000040 */
6568 #define LPTIM_ISR_DOWN                LPTIM_ISR_DOWN_Msk                       /*!< Counter direction change up to down */
6569 
6570 /******************  Bit definition for LPTIM_ICR register  *******************/
6571 #define LPTIM_ICR_CMPMCF_Pos          (0U)
6572 #define LPTIM_ICR_CMPMCF_Msk          (0x1UL << LPTIM_ICR_CMPMCF_Pos)           /*!< 0x00000001 */
6573 #define LPTIM_ICR_CMPMCF              LPTIM_ICR_CMPMCF_Msk                     /*!< Compare match Clear Flag                       */
6574 #define LPTIM_ICR_ARRMCF_Pos          (1U)
6575 #define LPTIM_ICR_ARRMCF_Msk          (0x1UL << LPTIM_ICR_ARRMCF_Pos)           /*!< 0x00000002 */
6576 #define LPTIM_ICR_ARRMCF              LPTIM_ICR_ARRMCF_Msk                     /*!< Autoreload match Clear Flag                    */
6577 #define LPTIM_ICR_EXTTRIGCF_Pos       (2U)
6578 #define LPTIM_ICR_EXTTRIGCF_Msk       (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)        /*!< 0x00000004 */
6579 #define LPTIM_ICR_EXTTRIGCF           LPTIM_ICR_EXTTRIGCF_Msk                  /*!< External trigger edge event Clear Flag         */
6580 #define LPTIM_ICR_CMPOKCF_Pos         (3U)
6581 #define LPTIM_ICR_CMPOKCF_Msk         (0x1UL << LPTIM_ICR_CMPOKCF_Pos)          /*!< 0x00000008 */
6582 #define LPTIM_ICR_CMPOKCF             LPTIM_ICR_CMPOKCF_Msk                    /*!< Compare register update OK Clear Flag          */
6583 #define LPTIM_ICR_ARROKCF_Pos         (4U)
6584 #define LPTIM_ICR_ARROKCF_Msk         (0x1UL << LPTIM_ICR_ARROKCF_Pos)          /*!< 0x00000010 */
6585 #define LPTIM_ICR_ARROKCF             LPTIM_ICR_ARROKCF_Msk                    /*!< Autoreload register update OK Clear Flag       */
6586 #define LPTIM_ICR_UPCF_Pos            (5U)
6587 #define LPTIM_ICR_UPCF_Msk            (0x1UL << LPTIM_ICR_UPCF_Pos)             /*!< 0x00000020 */
6588 #define LPTIM_ICR_UPCF                LPTIM_ICR_UPCF_Msk                       /*!< Counter direction change down to up Clear Flag */
6589 #define LPTIM_ICR_DOWNCF_Pos          (6U)
6590 #define LPTIM_ICR_DOWNCF_Msk          (0x1UL << LPTIM_ICR_DOWNCF_Pos)           /*!< 0x00000040 */
6591 #define LPTIM_ICR_DOWNCF              LPTIM_ICR_DOWNCF_Msk                     /*!< Counter direction change up to down Clear Flag */
6592 
6593 /******************  Bit definition for LPTIM_IER register ********************/
6594 #define LPTIM_IER_CMPMIE_Pos          (0U)
6595 #define LPTIM_IER_CMPMIE_Msk          (0x1UL << LPTIM_IER_CMPMIE_Pos)           /*!< 0x00000001 */
6596 #define LPTIM_IER_CMPMIE              LPTIM_IER_CMPMIE_Msk                     /*!< Compare match Interrupt Enable                       */
6597 #define LPTIM_IER_ARRMIE_Pos          (1U)
6598 #define LPTIM_IER_ARRMIE_Msk          (0x1UL << LPTIM_IER_ARRMIE_Pos)           /*!< 0x00000002 */
6599 #define LPTIM_IER_ARRMIE              LPTIM_IER_ARRMIE_Msk                     /*!< Autoreload match Interrupt Enable                    */
6600 #define LPTIM_IER_EXTTRIGIE_Pos       (2U)
6601 #define LPTIM_IER_EXTTRIGIE_Msk       (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)        /*!< 0x00000004 */
6602 #define LPTIM_IER_EXTTRIGIE           LPTIM_IER_EXTTRIGIE_Msk                  /*!< External trigger edge event Interrupt Enable         */
6603 #define LPTIM_IER_CMPOKIE_Pos         (3U)
6604 #define LPTIM_IER_CMPOKIE_Msk         (0x1UL << LPTIM_IER_CMPOKIE_Pos)          /*!< 0x00000008 */
6605 #define LPTIM_IER_CMPOKIE             LPTIM_IER_CMPOKIE_Msk                    /*!< Compare register update OK Interrupt Enable          */
6606 #define LPTIM_IER_ARROKIE_Pos         (4U)
6607 #define LPTIM_IER_ARROKIE_Msk         (0x1UL << LPTIM_IER_ARROKIE_Pos)          /*!< 0x00000010 */
6608 #define LPTIM_IER_ARROKIE             LPTIM_IER_ARROKIE_Msk                    /*!< Autoreload register update OK Interrupt Enable       */
6609 #define LPTIM_IER_UPIE_Pos            (5U)
6610 #define LPTIM_IER_UPIE_Msk            (0x1UL << LPTIM_IER_UPIE_Pos)             /*!< 0x00000020 */
6611 #define LPTIM_IER_UPIE                LPTIM_IER_UPIE_Msk                       /*!< Counter direction change down to up Interrupt Enable */
6612 #define LPTIM_IER_DOWNIE_Pos          (6U)
6613 #define LPTIM_IER_DOWNIE_Msk          (0x1UL << LPTIM_IER_DOWNIE_Pos)           /*!< 0x00000040 */
6614 #define LPTIM_IER_DOWNIE              LPTIM_IER_DOWNIE_Msk                     /*!< Counter direction change up to down Interrupt Enable */
6615 
6616 /******************  Bit definition for LPTIM_CFGR register *******************/
6617 #define LPTIM_CFGR_CKSEL_Pos          (0U)
6618 #define LPTIM_CFGR_CKSEL_Msk          (0x1UL << LPTIM_CFGR_CKSEL_Pos)           /*!< 0x00000001 */
6619 #define LPTIM_CFGR_CKSEL              LPTIM_CFGR_CKSEL_Msk                     /*!< Clock selector */
6620 
6621 #define LPTIM_CFGR_CKPOL_Pos          (1U)
6622 #define LPTIM_CFGR_CKPOL_Msk          (0x3UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000006 */
6623 #define LPTIM_CFGR_CKPOL              LPTIM_CFGR_CKPOL_Msk                     /*!< CKPOL[1:0] bits (Clock polarity) */
6624 #define LPTIM_CFGR_CKPOL_0            (0x1UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000002 */
6625 #define LPTIM_CFGR_CKPOL_1            (0x2UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000004 */
6626 
6627 #define LPTIM_CFGR_CKFLT_Pos          (3U)
6628 #define LPTIM_CFGR_CKFLT_Msk          (0x3UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000018 */
6629 #define LPTIM_CFGR_CKFLT              LPTIM_CFGR_CKFLT_Msk                     /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
6630 #define LPTIM_CFGR_CKFLT_0            (0x1UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000008 */
6631 #define LPTIM_CFGR_CKFLT_1            (0x2UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000010 */
6632 
6633 #define LPTIM_CFGR_TRGFLT_Pos         (6U)
6634 #define LPTIM_CFGR_TRGFLT_Msk         (0x3UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x000000C0 */
6635 #define LPTIM_CFGR_TRGFLT             LPTIM_CFGR_TRGFLT_Msk                    /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
6636 #define LPTIM_CFGR_TRGFLT_0           (0x1UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000040 */
6637 #define LPTIM_CFGR_TRGFLT_1           (0x2UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000080 */
6638 
6639 #define LPTIM_CFGR_PRESC_Pos          (9U)
6640 #define LPTIM_CFGR_PRESC_Msk          (0x7UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000E00 */
6641 #define LPTIM_CFGR_PRESC              LPTIM_CFGR_PRESC_Msk                     /*!< PRESC[2:0] bits (Clock prescaler) */
6642 #define LPTIM_CFGR_PRESC_0            (0x1UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000200 */
6643 #define LPTIM_CFGR_PRESC_1            (0x2UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000400 */
6644 #define LPTIM_CFGR_PRESC_2            (0x4UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000800 */
6645 
6646 #define LPTIM_CFGR_TRIGSEL_Pos        (13U)
6647 #define LPTIM_CFGR_TRIGSEL_Msk        (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x0000E000 */
6648 #define LPTIM_CFGR_TRIGSEL            LPTIM_CFGR_TRIGSEL_Msk                   /*!< TRIGSEL[2:0]] bits (Trigger selector) */
6649 #define LPTIM_CFGR_TRIGSEL_0          (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00002000 */
6650 #define LPTIM_CFGR_TRIGSEL_1          (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00004000 */
6651 #define LPTIM_CFGR_TRIGSEL_2          (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00008000 */
6652 
6653 #define LPTIM_CFGR_TRIGEN_Pos         (17U)
6654 #define LPTIM_CFGR_TRIGEN_Msk         (0x3UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00060000 */
6655 #define LPTIM_CFGR_TRIGEN             LPTIM_CFGR_TRIGEN_Msk                    /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
6656 #define LPTIM_CFGR_TRIGEN_0           (0x1UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00020000 */
6657 #define LPTIM_CFGR_TRIGEN_1           (0x2UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00040000 */
6658 
6659 #define LPTIM_CFGR_TIMOUT_Pos         (19U)
6660 #define LPTIM_CFGR_TIMOUT_Msk         (0x1UL << LPTIM_CFGR_TIMOUT_Pos)          /*!< 0x00080000 */
6661 #define LPTIM_CFGR_TIMOUT             LPTIM_CFGR_TIMOUT_Msk                    /*!< Timout enable           */
6662 #define LPTIM_CFGR_WAVE_Pos           (20U)
6663 #define LPTIM_CFGR_WAVE_Msk           (0x1UL << LPTIM_CFGR_WAVE_Pos)            /*!< 0x00100000 */
6664 #define LPTIM_CFGR_WAVE               LPTIM_CFGR_WAVE_Msk                      /*!< Waveform shape          */
6665 #define LPTIM_CFGR_WAVPOL_Pos         (21U)
6666 #define LPTIM_CFGR_WAVPOL_Msk         (0x1UL << LPTIM_CFGR_WAVPOL_Pos)          /*!< 0x00200000 */
6667 #define LPTIM_CFGR_WAVPOL             LPTIM_CFGR_WAVPOL_Msk                    /*!< Waveform shape polarity */
6668 #define LPTIM_CFGR_PRELOAD_Pos        (22U)
6669 #define LPTIM_CFGR_PRELOAD_Msk        (0x1UL << LPTIM_CFGR_PRELOAD_Pos)         /*!< 0x00400000 */
6670 #define LPTIM_CFGR_PRELOAD            LPTIM_CFGR_PRELOAD_Msk                   /*!< Reg update mode         */
6671 #define LPTIM_CFGR_COUNTMODE_Pos      (23U)
6672 #define LPTIM_CFGR_COUNTMODE_Msk      (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)       /*!< 0x00800000 */
6673 #define LPTIM_CFGR_COUNTMODE          LPTIM_CFGR_COUNTMODE_Msk                 /*!< Counter mode enable     */
6674 #define LPTIM_CFGR_ENC_Pos            (24U)
6675 #define LPTIM_CFGR_ENC_Msk            (0x1UL << LPTIM_CFGR_ENC_Pos)             /*!< 0x01000000 */
6676 #define LPTIM_CFGR_ENC                LPTIM_CFGR_ENC_Msk                       /*!< Encoder mode enable     */
6677 
6678 /******************  Bit definition for LPTIM_CR register  ********************/
6679 #define LPTIM_CR_ENABLE_Pos           (0U)
6680 #define LPTIM_CR_ENABLE_Msk           (0x1UL << LPTIM_CR_ENABLE_Pos)            /*!< 0x00000001 */
6681 #define LPTIM_CR_ENABLE               LPTIM_CR_ENABLE_Msk                      /*!< LPTIMer enable                 */
6682 #define LPTIM_CR_SNGSTRT_Pos          (1U)
6683 #define LPTIM_CR_SNGSTRT_Msk          (0x1UL << LPTIM_CR_SNGSTRT_Pos)           /*!< 0x00000002 */
6684 #define LPTIM_CR_SNGSTRT              LPTIM_CR_SNGSTRT_Msk                     /*!< Timer start in single mode     */
6685 #define LPTIM_CR_CNTSTRT_Pos          (2U)
6686 #define LPTIM_CR_CNTSTRT_Msk          (0x1UL << LPTIM_CR_CNTSTRT_Pos)           /*!< 0x00000004 */
6687 #define LPTIM_CR_CNTSTRT              LPTIM_CR_CNTSTRT_Msk                     /*!< Timer start in continuous mode */
6688 
6689 /******************  Bit definition for LPTIM_CMP register  *******************/
6690 #define LPTIM_CMP_CMP_Pos             (0U)
6691 #define LPTIM_CMP_CMP_Msk             (0xFFFFUL << LPTIM_CMP_CMP_Pos)           /*!< 0x0000FFFF */
6692 #define LPTIM_CMP_CMP                 LPTIM_CMP_CMP_Msk                        /*!< Compare register     */
6693 
6694 /******************  Bit definition for LPTIM_ARR register  *******************/
6695 #define LPTIM_ARR_ARR_Pos             (0U)
6696 #define LPTIM_ARR_ARR_Msk             (0xFFFFUL << LPTIM_ARR_ARR_Pos)           /*!< 0x0000FFFF */
6697 #define LPTIM_ARR_ARR                 LPTIM_ARR_ARR_Msk                        /*!< Auto reload register */
6698 
6699 /******************  Bit definition for LPTIM_CNT register  *******************/
6700 #define LPTIM_CNT_CNT_Pos             (0U)
6701 #define LPTIM_CNT_CNT_Msk             (0xFFFFUL << LPTIM_CNT_CNT_Pos)           /*!< 0x0000FFFF */
6702 #define LPTIM_CNT_CNT                 LPTIM_CNT_CNT_Msk                        /*!< Counter register     */
6703 
6704 /******************  Bit definition for LPTIM_OR register  *******************/
6705 #define LPTIM_OR_LPT_IN1_RMP_Pos      (0U)
6706 #define LPTIM_OR_LPT_IN1_RMP_Msk      (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000003 */
6707 #define LPTIM_OR_LPT_IN1_RMP          LPTIM_OR_LPT_IN1_RMP_Msk                 /*!< LPTIMER[1:0] bits (Remap selection) */
6708 #define LPTIM_OR_LPT_IN1_RMP_0        (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000001 */
6709 #define LPTIM_OR_LPT_IN1_RMP_1        (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000002 */
6710 
6711 /* Legacy Defines */
6712 #define  LPTIM_OR_OR                           LPTIM_OR_LPT_IN1_RMP
6713 #define  LPTIM_OR_OR_0                         LPTIM_OR_LPT_IN1_RMP_0
6714 #define  LPTIM_OR_OR_1                         LPTIM_OR_LPT_IN1_RMP_1
6715 
6716 
6717 /******************************************************************************/
6718 /*                                                                            */
6719 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
6720 /*                                                                            */
6721 /******************************************************************************/
6722 /*******************  Bit definition for USART_SR register  *******************/
6723 #define USART_SR_PE_Pos               (0U)
6724 #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
6725 #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
6726 #define USART_SR_FE_Pos               (1U)
6727 #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
6728 #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
6729 #define USART_SR_NE_Pos               (2U)
6730 #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
6731 #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
6732 #define USART_SR_ORE_Pos              (3U)
6733 #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
6734 #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
6735 #define USART_SR_IDLE_Pos             (4U)
6736 #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
6737 #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
6738 #define USART_SR_RXNE_Pos             (5U)
6739 #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
6740 #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
6741 #define USART_SR_TC_Pos               (6U)
6742 #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
6743 #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
6744 #define USART_SR_TXE_Pos              (7U)
6745 #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
6746 #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
6747 #define USART_SR_LBD_Pos              (8U)
6748 #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
6749 #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
6750 #define USART_SR_CTS_Pos              (9U)
6751 #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
6752 #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
6753 
6754 /*******************  Bit definition for USART_DR register  *******************/
6755 #define USART_DR_DR_Pos               (0U)
6756 #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
6757 #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
6758 
6759 /******************  Bit definition for USART_BRR register  *******************/
6760 #define USART_BRR_DIV_Fraction_Pos    (0U)
6761 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
6762 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
6763 #define USART_BRR_DIV_Mantissa_Pos    (4U)
6764 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
6765 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
6766 
6767 /******************  Bit definition for USART_CR1 register  *******************/
6768 #define USART_CR1_SBK_Pos             (0U)
6769 #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
6770 #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
6771 #define USART_CR1_RWU_Pos             (1U)
6772 #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
6773 #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
6774 #define USART_CR1_RE_Pos              (2U)
6775 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
6776 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
6777 #define USART_CR1_TE_Pos              (3U)
6778 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
6779 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
6780 #define USART_CR1_IDLEIE_Pos          (4U)
6781 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
6782 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
6783 #define USART_CR1_RXNEIE_Pos          (5U)
6784 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
6785 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
6786 #define USART_CR1_TCIE_Pos            (6U)
6787 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
6788 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
6789 #define USART_CR1_TXEIE_Pos           (7U)
6790 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
6791 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
6792 #define USART_CR1_PEIE_Pos            (8U)
6793 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
6794 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
6795 #define USART_CR1_PS_Pos              (9U)
6796 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
6797 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
6798 #define USART_CR1_PCE_Pos             (10U)
6799 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
6800 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
6801 #define USART_CR1_WAKE_Pos            (11U)
6802 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
6803 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
6804 #define USART_CR1_M_Pos               (12U)
6805 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
6806 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
6807 #define USART_CR1_UE_Pos              (13U)
6808 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
6809 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
6810 #define USART_CR1_OVER8_Pos           (15U)
6811 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
6812 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
6813 
6814 /******************  Bit definition for USART_CR2 register  *******************/
6815 #define USART_CR2_ADD_Pos             (0U)
6816 #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
6817 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
6818 #define USART_CR2_LBDL_Pos            (5U)
6819 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
6820 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
6821 #define USART_CR2_LBDIE_Pos           (6U)
6822 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
6823 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
6824 #define USART_CR2_LBCL_Pos            (8U)
6825 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
6826 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
6827 #define USART_CR2_CPHA_Pos            (9U)
6828 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
6829 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
6830 #define USART_CR2_CPOL_Pos            (10U)
6831 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
6832 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
6833 #define USART_CR2_CLKEN_Pos           (11U)
6834 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
6835 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
6836 
6837 #define USART_CR2_STOP_Pos            (12U)
6838 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
6839 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
6840 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
6841 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
6842 
6843 #define USART_CR2_LINEN_Pos           (14U)
6844 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
6845 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
6846 
6847 /******************  Bit definition for USART_CR3 register  *******************/
6848 #define USART_CR3_EIE_Pos             (0U)
6849 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
6850 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
6851 #define USART_CR3_IREN_Pos            (1U)
6852 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
6853 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
6854 #define USART_CR3_IRLP_Pos            (2U)
6855 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
6856 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
6857 #define USART_CR3_HDSEL_Pos           (3U)
6858 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
6859 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
6860 #define USART_CR3_NACK_Pos            (4U)
6861 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
6862 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
6863 #define USART_CR3_SCEN_Pos            (5U)
6864 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
6865 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
6866 #define USART_CR3_DMAR_Pos            (6U)
6867 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
6868 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
6869 #define USART_CR3_DMAT_Pos            (7U)
6870 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
6871 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
6872 #define USART_CR3_RTSE_Pos            (8U)
6873 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
6874 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
6875 #define USART_CR3_CTSE_Pos            (9U)
6876 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
6877 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
6878 #define USART_CR3_CTSIE_Pos           (10U)
6879 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
6880 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
6881 #define USART_CR3_ONEBIT_Pos          (11U)
6882 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
6883 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
6884 
6885 /******************  Bit definition for USART_GTPR register  ******************/
6886 #define USART_GTPR_PSC_Pos            (0U)
6887 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
6888 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
6889 #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
6890 #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
6891 #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
6892 #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
6893 #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
6894 #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
6895 #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
6896 #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
6897 
6898 #define USART_GTPR_GT_Pos             (8U)
6899 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
6900 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
6901 
6902 /******************************************************************************/
6903 /*                                                                            */
6904 /*                            Window WATCHDOG                                 */
6905 /*                                                                            */
6906 /******************************************************************************/
6907 /*******************  Bit definition for WWDG_CR register  ********************/
6908 #define WWDG_CR_T_Pos           (0U)
6909 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
6910 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6911 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
6912 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
6913 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
6914 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
6915 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
6916 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
6917 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
6918 /* Legacy defines */
6919 #define  WWDG_CR_T0                          WWDG_CR_T_0
6920 #define  WWDG_CR_T1                          WWDG_CR_T_1
6921 #define  WWDG_CR_T2                          WWDG_CR_T_2
6922 #define  WWDG_CR_T3                          WWDG_CR_T_3
6923 #define  WWDG_CR_T4                          WWDG_CR_T_4
6924 #define  WWDG_CR_T5                          WWDG_CR_T_5
6925 #define  WWDG_CR_T6                          WWDG_CR_T_6
6926 
6927 #define WWDG_CR_WDGA_Pos        (7U)
6928 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
6929 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
6930 
6931 /*******************  Bit definition for WWDG_CFR register  *******************/
6932 #define WWDG_CFR_W_Pos          (0U)
6933 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
6934 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
6935 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
6936 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
6937 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
6938 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
6939 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
6940 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
6941 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
6942 /* Legacy defines */
6943 #define  WWDG_CFR_W0                         WWDG_CFR_W_0
6944 #define  WWDG_CFR_W1                         WWDG_CFR_W_1
6945 #define  WWDG_CFR_W2                         WWDG_CFR_W_2
6946 #define  WWDG_CFR_W3                         WWDG_CFR_W_3
6947 #define  WWDG_CFR_W4                         WWDG_CFR_W_4
6948 #define  WWDG_CFR_W5                         WWDG_CFR_W_5
6949 #define  WWDG_CFR_W6                         WWDG_CFR_W_6
6950 
6951 #define WWDG_CFR_WDGTB_Pos      (7U)
6952 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
6953 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
6954 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
6955 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
6956 /* Legacy defines */
6957 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
6958 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
6959 
6960 #define WWDG_CFR_EWI_Pos        (9U)
6961 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
6962 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
6963 
6964 /*******************  Bit definition for WWDG_SR register  ********************/
6965 #define WWDG_SR_EWIF_Pos        (0U)
6966 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
6967 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
6968 
6969 
6970 /******************************************************************************/
6971 /*                                                                            */
6972 /*                                DBG                                         */
6973 /*                                                                            */
6974 /******************************************************************************/
6975 /********************  Bit definition for DBGMCU_IDCODE register  *************/
6976 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
6977 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
6978 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
6979 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
6980 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
6981 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
6982 
6983 /********************  Bit definition for DBGMCU_CR register  *****************/
6984 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
6985 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
6986 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
6987 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
6988 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
6989 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
6990 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
6991 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
6992 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
6993 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
6994 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
6995 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
6996 
6997 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
6998 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
6999 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
7000 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
7001 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
7002 
7003 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
7004 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
7005 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
7006 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
7007 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
7008 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
7009 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
7010 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
7011 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
7012 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
7013 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
7014 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
7015 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
7016 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
7017 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
7018 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
7019 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
7020 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
7021 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
7022 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
7023 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
7024 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
7025 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)
7026 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
7027 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
7028 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
7029 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
7030 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
7031 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
7032 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
7033 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
7034 
7035 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
7036 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
7037 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
7038 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
7039 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
7040 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
7041 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
7042 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
7043 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
7044 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
7045 /**
7046   * @}
7047   */
7048 
7049 /**
7050   * @}
7051   */
7052 
7053 /** @addtogroup Exported_macros
7054   * @{
7055   */
7056 
7057 /******************************* ADC Instances ********************************/
7058 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7059 
7060 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7061 /******************************* CRC Instances ********************************/
7062 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7063 
7064 /******************************* DAC Instances ********************************/
7065 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
7066 
7067 
7068 /******************************** DMA Instances *******************************/
7069 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
7070                                               ((INSTANCE) == DMA1_Stream1) || \
7071                                               ((INSTANCE) == DMA1_Stream2) || \
7072                                               ((INSTANCE) == DMA1_Stream3) || \
7073                                               ((INSTANCE) == DMA1_Stream4) || \
7074                                               ((INSTANCE) == DMA1_Stream5) || \
7075                                               ((INSTANCE) == DMA1_Stream6) || \
7076                                               ((INSTANCE) == DMA1_Stream7) || \
7077                                               ((INSTANCE) == DMA2_Stream0) || \
7078                                               ((INSTANCE) == DMA2_Stream1) || \
7079                                               ((INSTANCE) == DMA2_Stream2) || \
7080                                               ((INSTANCE) == DMA2_Stream3) || \
7081                                               ((INSTANCE) == DMA2_Stream4) || \
7082                                               ((INSTANCE) == DMA2_Stream5) || \
7083                                               ((INSTANCE) == DMA2_Stream6) || \
7084                                               ((INSTANCE) == DMA2_Stream7))
7085 
7086 /******************************* GPIO Instances *******************************/
7087 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7088                                         ((INSTANCE) == GPIOB) || \
7089                                         ((INSTANCE) == GPIOC) || \
7090                                         ((INSTANCE) == GPIOH))
7091 
7092 /******************************** I2C Instances *******************************/
7093 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7094                                        ((INSTANCE) == I2C2))
7095 
7096 /******************************* SMBUS Instances ******************************/
7097 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
7098 
7099 /******************************** I2S Instances *******************************/
7100 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \
7101                                         ((INSTANCE) == SPI2) || \
7102                                         ((INSTANCE) == SPI5))
7103 
7104 
7105 /******************************* LPTIM Instances ******************************/
7106 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
7107 
7108 /******************************* RNG Instances ********************************/
7109 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
7110 
7111 
7112 
7113 /****************************** RTC Instances *********************************/
7114 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
7115 
7116 
7117 /******************************** SPI Instances *******************************/
7118 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
7119                                        ((INSTANCE) == SPI2)  || \
7120                                        ((INSTANCE) == SPI5))
7121 
7122 
7123 /*************************** SPI Extended Instances ***************************/
7124 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \
7125                                            ((INSTANCE) == SPI2)    || \
7126                                            ((INSTANCE) == SPI5))
7127 /****************** TIM Instances : All supported instances *******************/
7128 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
7129                                    ((INSTANCE) == TIM5)   || \
7130                                    ((INSTANCE) == TIM6)   || \
7131                                    ((INSTANCE) == TIM9)   || \
7132                                    ((INSTANCE) == TIM11))
7133 
7134 /************* TIM Instances : at least 1 capture/compare channel *************/
7135 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
7136                                          ((INSTANCE) == TIM5)  || \
7137                                          ((INSTANCE) == TIM9)  || \
7138                                          ((INSTANCE) == TIM11))
7139 
7140 /************ TIM Instances : at least 2 capture/compare channels *************/
7141 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7142                                        ((INSTANCE) == TIM5) || \
7143                                        ((INSTANCE) == TIM9))
7144 
7145 /************ TIM Instances : at least 3 capture/compare channels *************/
7146 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
7147                                          ((INSTANCE) == TIM5))
7148 
7149 /************ TIM Instances : at least 4 capture/compare channels *************/
7150 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7151                                        ((INSTANCE) == TIM5))
7152 
7153 /******************** TIM Instances : Advanced-control timers *****************/
7154 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7155 
7156 /******************* TIM Instances : Timer input XOR function *****************/
7157 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
7158                                          ((INSTANCE) == TIM5))
7159 
7160 /****************** TIM Instances : DMA requests generation (UDE) *************/
7161 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7162                                        ((INSTANCE) == TIM5) || \
7163                                        ((INSTANCE) == TIM6))
7164 
7165 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7166 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7167                                           ((INSTANCE) == TIM5))
7168 
7169 /************ TIM Instances : DMA requests generation (COMDE) *****************/
7170 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7171                                           ((INSTANCE) == TIM5))
7172 
7173 /******************** TIM Instances : DMA burst feature ***********************/
7174 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7175                                              ((INSTANCE) == TIM5))
7176 
7177 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7178 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7179                                           ((INSTANCE) == TIM5) || \
7180                                           ((INSTANCE) == TIM6))
7181 
7182 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7183 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7184                                          ((INSTANCE) == TIM5) || \
7185                                          ((INSTANCE) == TIM9))
7186 /********************** TIM Instances : 32 bit Counter ************************/
7187 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5)
7188 
7189 /***************** TIM Instances : external trigger input available ************/
7190 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7191                                         ((INSTANCE) == TIM5))
7192 
7193 /****************** TIM Instances : remapping capability **********************/
7194 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5)  || \
7195                                          ((INSTANCE) == TIM11))
7196 
7197 /******************* TIM Instances : output(s) available **********************/
7198 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7199     ((((INSTANCE) == TIM1) &&                  \
7200      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7201       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7202       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7203       ((CHANNEL) == TIM_CHANNEL_4)))           \
7204     ||                                         \
7205     (((INSTANCE) == TIM5) &&                   \
7206      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7207       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7208       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7209       ((CHANNEL) == TIM_CHANNEL_4)))           \
7210     ||                                         \
7211     (((INSTANCE) == TIM9) &&                   \
7212      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7213       ((CHANNEL) == TIM_CHANNEL_2)))           \
7214     ||                                         \
7215     (((INSTANCE) == TIM11) &&                  \
7216      (((CHANNEL) == TIM_CHANNEL_1))))
7217 
7218 /************ TIM Instances : complementary output(s) available ***************/
7219 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7220    ((((INSTANCE) == TIM1) &&                    \
7221      (((CHANNEL) == TIM_CHANNEL_1) ||           \
7222       ((CHANNEL) == TIM_CHANNEL_2) ||           \
7223       ((CHANNEL) == TIM_CHANNEL_3))))
7224 
7225 /****************** TIM Instances : supporting counting mode selection ********/
7226 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7227                                                         ((INSTANCE) == TIM5))
7228 
7229 /****************** TIM Instances : supporting clock division *****************/
7230 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
7231                                                   ((INSTANCE) == TIM5)   || \
7232                                                   ((INSTANCE) == TIM9)   || \
7233                                                   ((INSTANCE) == TIM11))
7234 
7235 /****************** TIM Instances : supporting commutation event generation ***/
7236 
7237 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7238 
7239 /****************** TIM Instances : supporting OCxREF clear *******************/
7240 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
7241                                                        ((INSTANCE) == TIM5))
7242 
7243 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
7244 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7245                                                         ((INSTANCE) == TIM5) || \
7246                                                         ((INSTANCE) == TIM9))
7247 
7248 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
7249 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7250                                                         ((INSTANCE) == TIM5))
7251 
7252 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
7253 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
7254                                                         ((INSTANCE) == TIM5) || \
7255                                                         ((INSTANCE) == TIM9))
7256 
7257 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
7258 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
7259                                                         ((INSTANCE) == TIM5) || \
7260                                                         ((INSTANCE) == TIM9))
7261 
7262 /****************** TIM Instances : supporting repetition counter *************/
7263 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))
7264 
7265 /****************** TIM Instances : supporting encoder interface **************/
7266 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7267                                                       ((INSTANCE) == TIM5) || \
7268                                                       ((INSTANCE) == TIM9))
7269 /****************** TIM Instances : supporting Hall sensor interface **********/
7270 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
7271                                                           ((INSTANCE) == TIM5))
7272 /****************** TIM Instances : supporting the break function *************/
7273 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))
7274 
7275 /******************** USART Instances : Synchronous mode **********************/
7276 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7277                                      ((INSTANCE) == USART2) || \
7278                                      ((INSTANCE) == USART6))
7279 
7280 /******************** UART Instances : Half-Duplex mode **********************/
7281 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7282                                                ((INSTANCE) == USART2) || \
7283                                                ((INSTANCE) == USART6))
7284 
7285 /* Legacy defines */
7286 #define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
7287 
7288 /****************** UART Instances : Hardware Flow control ********************/
7289 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7290                                            ((INSTANCE) == USART2) || \
7291                                            ((INSTANCE) == USART6))
7292 /******************** UART Instances : LIN mode **********************/
7293 #define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
7294 
7295 /********************* UART Instances : Smart card mode ***********************/
7296 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7297                                          ((INSTANCE) == USART2) || \
7298                                          ((INSTANCE) == USART6))
7299 
7300 /*********************** UART Instances : IRDA mode ***************************/
7301 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7302                                     ((INSTANCE) == USART2) || \
7303                                     ((INSTANCE) == USART6))
7304 
7305 /****************************** IWDG Instances ********************************/
7306 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
7307 
7308 /****************************** WWDG Instances ********************************/
7309 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
7310 
7311 
7312 /***************************** FMPI2C Instances *******************************/
7313 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
7314 #define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE
7315 
7316 /*
7317  * @brief Specific devices reset values definitions
7318  */
7319 #define RCC_PLLCFGR_RST_VALUE              0x7F003010U
7320 #define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U
7321 
7322 #define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/
7323 #define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
7324 #define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
7325 #define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
7326 #define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
7327 #define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
7328 #define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
7329 #define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
7330 
7331 #define RCC_PLLN_MIN_VALUE                 50U
7332 #define RCC_PLLN_MAX_VALUE                432U
7333 
7334 #define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
7335 #define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
7336 #define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
7337 
7338 #define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
7339 #define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
7340 
7341 #define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
7342 #define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
7343 
7344 
7345 /**
7346   * @}
7347   */
7348 
7349 /**
7350   * @}
7351   */
7352 
7353 /**
7354   * @}
7355   */
7356 
7357 #ifdef __cplusplus
7358 }
7359 #endif /* __cplusplus */
7360 
7361 #endif /* __STM32F410Rx_H */
7362