1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G4xx_HAL_RCC_H 20 #define STM32G4xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g4xx_hal_def.h" 28 29 /** @addtogroup STM32G4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup RCC_Exported_Types RCC Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief RCC PLL configuration structure definition 44 */ 45 typedef struct 46 { 47 uint32_t PLLState; /*!< The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 54 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 55 56 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 57 This parameter must be a number between Min_Data = 8 and Max_Data = 127 */ 58 59 uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. 60 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 61 62 uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks. 63 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 64 65 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 66 User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ. 67 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 68 69 }RCC_PLLInitTypeDef; 70 71 /** 72 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 73 */ 74 typedef struct 75 { 76 uint32_t OscillatorType; /*!< The oscillators to be configured. 77 This parameter can be a value of @ref RCC_Oscillator_Type */ 78 79 uint32_t HSEState; /*!< The new state of the HSE. 80 This parameter can be a value of @ref RCC_HSE_Config */ 81 82 uint32_t LSEState; /*!< The new state of the LSE. 83 This parameter can be a value of @ref RCC_LSE_Config */ 84 85 uint32_t HSIState; /*!< The new state of the HSI. 86 This parameter can be a value of @ref RCC_HSI_Config */ 87 88 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 89 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 90 91 uint32_t LSIState; /*!< The new state of the LSI. 92 This parameter can be a value of @ref RCC_LSI_Config */ 93 94 uint32_t HSI48State; /*!< The new state of the HSI48. 95 This parameter can be a value of @ref RCC_HSI48_Config */ 96 97 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 98 99 }RCC_OscInitTypeDef; 100 101 /** 102 * @brief RCC System, AHB and APB busses clock configuration structure definition 103 */ 104 typedef struct 105 { 106 uint32_t ClockType; /*!< The clock to be configured. 107 This parameter can be a value of @ref RCC_System_Clock_Type */ 108 109 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 110 This parameter can be a value of @ref RCC_System_Clock_Source */ 111 112 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 113 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 114 115 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 116 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 117 118 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 119 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 120 121 }RCC_ClkInitTypeDef; 122 123 /** 124 * @} 125 */ 126 127 /* Exported constants --------------------------------------------------------*/ 128 /** @defgroup RCC_Exported_Constants RCC Exported Constants 129 * @{ 130 */ 131 132 /** @defgroup RCC_Timeout_Value Timeout Values 133 * @{ 134 */ 135 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 136 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 137 /** 138 * @} 139 */ 140 141 /** @defgroup RCC_Oscillator_Type Oscillator Type 142 * @{ 143 */ 144 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 145 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 146 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 147 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 148 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 149 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 150 /** 151 * @} 152 */ 153 154 /** @defgroup RCC_HSE_Config HSE Config 155 * @{ 156 */ 157 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 158 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 159 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 160 /** 161 * @} 162 */ 163 164 /** @defgroup RCC_LSE_Config LSE Config 165 * @{ 166 */ 167 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 168 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 169 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 170 /** 171 * @} 172 */ 173 174 /** @defgroup RCC_HSI_Config HSI Config 175 * @{ 176 */ 177 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 178 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 179 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup RCC_LSI_Config LSI Config 185 * @{ 186 */ 187 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 188 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 189 /** 190 * @} 191 */ 192 193 /** @defgroup RCC_HSI48_Config HSI48 Config 194 * @{ 195 */ 196 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 197 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_PLL_Config PLL Config 203 * @{ 204 */ 205 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ 206 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 207 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 213 * @{ 214 */ 215 #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ 216 #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ 217 #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ 218 #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ 219 #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ 220 #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ 221 #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ 222 #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ 223 #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ 224 #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ 225 #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ 226 #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ 227 #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ 228 #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ 229 #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ 230 #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 236 * @{ 237 */ 238 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 239 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 240 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 241 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 242 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 243 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 244 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 245 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 246 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 247 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 248 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 249 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 250 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 251 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 252 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 253 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 254 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 255 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 256 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 257 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 258 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 259 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 260 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 261 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 262 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 263 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 264 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 265 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 266 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 267 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 273 * @{ 274 */ 275 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 276 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 277 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 278 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 284 * @{ 285 */ 286 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 287 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 288 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 289 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 295 * @{ 296 */ 297 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ 298 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 299 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 305 * @{ 306 */ 307 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ 308 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 309 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCC_System_Clock_Type System Clock Type 315 * @{ 316 */ 317 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 318 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 319 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 320 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 321 /** 322 * @} 323 */ 324 325 /** @defgroup RCC_System_Clock_Source System Clock Source 326 * @{ 327 */ 328 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 329 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 330 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 336 * @{ 337 */ 338 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 339 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 340 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 346 * @{ 347 */ 348 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 349 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 350 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 351 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 352 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 353 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 354 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 355 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 356 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 362 * @{ 363 */ 364 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 365 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 366 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 367 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 368 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 369 /** 370 * @} 371 */ 372 373 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 374 * @{ 375 */ 376 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 377 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 378 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 379 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup RCC_MCO_Index MCO Index 385 * @{ 386 */ 387 /* 32 28 20 16 0 388 -------------------------------- 389 | MCO | GPIO | GPIO | GPIO | 390 | Index | AF | Port | Pin | 391 -------------------------------*/ 392 393 #define RCC_MCO_GPIOPORT_POS 16U 394 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 395 #define RCC_MCO_GPIOAF_POS 20U 396 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 397 #define RCC_MCO_INDEX_POS 28U 398 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 399 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 400 #define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 401 #define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) 402 403 /* Legacy Defines*/ 404 #define RCC_MCO1 RCC_MCO_PA8 405 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 406 /** 407 * @} 408 */ 409 410 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 411 * @{ 412 */ 413 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 414 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 415 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 416 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 417 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 418 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 419 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 420 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 426 * @{ 427 */ 428 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 429 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 430 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 431 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 432 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 433 /** 434 * @} 435 */ 436 437 /** @defgroup RCC_Interrupt Interrupts 438 * @{ 439 */ 440 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 441 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 442 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 443 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 444 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 445 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 446 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 447 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup RCC_Flag Flags 453 * Elements values convention: XXXYYYYYb 454 * - YYYYY : Flag position in the register 455 * - XXX : Register index 456 * - 001: CR register 457 * - 010: BDCR register 458 * - 011: CSR register 459 * - 100: CRRCR register 460 * @{ 461 */ 462 /* Flags in the CR register */ 463 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 464 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 465 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 466 467 /* Flags in the BDCR register */ 468 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 469 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 470 471 /* Flags in the CSR register */ 472 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 473 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 474 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 475 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 476 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 477 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 478 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 479 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 480 481 /* Flags in the CRRCR register */ 482 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 483 /** 484 * @} 485 */ 486 487 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 488 * @{ 489 */ 490 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 491 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 492 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 493 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 494 /** 495 * @} 496 */ 497 498 /** 499 * @} 500 */ 501 502 /* Exported macros -----------------------------------------------------------*/ 503 504 /** @defgroup RCC_Exported_Macros RCC Exported Macros 505 * @{ 506 */ 507 508 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 509 * @brief Enable or disable the AHB1 peripheral clock. 510 * @note After reset, the peripheral clock (used for registers read/write access) 511 * is disabled and the application software has to enable this clock before 512 * using it. 513 * @{ 514 */ 515 516 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 517 __IO uint32_t tmpreg; \ 518 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 519 /* Delay after an RCC peripheral clock enabling */ \ 520 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 521 UNUSED(tmpreg); \ 522 } while(0) 523 524 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 525 __IO uint32_t tmpreg; \ 526 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 527 /* Delay after an RCC peripheral clock enabling */ \ 528 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 529 UNUSED(tmpreg); \ 530 } while(0) 531 532 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 533 __IO uint32_t tmpreg; \ 534 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 535 /* Delay after an RCC peripheral clock enabling */ \ 536 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 537 UNUSED(tmpreg); \ 538 } while(0) 539 540 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 541 __IO uint32_t tmpreg; \ 542 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 543 /* Delay after an RCC peripheral clock enabling */ \ 544 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 545 UNUSED(tmpreg); \ 546 } while(0) 547 548 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 549 __IO uint32_t tmpreg; \ 550 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 551 /* Delay after an RCC peripheral clock enabling */ \ 552 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 553 UNUSED(tmpreg); \ 554 } while(0) 555 556 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 557 __IO uint32_t tmpreg; \ 558 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 559 /* Delay after an RCC peripheral clock enabling */ \ 560 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 561 UNUSED(tmpreg); \ 562 } while(0) 563 564 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 565 __IO uint32_t tmpreg; \ 566 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 567 /* Delay after an RCC peripheral clock enabling */ \ 568 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 569 UNUSED(tmpreg); \ 570 } while(0) 571 572 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 573 574 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 575 576 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 577 578 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 579 580 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 581 582 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 583 584 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 585 586 /** 587 * @} 588 */ 589 590 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 591 * @brief Enable or disable the AHB2 peripheral clock. 592 * @note After reset, the peripheral clock (used for registers read/write access) 593 * is disabled and the application software has to enable this clock before 594 * using it. 595 * @{ 596 */ 597 598 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 599 __IO uint32_t tmpreg; \ 600 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 601 /* Delay after an RCC peripheral clock enabling */ \ 602 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 603 UNUSED(tmpreg); \ 604 } while(0) 605 606 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 607 __IO uint32_t tmpreg; \ 608 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 609 /* Delay after an RCC peripheral clock enabling */ \ 610 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 611 UNUSED(tmpreg); \ 612 } while(0) 613 614 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 615 __IO uint32_t tmpreg; \ 616 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 617 /* Delay after an RCC peripheral clock enabling */ \ 618 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 619 UNUSED(tmpreg); \ 620 } while(0) 621 622 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 623 __IO uint32_t tmpreg; \ 624 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 625 /* Delay after an RCC peripheral clock enabling */ \ 626 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 627 UNUSED(tmpreg); \ 628 } while(0) 629 630 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 631 __IO uint32_t tmpreg; \ 632 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 633 /* Delay after an RCC peripheral clock enabling */ \ 634 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 635 UNUSED(tmpreg); \ 636 } while(0) 637 638 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 639 __IO uint32_t tmpreg; \ 640 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 641 /* Delay after an RCC peripheral clock enabling */ \ 642 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 643 UNUSED(tmpreg); \ 644 } while(0) 645 646 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 647 __IO uint32_t tmpreg; \ 648 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 649 /* Delay after an RCC peripheral clock enabling */ \ 650 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 651 UNUSED(tmpreg); \ 652 } while(0) 653 654 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 655 __IO uint32_t tmpreg; \ 656 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ 657 /* Delay after an RCC peripheral clock enabling */ \ 658 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ 659 UNUSED(tmpreg); \ 660 } while(0) 661 662 #if defined(ADC345_COMMON) 663 #define __HAL_RCC_ADC345_CLK_ENABLE() do { \ 664 __IO uint32_t tmpreg; \ 665 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ 666 /* Delay after an RCC peripheral clock enabling */ \ 667 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ 668 UNUSED(tmpreg); \ 669 } while(0) 670 #endif /* ADC345_COMMON */ 671 672 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 673 __IO uint32_t tmpreg; \ 674 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 675 /* Delay after an RCC peripheral clock enabling */ \ 676 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 677 UNUSED(tmpreg); \ 678 } while(0) 679 680 #if defined(DAC2) 681 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ 682 __IO uint32_t tmpreg; \ 683 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ 684 /* Delay after an RCC peripheral clock enabling */ \ 685 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ 686 UNUSED(tmpreg); \ 687 } while(0) 688 #endif /* DAC2 */ 689 690 #define __HAL_RCC_DAC3_CLK_ENABLE() do { \ 691 __IO uint32_t tmpreg; \ 692 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ 693 /* Delay after an RCC peripheral clock enabling */ \ 694 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ 695 UNUSED(tmpreg); \ 696 } while(0) 697 698 #if defined(DAC4) 699 #define __HAL_RCC_DAC4_CLK_ENABLE() do { \ 700 __IO uint32_t tmpreg; \ 701 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ 702 /* Delay after an RCC peripheral clock enabling */ \ 703 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ 704 UNUSED(tmpreg); \ 705 } while(0) 706 #endif /* DAC4 */ 707 708 #if defined(AES) 709 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 710 __IO uint32_t tmpreg; \ 711 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 712 /* Delay after an RCC peripheral clock enabling */ \ 713 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 714 UNUSED(tmpreg); \ 715 } while(0) 716 #endif /* AES */ 717 718 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 719 __IO uint32_t tmpreg; \ 720 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 721 /* Delay after an RCC peripheral clock enabling */ \ 722 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 723 UNUSED(tmpreg); \ 724 } while(0) 725 726 727 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 728 729 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 730 731 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 732 733 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 734 735 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 736 737 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 738 739 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 740 741 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) 742 743 #if defined(ADC345_COMMON) 744 #define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) 745 #endif /* ADC345_COMMON */ 746 747 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) 748 749 #if defined(DAC2) 750 #define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) 751 #endif /* DAC2 */ 752 753 #define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) 754 755 #if defined(DAC4) 756 #define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) 757 #endif /* DAC4 */ 758 759 #if defined(AES) 760 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 761 #endif /* AES */ 762 763 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 764 765 /** 766 * @} 767 */ 768 769 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 770 * @brief Enable or disable the AHB3 peripheral clock. 771 * @note After reset, the peripheral clock (used for registers read/write access) 772 * is disabled and the application software has to enable this clock before 773 * using it. 774 * @{ 775 */ 776 777 #if defined(FMC_BANK1) 778 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 779 __IO uint32_t tmpreg; \ 780 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 781 /* Delay after an RCC peripheral clock enabling */ \ 782 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 783 UNUSED(tmpreg); \ 784 } while(0) 785 #endif /* FMC_BANK1 */ 786 787 #if defined(QUADSPI) 788 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 789 __IO uint32_t tmpreg; \ 790 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 791 /* Delay after an RCC peripheral clock enabling */ \ 792 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 793 UNUSED(tmpreg); \ 794 } while(0) 795 #endif /* QUADSPI */ 796 797 #if defined(FMC_BANK1) 798 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 799 #endif /* FMC_BANK1 */ 800 801 #if defined(QUADSPI) 802 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 803 #endif /* QUADSPI */ 804 805 /** 806 * @} 807 */ 808 809 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 810 * @brief Enable or disable the APB1 peripheral clock. 811 * @note After reset, the peripheral clock (used for registers read/write access) 812 * is disabled and the application software has to enable this clock before 813 * using it. 814 * @{ 815 */ 816 817 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 818 __IO uint32_t tmpreg; \ 819 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 820 /* Delay after an RCC peripheral clock enabling */ \ 821 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 822 UNUSED(tmpreg); \ 823 } while(0) 824 825 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 826 __IO uint32_t tmpreg; \ 827 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 828 /* Delay after an RCC peripheral clock enabling */ \ 829 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 830 UNUSED(tmpreg); \ 831 } while(0) 832 833 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 834 __IO uint32_t tmpreg; \ 835 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 836 /* Delay after an RCC peripheral clock enabling */ \ 837 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 838 UNUSED(tmpreg); \ 839 } while(0) 840 841 #if defined(TIM5) 842 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 843 __IO uint32_t tmpreg; \ 844 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 845 /* Delay after an RCC peripheral clock enabling */ \ 846 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 847 UNUSED(tmpreg); \ 848 } while(0) 849 #endif /* TIM5 */ 850 851 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 852 __IO uint32_t tmpreg; \ 853 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 854 /* Delay after an RCC peripheral clock enabling */ \ 855 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 856 UNUSED(tmpreg); \ 857 } while(0) 858 859 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 860 __IO uint32_t tmpreg; \ 861 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 862 /* Delay after an RCC peripheral clock enabling */ \ 863 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 864 UNUSED(tmpreg); \ 865 } while(0) 866 867 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 868 __IO uint32_t tmpreg; \ 869 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 870 /* Delay after an RCC peripheral clock enabling */ \ 871 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 872 UNUSED(tmpreg); \ 873 } while(0) 874 875 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 876 __IO uint32_t tmpreg; \ 877 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 878 /* Delay after an RCC peripheral clock enabling */ \ 879 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 880 UNUSED(tmpreg); \ 881 } while(0) 882 883 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 884 __IO uint32_t tmpreg; \ 885 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 886 /* Delay after an RCC peripheral clock enabling */ \ 887 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 888 UNUSED(tmpreg); \ 889 } while(0) 890 891 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 892 __IO uint32_t tmpreg; \ 893 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 894 /* Delay after an RCC peripheral clock enabling */ \ 895 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 896 UNUSED(tmpreg); \ 897 } while(0) 898 899 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 900 __IO uint32_t tmpreg; \ 901 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 902 /* Delay after an RCC peripheral clock enabling */ \ 903 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 904 UNUSED(tmpreg); \ 905 } while(0) 906 907 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 908 __IO uint32_t tmpreg; \ 909 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 910 /* Delay after an RCC peripheral clock enabling */ \ 911 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 912 UNUSED(tmpreg); \ 913 } while(0) 914 915 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 916 __IO uint32_t tmpreg; \ 917 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 918 /* Delay after an RCC peripheral clock enabling */ \ 919 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 920 UNUSED(tmpreg); \ 921 } while(0) 922 923 #if defined(UART4) 924 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 925 __IO uint32_t tmpreg; \ 926 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 927 /* Delay after an RCC peripheral clock enabling */ \ 928 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 929 UNUSED(tmpreg); \ 930 } while(0) 931 #endif /* UART4 */ 932 933 #if defined(UART5) 934 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 935 __IO uint32_t tmpreg; \ 936 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 937 /* Delay after an RCC peripheral clock enabling */ \ 938 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 939 UNUSED(tmpreg); \ 940 } while(0) 941 #endif /* UART5 */ 942 943 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 944 __IO uint32_t tmpreg; \ 945 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 946 /* Delay after an RCC peripheral clock enabling */ \ 947 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 948 UNUSED(tmpreg); \ 949 } while(0) 950 951 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 952 __IO uint32_t tmpreg; \ 953 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 954 /* Delay after an RCC peripheral clock enabling */ \ 955 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 956 UNUSED(tmpreg); \ 957 } while(0) 958 959 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 960 __IO uint32_t tmpreg; \ 961 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ 962 /* Delay after an RCC peripheral clock enabling */ \ 963 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ 964 UNUSED(tmpreg); \ 965 } while(0) 966 967 #if defined(FDCAN1) 968 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 969 __IO uint32_t tmpreg; \ 970 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ 971 /* Delay after an RCC peripheral clock enabling */ \ 972 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ 973 UNUSED(tmpreg); \ 974 } while(0) 975 #endif /* FDCAN1 */ 976 977 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 978 __IO uint32_t tmpreg; \ 979 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 980 /* Delay after an RCC peripheral clock enabling */ \ 981 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 982 UNUSED(tmpreg); \ 983 } while(0) 984 985 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 986 __IO uint32_t tmpreg; \ 987 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 988 /* Delay after an RCC peripheral clock enabling */ \ 989 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 990 UNUSED(tmpreg); \ 991 } while(0) 992 993 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 994 __IO uint32_t tmpreg; \ 995 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 996 /* Delay after an RCC peripheral clock enabling */ \ 997 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 998 UNUSED(tmpreg); \ 999 } while(0) 1000 1001 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1002 __IO uint32_t tmpreg; \ 1003 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1004 /* Delay after an RCC peripheral clock enabling */ \ 1005 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1006 UNUSED(tmpreg); \ 1007 } while(0) 1008 1009 #if defined(I2C4) 1010 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1011 __IO uint32_t tmpreg; \ 1012 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1013 /* Delay after an RCC peripheral clock enabling */ \ 1014 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1015 UNUSED(tmpreg); \ 1016 } while(0) 1017 #endif /* I2C4 */ 1018 1019 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg; \ 1021 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1024 UNUSED(tmpreg); \ 1025 } while(0) 1026 1027 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1028 1029 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1030 1031 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1032 1033 #if defined(TIM5) 1034 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1035 #endif /* TIM5 */ 1036 1037 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1038 1039 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1040 1041 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1042 1043 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1044 1045 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN) 1046 1047 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1048 1049 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1050 1051 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1052 1053 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1054 1055 #if defined(UART4) 1056 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1057 #endif /* UART4 */ 1058 1059 #if defined(UART5) 1060 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1061 #endif /* UART5 */ 1062 1063 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1064 1065 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1066 1067 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) 1068 1069 #if defined(FDCAN1) 1070 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) 1071 #endif /* FDCAN1 */ 1072 1073 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1074 1075 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1076 1077 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1078 1079 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1080 1081 #if defined(I2C4) 1082 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1083 #endif /* I2C4 */ 1084 1085 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1086 1087 /** 1088 * @} 1089 */ 1090 1091 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1092 * @brief Enable or disable the APB2 peripheral clock. 1093 * @note After reset, the peripheral clock (used for registers read/write access) 1094 * is disabled and the application software has to enable this clock before 1095 * using it. 1096 * @{ 1097 */ 1098 1099 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1100 __IO uint32_t tmpreg; \ 1101 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1102 /* Delay after an RCC peripheral clock enabling */ \ 1103 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1104 UNUSED(tmpreg); \ 1105 } while(0) 1106 1107 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1108 __IO uint32_t tmpreg; \ 1109 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1110 /* Delay after an RCC peripheral clock enabling */ \ 1111 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1112 UNUSED(tmpreg); \ 1113 } while(0) 1114 1115 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1116 __IO uint32_t tmpreg; \ 1117 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1118 /* Delay after an RCC peripheral clock enabling */ \ 1119 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1120 UNUSED(tmpreg); \ 1121 } while(0) 1122 1123 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1124 __IO uint32_t tmpreg; \ 1125 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1126 /* Delay after an RCC peripheral clock enabling */ \ 1127 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1128 UNUSED(tmpreg); \ 1129 } while(0) 1130 1131 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1132 __IO uint32_t tmpreg; \ 1133 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1134 /* Delay after an RCC peripheral clock enabling */ \ 1135 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1136 UNUSED(tmpreg); \ 1137 } while(0) 1138 1139 #if defined(SPI4) 1140 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1141 __IO uint32_t tmpreg; \ 1142 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1143 /* Delay after an RCC peripheral clock enabling */ \ 1144 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1145 UNUSED(tmpreg); \ 1146 } while(0) 1147 #endif /* SPI4 */ 1148 1149 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1150 __IO uint32_t tmpreg; \ 1151 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1152 /* Delay after an RCC peripheral clock enabling */ \ 1153 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1154 UNUSED(tmpreg); \ 1155 } while(0) 1156 1157 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1158 __IO uint32_t tmpreg; \ 1159 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1160 /* Delay after an RCC peripheral clock enabling */ \ 1161 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1162 UNUSED(tmpreg); \ 1163 } while(0) 1164 1165 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1166 __IO uint32_t tmpreg; \ 1167 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1168 /* Delay after an RCC peripheral clock enabling */ \ 1169 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1170 UNUSED(tmpreg); \ 1171 } while(0) 1172 1173 #if defined(TIM20) 1174 #define __HAL_RCC_TIM20_CLK_ENABLE() do { \ 1175 __IO uint32_t tmpreg; \ 1176 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ 1177 /* Delay after an RCC peripheral clock enabling */ \ 1178 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ 1179 UNUSED(tmpreg); \ 1180 } while(0) 1181 #endif /* TIM20 */ 1182 1183 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1184 __IO uint32_t tmpreg; \ 1185 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1186 /* Delay after an RCC peripheral clock enabling */ \ 1187 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1188 UNUSED(tmpreg); \ 1189 } while(0) 1190 1191 #if defined(HRTIM1) 1192 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ 1193 __IO uint32_t tmpreg; \ 1194 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ 1195 /* Delay after an RCC peripheral clock enabling */ \ 1196 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ 1197 UNUSED(tmpreg); \ 1198 } while(0) 1199 #endif /* HRTIM1 */ 1200 1201 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1202 1203 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1204 1205 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1206 1207 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1208 1209 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1210 1211 #if defined(SPI4) 1212 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) 1213 #endif /* SPI4 */ 1214 1215 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1216 1217 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1218 1219 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1220 1221 #if defined(TIM20) 1222 #define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) 1223 #endif /* TIM20 */ 1224 1225 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1226 1227 #if defined(HRTIM1) 1228 #define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) 1229 #endif /* HRTIM1 */ 1230 1231 /** 1232 * @} 1233 */ 1234 1235 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1236 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1237 * @note After reset, the peripheral clock (used for registers read/write access) 1238 * is disabled and the application software has to enable this clock before 1239 * using it. 1240 * @{ 1241 */ 1242 1243 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1244 1245 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1246 1247 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1248 1249 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 1250 1251 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 1252 1253 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1254 1255 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1256 1257 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1258 1259 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1260 1261 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1262 1263 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 1264 1265 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 1266 1267 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1268 1269 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1270 1271 /** 1272 * @} 1273 */ 1274 1275 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1276 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1277 * @note After reset, the peripheral clock (used for registers read/write access) 1278 * is disabled and the application software has to enable this clock before 1279 * using it. 1280 * @{ 1281 */ 1282 1283 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1284 1285 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 1286 1287 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1288 1289 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1290 1291 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1292 1293 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1294 1295 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1296 1297 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U) 1298 1299 #if defined(ADC345_COMMON) 1300 #define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U) 1301 #endif /* ADC345_COMMON */ 1302 1303 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) 1304 1305 #if defined(DAC2) 1306 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U) 1307 #endif /* DAC2 */ 1308 1309 #define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U) 1310 1311 #if defined(DAC4) 1312 #define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U) 1313 #endif /* DAC4 */ 1314 1315 #if defined(AES) 1316 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1317 #endif /* AES */ 1318 1319 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1320 1321 1322 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1323 1324 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1325 1326 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1327 1328 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1329 1330 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1331 1332 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1333 1334 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1335 1336 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U) 1337 1338 #if defined(ADC345_COMMON) 1339 #define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U) 1340 #endif /* ADC345_COMMON */ 1341 1342 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) 1343 1344 #if defined(DAC2) 1345 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U) 1346 #endif /* DAC2 */ 1347 1348 #define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U) 1349 1350 #if defined(DAC4) 1351 #define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U) 1352 #endif /* DAC4 */ 1353 1354 #if defined(AES) 1355 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1356 #endif /* AES */ 1357 1358 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1365 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1366 * @note After reset, the peripheral clock (used for registers read/write access) 1367 * is disabled and the application software has to enable this clock before 1368 * using it. 1369 * @{ 1370 */ 1371 1372 #if defined(FMC_BANK1) 1373 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1374 #endif /* FMC_BANK1 */ 1375 1376 #if defined(QUADSPI) 1377 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) 1378 #endif /* QUADSPI */ 1379 1380 #if defined(FMC_BANK1) 1381 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1382 #endif /* FMC_BANK1 */ 1383 1384 #if defined(QUADSPI) 1385 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) 1386 #endif /* QUADSPI */ 1387 1388 /** 1389 * @} 1390 */ 1391 1392 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1393 * @brief Check whether the APB1 peripheral clock is enabled or not. 1394 * @note After reset, the peripheral clock (used for registers read/write access) 1395 * is disabled and the application software has to enable this clock before 1396 * using it. 1397 * @{ 1398 */ 1399 1400 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1401 1402 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1403 1404 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1405 1406 #if defined(TIM5) 1407 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1408 #endif /* TIM5 */ 1409 1410 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1411 1412 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1413 1414 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1415 1416 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1417 1418 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1419 1420 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1421 1422 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1423 1424 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1425 1426 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1427 1428 #if defined(UART4) 1429 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1430 #endif /* UART4 */ 1431 1432 #if defined(UART5) 1433 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1434 #endif /* UART5 */ 1435 1436 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1437 1438 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1439 1440 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U) 1441 1442 #if defined(FDCAN1) 1443 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U) 1444 #endif /* FDCAN1 */ 1445 1446 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1447 1448 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1449 1450 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1451 1452 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1453 1454 #if defined(I2C4) 1455 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1456 #endif /* I2C4 */ 1457 1458 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 1459 1460 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1461 1462 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1463 1464 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1465 1466 #if defined(TIM5) 1467 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1468 #endif /* TIM5 */ 1469 1470 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1471 1472 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1473 1474 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1475 1476 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 1477 1478 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 1479 1480 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1481 1482 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 1483 1484 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1485 1486 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1487 1488 #if defined(UART4) 1489 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1490 #endif /* UART4 */ 1491 1492 #if defined(UART5) 1493 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1494 #endif /* UART5 */ 1495 1496 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1497 1498 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1499 1500 #if defined(USB) 1501 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U) 1502 #endif /* USB */ 1503 1504 #if defined(FDCAN1) 1505 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U) 1506 #endif /* FDCAN1 */ 1507 1508 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 1509 1510 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 1511 1512 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 1513 1514 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 1515 1516 #if defined(I2C4) 1517 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1518 #endif /* I2C4 */ 1519 1520 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) 1521 1522 /** 1523 * @} 1524 */ 1525 1526 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1527 * @brief Check whether the APB2 peripheral clock is enabled or not. 1528 * @note After reset, the peripheral clock (used for registers read/write access) 1529 * is disabled and the application software has to enable this clock before 1530 * using it. 1531 * @{ 1532 */ 1533 1534 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 1535 1536 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 1537 1538 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 1539 1540 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 1541 1542 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 1543 1544 #if defined(SPI4) 1545 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) 1546 #endif /* SPI4 */ 1547 1548 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 1549 1550 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 1551 1552 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 1553 1554 #if defined(TIM20) 1555 #define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U) 1556 #endif /* TIM20 */ 1557 1558 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 1559 1560 #if defined(HRTIM1) 1561 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U) 1562 #endif /* HRTIM1 */ 1563 1564 1565 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 1566 1567 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 1568 1569 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 1570 1571 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 1572 1573 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 1574 1575 #if defined(SPI4) 1576 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) 1577 #endif /* SPI4 */ 1578 1579 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 1580 1581 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 1582 1583 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 1584 1585 #if defined(TIM20) 1586 #define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U) 1587 #endif /* TIM20 */ 1588 1589 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 1590 1591 #if defined(HRTIM1) 1592 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U) 1593 #endif /* HRTIM1 */ 1594 1595 /** 1596 * @} 1597 */ 1598 1599 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1600 * @brief Force or release AHB1 peripheral reset. 1601 * @{ 1602 */ 1603 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 1604 1605 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1606 1607 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1608 1609 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1610 1611 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 1612 1613 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 1614 1615 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1616 1617 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1618 1619 1620 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 1621 1622 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1623 1624 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1625 1626 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1627 1628 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 1629 1630 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 1631 1632 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1633 1634 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1635 1636 /** 1637 * @} 1638 */ 1639 1640 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1641 * @brief Force or release AHB2 peripheral reset. 1642 * @{ 1643 */ 1644 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 1645 1646 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1647 1648 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1649 1650 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1651 1652 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1653 1654 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1655 1656 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1657 1658 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1659 1660 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) 1661 1662 #if defined(ADC345_COMMON) 1663 #define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) 1664 #endif /* ADC345_COMMON */ 1665 1666 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 1667 1668 #if defined(DAC2) 1669 #define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) 1670 #endif /* DAC2 */ 1671 1672 #define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) 1673 1674 #if defined(DAC4) 1675 #define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) 1676 #endif /* DAC4 */ 1677 1678 #if defined(AES) 1679 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1680 #endif /* AES */ 1681 1682 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1683 1684 1685 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 1686 1687 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1688 1689 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1690 1691 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1692 1693 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1694 1695 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1696 1697 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1698 1699 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1700 1701 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) 1702 1703 #if defined(ADC345_COMMON) 1704 #define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) 1705 #endif /* ADC345_COMMON */ 1706 1707 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 1708 1709 #if defined(DAC2) 1710 #define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) 1711 #endif /* DAC2 */ 1712 1713 #define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) 1714 1715 #if defined(DAC4) 1716 #define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) 1717 #endif /* DAC4 */ 1718 1719 #if defined(AES) 1720 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1721 #endif /* AES */ 1722 1723 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1724 1725 /** 1726 * @} 1727 */ 1728 1729 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1730 * @brief Force or release AHB3 peripheral reset. 1731 * @{ 1732 */ 1733 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) 1734 1735 #if defined(FMC_BANK1) 1736 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1737 #endif /* FMC_BANK1 */ 1738 1739 #if defined(QUADSPI) 1740 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 1741 #endif /* QUADSPI */ 1742 1743 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 1744 1745 #if defined(FMC_BANK1) 1746 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1747 #endif /* FMC_BANK1 */ 1748 1749 #if defined(QUADSPI) 1750 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 1751 #endif /* QUADSPI */ 1752 1753 /** 1754 * @} 1755 */ 1756 1757 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1758 * @brief Force or release APB1 peripheral reset. 1759 * @{ 1760 */ 1761 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) 1762 1763 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1764 1765 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1766 1767 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1768 1769 #if defined(TIM5) 1770 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1771 #endif /* TIM5 */ 1772 1773 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1774 1775 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1776 1777 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1778 1779 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1780 1781 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1782 1783 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1784 1785 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1786 1787 #if defined(UART4) 1788 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1789 #endif /* UART4 */ 1790 1791 #if defined(UART5) 1792 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1793 #endif /* UART5 */ 1794 1795 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1796 1797 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1798 1799 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) 1800 1801 #if defined(FDCAN1) 1802 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) 1803 #endif /* FDCAN1 */ 1804 1805 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1806 1807 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1808 1809 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1810 1811 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1812 1813 #if defined(I2C4) 1814 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1815 #endif /* I2C4 */ 1816 1817 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1818 1819 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) 1820 1821 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1822 1823 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1824 1825 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1826 1827 #if defined(TIM5) 1828 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1829 #endif /* TIM5 */ 1830 1831 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1832 1833 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1834 1835 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1836 1837 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1838 1839 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1840 1841 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1842 1843 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1844 1845 #if defined(UART4) 1846 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1847 #endif /* UART4 */ 1848 1849 #if defined(UART5) 1850 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1851 #endif /* UART5 */ 1852 1853 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1854 1855 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1856 1857 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) 1858 1859 #if defined(FDCAN1) 1860 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) 1861 #endif /* FDCAN1 */ 1862 1863 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1864 1865 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1866 1867 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1868 1869 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1870 1871 #if defined(I2C4) 1872 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1873 #endif /* I2C4 */ 1874 1875 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1876 1877 /** 1878 * @} 1879 */ 1880 1881 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1882 * @brief Force or release APB2 peripheral reset. 1883 * @{ 1884 */ 1885 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 1886 1887 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1888 1889 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1890 1891 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1892 1893 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1894 1895 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1896 1897 #if defined(SPI4) 1898 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 1899 #endif /* SPI4 */ 1900 1901 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1902 1903 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1904 1905 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1906 1907 #if defined(TIM20) 1908 #define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) 1909 #endif /* TIM20 */ 1910 1911 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1912 1913 #if defined(HRTIM1) 1914 #define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) 1915 #endif /* HRTIM1 */ 1916 1917 1918 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 1919 1920 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1921 1922 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1923 1924 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1925 1926 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1927 1928 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1929 1930 #if defined(SPI4) 1931 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 1932 #endif /* SPI4 */ 1933 1934 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1935 1936 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1937 1938 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1939 1940 #if defined(TIM20) 1941 #define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) 1942 #endif /* TIM20 */ 1943 1944 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1945 1946 #if defined(HRTIM1) 1947 #define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) 1948 #endif /* HRTIM1 */ 1949 1950 /** 1951 * @} 1952 */ 1953 1954 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 1955 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 1956 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1957 * power consumption. 1958 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1959 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1960 * @{ 1961 */ 1962 1963 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 1964 1965 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 1966 1967 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 1968 1969 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 1970 1971 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 1972 1973 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 1974 1975 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 1976 1977 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 1978 1979 1980 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 1981 1982 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 1983 1984 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 1985 1986 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 1987 1988 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 1989 1990 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 1991 1992 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 1993 1994 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 1995 1996 /** 1997 * @} 1998 */ 1999 2000 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2001 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2002 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2003 * power consumption. 2004 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2005 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2006 * @{ 2007 */ 2008 2009 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2010 2011 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2012 2013 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2014 2015 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2016 2017 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2018 2019 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2020 2021 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2022 2023 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2024 2025 #define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) 2026 2027 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) 2028 2029 #if defined(ADC345_COMMON) 2030 #define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) 2031 #endif /* ADC345_COMMON */ 2032 2033 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) 2034 2035 #if defined(DAC2) 2036 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) 2037 #endif /* DAC2 */ 2038 2039 #define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) 2040 2041 #if defined(DAC4) 2042 #define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) 2043 #endif /* DAC4 */ 2044 2045 #if defined(AES) 2046 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2047 #endif /* AES */ 2048 2049 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2050 2051 2052 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2053 2054 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2055 2056 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2057 2058 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2059 2060 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2061 2062 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2063 2064 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2065 2066 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2067 2068 #define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) 2069 2070 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) 2071 2072 #if defined(ADC345_COMMON) 2073 #define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) 2074 #endif /* ADC345_COMMON */ 2075 2076 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) 2077 2078 #if defined(DAC2) 2079 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) 2080 #endif /* DAC2 */ 2081 2082 #define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) 2083 2084 #if defined(DAC4) 2085 #define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) 2086 #endif /* DAC4 */ 2087 2088 #if defined(AES) 2089 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2090 #endif /* AES */ 2091 2092 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2093 2094 /** 2095 * @} 2096 */ 2097 2098 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2099 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2100 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2101 * power consumption. 2102 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2103 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2104 * @{ 2105 */ 2106 2107 #if defined(FMC_BANK1) 2108 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2109 #endif /* FMC_BANK1 */ 2110 2111 #if defined(QUADSPI) 2112 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2113 #endif /* QUADSPI */ 2114 2115 #if defined(FMC_BANK1) 2116 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2117 #endif /* FMC_BANK1 */ 2118 2119 #if defined(QUADSPI) 2120 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 2121 #endif /* QUADSPI */ 2122 2123 /** 2124 * @} 2125 */ 2126 2127 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2128 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2129 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2130 * power consumption. 2131 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2132 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2133 * @{ 2134 */ 2135 2136 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2137 2138 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2139 2140 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2141 2142 #if defined(TIM5) 2143 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2144 #endif /* TIM5 */ 2145 2146 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2147 2148 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2149 2150 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2151 2152 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2153 2154 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2155 2156 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2157 2158 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2159 2160 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2161 2162 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2163 2164 #if defined(UART4) 2165 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2166 #endif /* UART4 */ 2167 2168 #if defined(UART5) 2169 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2170 #endif /* UART5 */ 2171 2172 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2173 2174 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2175 2176 #if defined(USB) 2177 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) 2178 #endif /* USB */ 2179 2180 #if defined(FDCAN1) 2181 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) 2182 #endif /* FDCAN1 */ 2183 2184 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2185 2186 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2187 2188 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2189 2190 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2191 2192 #if defined(I2C4) 2193 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2194 #endif /* I2C4 */ 2195 2196 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2197 2198 2199 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2200 2201 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2202 2203 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2204 2205 #if defined(TIM5) 2206 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2207 #endif /* TIM5 */ 2208 2209 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2210 2211 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2212 2213 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2214 2215 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2216 2217 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2218 2219 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2220 2221 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2222 2223 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2224 2225 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2226 2227 #if defined(UART4) 2228 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2229 #endif /* UART4 */ 2230 2231 #if defined(UART5) 2232 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2233 #endif /* UART5 */ 2234 2235 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2236 2237 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2238 2239 #if defined(USB) 2240 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) 2241 #endif /* USB */ 2242 2243 #if defined(FDCAN1) 2244 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) 2245 #endif /* FDCAN1 */ 2246 2247 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2248 2249 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2250 2251 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2252 2253 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2254 2255 #if defined(I2C4) 2256 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2257 #endif /* I2C4 */ 2258 2259 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2260 2261 /** 2262 * @} 2263 */ 2264 2265 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2266 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2267 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2268 * power consumption. 2269 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2270 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2271 * @{ 2272 */ 2273 2274 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2275 2276 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2277 2278 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2279 2280 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2281 2282 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2283 2284 #if defined(SPI4) 2285 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) 2286 #endif /* SPI4 */ 2287 2288 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2289 2290 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2291 2292 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2293 2294 #if defined(TIM20) 2295 #define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) 2296 #endif /* TIM20 */ 2297 2298 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2299 2300 #if defined(HRTIM1) 2301 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) 2302 #endif /* HRTIM1 */ 2303 2304 2305 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2306 2307 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2308 2309 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2310 2311 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2312 2313 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2314 2315 #if defined(SPI4) 2316 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) 2317 #endif /* SPI4 */ 2318 2319 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2320 2321 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2322 2323 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2324 2325 #if defined(TIM20) 2326 #define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) 2327 #endif /* TIM20 */ 2328 2329 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2330 2331 #if defined(HRTIM1) 2332 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) 2333 #endif /* HRTIM1 */ 2334 2335 /** 2336 * @} 2337 */ 2338 2339 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2340 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2341 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2342 * power consumption. 2343 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2344 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2345 * @{ 2346 */ 2347 2348 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 2349 2350 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 2351 2352 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 2353 2354 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U) 2355 2356 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U) 2357 2358 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 2359 2360 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 2361 2362 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 2363 2364 2365 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 2366 2367 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 2368 2369 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 2370 2371 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U) 2372 2373 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U) 2374 2375 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 2376 2377 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 2378 2379 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 2380 2381 /** 2382 * @} 2383 */ 2384 2385 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2386 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2387 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2388 * power consumption. 2389 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2390 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2391 * @{ 2392 */ 2393 2394 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 2395 2396 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 2397 2398 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 2399 2400 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 2401 2402 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 2403 2404 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 2405 2406 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 2407 2408 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 2409 2410 #define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U) 2411 2412 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U) 2413 2414 #if defined(ADC345_COMMON) 2415 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U) 2416 #endif /* ADC345_COMMON */ 2417 2418 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U) 2419 2420 #if defined(DAC2) 2421 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U) 2422 #endif /* DAC2 */ 2423 2424 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U) 2425 2426 #if defined(DAC4) 2427 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U) 2428 #endif /* DAC4 */ 2429 2430 #if defined(AES) 2431 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 2432 #endif /* AES */ 2433 2434 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 2435 2436 2437 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 2438 2439 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 2440 2441 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 2442 2443 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 2444 2445 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 2446 2447 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 2448 2449 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 2450 2451 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 2452 2453 #define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U) 2454 2455 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U) 2456 2457 #if defined(ADC345_COMMON) 2458 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U) 2459 #endif /* ADC345_COMMON */ 2460 2461 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U) 2462 2463 #if defined(DAC2) 2464 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U) 2465 #endif /* DAC2 */ 2466 2467 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U) 2468 2469 #if defined(DAC4) 2470 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U) 2471 #endif /* DAC4 */ 2472 2473 #if defined(AES) 2474 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 2475 #endif /* AES */ 2476 2477 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 2478 2479 /** 2480 * @} 2481 */ 2482 2483 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2484 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2485 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2486 * power consumption. 2487 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2488 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2489 * @{ 2490 */ 2491 2492 #if defined(FMC_BANK1) 2493 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 2494 #endif /* FMC_BANK1 */ 2495 2496 #if defined(QUADSPI) 2497 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) 2498 #endif /* QUADSPI */ 2499 2500 #if defined(FMC_BANK1) 2501 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 2502 #endif /* FMC_BANK1 */ 2503 2504 #if defined(QUADSPI) 2505 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) 2506 #endif /* QUADSPI */ 2507 2508 /** 2509 * @} 2510 */ 2511 2512 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2513 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2514 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2515 * power consumption. 2516 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2517 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2518 * @{ 2519 */ 2520 2521 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 2522 2523 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 2524 2525 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 2526 2527 #if defined(TIM5) 2528 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 2529 #endif /* TIM5 */ 2530 2531 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 2532 2533 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 2534 2535 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 2536 2537 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 2538 2539 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 2540 2541 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 2542 2543 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 2544 2545 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 2546 2547 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 2548 2549 #if defined(UART4) 2550 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 2551 #endif /* UART4 */ 2552 2553 #if defined(UART5) 2554 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 2555 #endif /* UART5 */ 2556 2557 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 2558 2559 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 2560 2561 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U) 2562 2563 #if defined(FDCAN1) 2564 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U) 2565 #endif /* FDCAN1 */ 2566 2567 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 2568 2569 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 2570 2571 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 2572 2573 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 2574 2575 #if defined(I2C4) 2576 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 2577 #endif /* I2C4 */ 2578 2579 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U) 2580 2581 2582 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 2583 2584 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 2585 2586 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 2587 2588 #if defined(TIM5) 2589 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 2590 #endif /* TIM5 */ 2591 2592 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 2593 2594 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 2595 2596 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 2597 2598 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 2599 2600 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 2601 2602 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 2603 2604 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 2605 2606 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 2607 2608 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 2609 2610 #if defined(UART4) 2611 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 2612 #endif /* UART4 */ 2613 2614 #if defined(UART5) 2615 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 2616 #endif /* UART5 */ 2617 2618 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 2619 2620 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 2621 2622 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U) 2623 2624 #if defined(FDCAN1) 2625 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U) 2626 #endif /* FDCAN1 */ 2627 2628 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 2629 2630 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 2631 2632 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 2633 2634 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 2635 2636 #if defined(I2C4) 2637 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 2638 #endif /* I2C4 */ 2639 2640 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U) 2641 2642 /** 2643 * @} 2644 */ 2645 2646 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2647 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2648 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2649 * power consumption. 2650 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2651 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2652 * @{ 2653 */ 2654 2655 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 2656 2657 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 2658 2659 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 2660 2661 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 2662 2663 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 2664 2665 #if defined(SPI4) 2666 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U) 2667 #endif /* SPI4 */ 2668 2669 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 2670 2671 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 2672 2673 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 2674 2675 #if defined(TIM20) 2676 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U) 2677 #endif /* TIM20 */ 2678 2679 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 2680 2681 #if defined(HRTIM1) 2682 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U) 2683 #endif /* HRTIM1 */ 2684 2685 2686 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 2687 2688 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 2689 2690 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 2691 2692 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 2693 2694 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 2695 2696 #if defined(SPI4) 2697 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U) 2698 #endif /* SPI4 */ 2699 2700 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 2701 2702 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 2703 2704 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 2705 2706 #if defined(TIM20) 2707 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U) 2708 #endif /* TIM20 */ 2709 2710 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 2711 2712 #if defined(HRTIM1) 2713 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U) 2714 #endif /* HRTIM1 */ 2715 2716 2717 /** 2718 * @} 2719 */ 2720 2721 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2722 * @{ 2723 */ 2724 2725 /** @brief Macros to force or release the Backup domain reset. 2726 * @note This function resets the RTC peripheral (including the backup registers) 2727 * and the RTC clock source selection in RCC_CSR register. 2728 * @note The BKPSRAM is not affected by this reset. 2729 * @retval None 2730 */ 2731 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2732 2733 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2734 2735 /** 2736 * @} 2737 */ 2738 2739 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2740 * @{ 2741 */ 2742 2743 /** @brief Macros to enable or disable the RTC clock. 2744 * @note As the RTC is in the Backup domain and write access is denied to 2745 * this domain after reset, you have to enable write access using 2746 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2747 * (to be done once after reset). 2748 * @note These macros must be used after the RTC clock source was selected. 2749 * @retval None 2750 */ 2751 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2752 2753 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2754 2755 /** 2756 * @} 2757 */ 2758 2759 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 2760 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2761 * It is used (enabled by hardware) as system clock source after startup 2762 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2763 * of the HSE used directly or indirectly as system clock (if the Clock 2764 * Security System CSS is enabled). 2765 * @note HSI can not be stopped if it is used as system clock source. In this case, 2766 * you have to select another source of the system clock then stop the HSI. 2767 * @note After enabling the HSI, the application software should wait on HSIRDY 2768 * flag to be set indicating that HSI clock is stable and can be used as 2769 * system clock source. 2770 * This parameter can be: ENABLE or DISABLE. 2771 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2772 * clock cycles. 2773 * @retval None 2774 */ 2775 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 2776 2777 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 2778 2779 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 2780 * @note The calibration is used to compensate for the variations in voltage 2781 * and temperature that influence the frequency of the internal HSI RC. 2782 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2783 * (default is RCC_HSICALIBRATION_DEFAULT). 2784 * This parameter must be a number between 0 and 0x7F. 2785 * @retval None 2786 */ 2787 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2788 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 2789 2790 /** 2791 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2792 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2793 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2794 * speed because of the HSI startup time. 2795 * @note The enable of this function has not effect on the HSION bit. 2796 * This parameter can be: ENABLE or DISABLE. 2797 * @retval None 2798 */ 2799 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 2800 2801 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 2802 2803 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2804 * @note After enabling the LSI, the application software should wait on 2805 * LSIRDY flag to be set indicating that LSI clock is stable and can 2806 * be used to clock the IWDG and/or the RTC. 2807 * @note LSI can not be disabled if the IWDG is running. 2808 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2809 * clock cycles. 2810 * @retval None 2811 */ 2812 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 2813 2814 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 2815 2816 /** 2817 * @brief Macro to configure the External High Speed oscillator (HSE). 2818 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2819 * supported by this macro. User should request a transition to HSE Off 2820 * first and then HSE On or HSE Bypass. 2821 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2822 * software should wait on HSERDY flag to be set indicating that HSE clock 2823 * is stable and can be used to clock the PLL and/or system clock. 2824 * @note HSE state can not be changed if it is used directly or through the 2825 * PLL as system clock. In this case, you have to select another source 2826 * of the system clock then change the HSE state (ex. disable it). 2827 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2828 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2829 * was previously enabled you have to enable it again after calling this 2830 * function. 2831 * @param __STATE__ specifies the new state of the HSE. 2832 * This parameter can be one of the following values: 2833 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2834 * 6 HSE oscillator clock cycles. 2835 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2836 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2837 * @retval None 2838 */ 2839 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2840 do { \ 2841 if((__STATE__) == RCC_HSE_ON) \ 2842 { \ 2843 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2844 } \ 2845 else if((__STATE__) == RCC_HSE_BYPASS) \ 2846 { \ 2847 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2848 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2849 } \ 2850 else \ 2851 { \ 2852 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 2853 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2854 } \ 2855 } while(0) 2856 2857 /** 2858 * @brief Macro to configure the External Low Speed oscillator (LSE). 2859 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2860 * supported by this macro. User should request a transition to LSE Off 2861 * first and then LSE On or LSE Bypass. 2862 * @note As the LSE is in the Backup domain and write access is denied to 2863 * this domain after reset, you have to enable write access using 2864 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2865 * (to be done once after reset). 2866 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2867 * software should wait on LSERDY flag to be set indicating that LSE clock 2868 * is stable and can be used to clock the RTC. 2869 * @param __STATE__ specifies the new state of the LSE. 2870 * This parameter can be one of the following values: 2871 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2872 * 6 LSE oscillator clock cycles. 2873 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2874 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2875 * @retval None 2876 */ 2877 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2878 do { \ 2879 if((__STATE__) == RCC_LSE_ON) \ 2880 { \ 2881 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2882 } \ 2883 else if((__STATE__) == RCC_LSE_BYPASS) \ 2884 { \ 2885 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2886 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2887 } \ 2888 else \ 2889 { \ 2890 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2891 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2892 } \ 2893 } while(0) 2894 2895 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2896 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2897 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2898 * flag to be set indicating that HSI48 clock is stable. 2899 * This parameter can be: ENABLE or DISABLE. 2900 * @retval None 2901 */ 2902 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2903 2904 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2905 2906 /** @brief Macros to configure the RTC clock (RTCCLK). 2907 * @note As the RTC clock configuration bits are in the Backup domain and write 2908 * access is denied to this domain after reset, you have to enable write 2909 * access using the Power Backup Access macro before to configure 2910 * the RTC clock source (to be done once after reset). 2911 * @note Once the RTC clock is configured it cannot be changed unless the 2912 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2913 * a Power On Reset (POR). 2914 * 2915 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2916 * This parameter can be one of the following values: 2917 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2918 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2919 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2920 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2921 * 2922 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2923 * work in STOP and STANDBY modes, and can be used as wakeup source. 2924 * However, when the HSE clock is used as RTC clock source, the RTC 2925 * cannot be used in STOP and STANDBY modes. 2926 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2927 * RTC clock source). 2928 * @retval None 2929 */ 2930 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 2931 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 2932 2933 2934 /** @brief Macro to get the RTC clock source. 2935 * @retval The returned value can be one of the following: 2936 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2937 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2938 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2939 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2940 */ 2941 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 2942 2943 /** @brief Macros to enable or disable the main PLL. 2944 * @note After enabling the main PLL, the application software should wait on 2945 * PLLRDY flag to be set indicating that PLL clock is stable and can 2946 * be used as system clock source. 2947 * @note The main PLL can not be disabled if it is used as system clock source 2948 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 2949 * @retval None 2950 */ 2951 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 2952 2953 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 2954 2955 /** @brief Macro to configure the PLL clock source. 2956 * @note This function must be used only when the main PLL is disabled. 2957 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2958 * This parameter can be one of the following values: 2959 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2960 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2961 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2962 * @retval None 2963 * 2964 */ 2965 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 2966 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 2967 2968 /** @brief Macro to configure the PLL source division factor M. 2969 * @note This function must be used only when the main PLL is disabled. 2970 * @param __PLLM__ specifies the division factor for PLL VCO input clock 2971 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 2972 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2973 * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency 2974 * of 8 MHz to limit PLL jitter. 2975 * @retval None 2976 * 2977 */ 2978 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 2979 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) 2980 2981 /** 2982 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 2983 * @note This macro must be used only when the main PLL is disabled. 2984 * @note This macro preserves the PLL's output clocks enable state. 2985 * 2986 * @param __PLLSOURCE__ specifies the PLL entry clock source. 2987 * This parameter can be one of the following values: 2988 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 2989 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 2990 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 2991 * 2992 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 2993 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider 2994 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 2995 * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency 2996 * of 8 MHz to limit PLL jitter. 2997 * 2998 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 2999 * This parameter must be a number between 8 and 127. 3000 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3001 * output frequency is between 64 and 344 MHz. 3002 * 3003 * @param __PLLP__ specifies the division factor for SAI clock. 3004 * This parameter must be a number in the range (2 to 31). 3005 * 3006 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 3007 * This parameter must be in the range (2, 4, 6 or 8). 3008 * @note If the USB OTG FS is used in your application, you have to set the 3009 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 3010 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 3011 * correctly. 3012 * @param __PLLR__ specifies the division factor for the main system clock. 3013 * @note You have to set the PLLR parameter correctly to not exceed 170MHZ. 3014 * This parameter must be in the range (2, 4, 6 or 8). 3015 * @retval None 3016 */ 3017 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 3018 MODIFY_REG(RCC->PLLCFGR, \ 3019 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 3020 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ 3021 ((__PLLSOURCE__) | \ 3022 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 3023 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 3024 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 3025 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 3026 ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 3027 3028 /** @brief Macro to get the oscillator used as PLL clock source. 3029 * @retval The oscillator used as PLL clock source. The returned value can be one 3030 * of the following: 3031 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 3032 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 3033 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 3034 */ 3035 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) 3036 3037 /** 3038 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK) 3039 * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime 3040 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 3041 * be stopped if used as System Clock. 3042 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 3043 * This parameter can be one or a combination of the following values: 3044 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. 3045 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), 3046 * FDCAN (<=48 MHz) and QSPI (<=48 MHz). 3047 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) 3048 * @retval None 3049 */ 3050 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3051 3052 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3053 3054 /** 3055 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 3056 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 3057 * This parameter can be one of the following values: 3058 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. 3059 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), 3060 * FDCAN (<=48 MHz) and QSPI (<=48 MHz). 3061 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) 3062 * @retval SET / RESET 3063 */ 3064 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3065 3066 /** 3067 * @brief Macro to configure the system clock source. 3068 * @param __SYSCLKSOURCE__ specifies the system clock source. 3069 * This parameter can be one of the following values: 3070 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 3071 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 3072 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 3073 * @retval None 3074 */ 3075 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 3076 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 3077 3078 /** @brief Macro to get the clock source used as system clock. 3079 * @retval The clock source used as system clock. The returned value can be one 3080 * of the following: 3081 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 3082 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 3083 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 3084 */ 3085 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) 3086 3087 /** 3088 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3089 * @note As the LSE is in the Backup domain and write access is denied to 3090 * this domain after reset, you have to enable write access using 3091 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3092 * (to be done once after reset). 3093 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 3094 * This parameter can be one of the following values: 3095 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3096 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3097 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3098 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3099 * @retval None 3100 */ 3101 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3102 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) 3103 3104 /** @brief Macro to configure the MCO clock. 3105 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3106 * This parameter can be one of the following values: 3107 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3108 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3109 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3110 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3111 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3112 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 3113 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3114 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 3115 * @param __MCODIV__ specifies the MCO clock prescaler. 3116 * This parameter can be one of the following values: 3117 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3118 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3119 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3120 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3121 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3122 */ 3123 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 3124 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 3125 3126 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3127 * @brief macros to manage the specified RCC Flags and interrupts. 3128 * @{ 3129 */ 3130 3131 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 3132 * the selected interrupts). 3133 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3134 * This parameter can be any combination of the following values: 3135 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3136 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3137 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3138 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3139 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3140 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 3141 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3142 * @retval None 3143 */ 3144 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3145 3146 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 3147 * the selected interrupts). 3148 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3149 * This parameter can be any combination of the following values: 3150 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3151 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3152 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3153 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3154 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3155 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 3156 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3157 * @retval None 3158 */ 3159 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3160 3161 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 3162 * bits to clear the selected interrupt pending bits. 3163 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3164 * This parameter can be any combination of the following values: 3165 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3166 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3167 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3168 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3169 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3170 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3171 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 3172 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3173 * @retval None 3174 */ 3175 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 3176 3177 /** @brief Check whether the RCC interrupt has occurred or not. 3178 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3179 * This parameter can be one of the following values: 3180 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3181 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3182 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3183 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3184 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3185 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3186 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 3187 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 3188 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 3189 */ 3190 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 3191 3192 /** @brief Set RMVF bit to clear the reset flags. 3193 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3194 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3195 * @retval None 3196 */ 3197 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 3198 3199 /** @brief Check whether the selected RCC flag is set or not. 3200 * @param __FLAG__ specifies the flag to check. 3201 * This parameter can be one of the following values: 3202 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3203 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3204 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3205 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 3206 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3207 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3208 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3209 * @arg @ref RCC_FLAG_BORRST BOR reset 3210 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3211 * @arg @ref RCC_FLAG_PINRST Pin reset 3212 * @arg @ref RCC_FLAG_SFTRST Software reset 3213 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3214 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3215 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3216 * @retval The new state of __FLAG__ (TRUE or FALSE). 3217 */ 3218 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 3219 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 3220 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 3221 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 3222 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ 3223 ? 1U : 0U) 3224 3225 /** 3226 * @} 3227 */ 3228 3229 /** 3230 * @} 3231 */ 3232 3233 /* Private constants ---------------------------------------------------------*/ 3234 /** @addtogroup RCC_Private_Constants 3235 * @{ 3236 */ 3237 /* Defines used for Flags */ 3238 #define CR_REG_INDEX 1U 3239 #define BDCR_REG_INDEX 2U 3240 #define CSR_REG_INDEX 3U 3241 #define CRRCR_REG_INDEX 4U 3242 3243 #define RCC_FLAG_MASK 0x1FU 3244 3245 /* Define used for IS_RCC_CLOCKTYPE() */ 3246 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */ 3247 3248 /** 3249 * @} 3250 */ 3251 3252 /* Private macros ------------------------------------------------------------*/ 3253 /** @addtogroup RCC_Private_Macros 3254 * @{ 3255 */ 3256 3257 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 3258 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 3259 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 3260 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 3261 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 3262 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 3263 3264 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 3265 ((__HSE__) == RCC_HSE_BYPASS)) 3266 3267 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 3268 ((__LSE__) == RCC_LSE_BYPASS)) 3269 3270 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 3271 3272 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 3273 3274 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 3275 3276 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 3277 3278 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 3279 ((__PLL__) == RCC_PLL_ON)) 3280 3281 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 3282 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 3283 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 3284 3285 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 3286 3287 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) 3288 3289 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 3290 3291 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3292 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3293 3294 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3295 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3296 3297 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) 3298 3299 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 3300 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 3301 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 3302 3303 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 3304 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 3305 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 3306 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 3307 ((__HCLK__) == RCC_SYSCLK_DIV512)) 3308 3309 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 3310 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 3311 ((__PCLK__) == RCC_HCLK_DIV16)) 3312 3313 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 3314 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 3315 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 3316 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 3317 3318 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \ 3319 ((__MCOX__) == RCC_MCO_PG10)) 3320 3321 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 3322 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 3323 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 3324 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 3325 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 3326 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 3327 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 3328 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 3329 3330 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 3331 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 3332 ((__DIV__) == RCC_MCODIV_16)) 3333 3334 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 3335 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 3336 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 3337 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 3338 3339 /** 3340 * @} 3341 */ 3342 3343 /* Include RCC HAL Extended module */ 3344 #include "stm32g4xx_hal_rcc_ex.h" 3345 3346 /* Exported functions --------------------------------------------------------*/ 3347 /** @addtogroup RCC_Exported_Functions 3348 * @{ 3349 */ 3350 3351 3352 /** @addtogroup RCC_Exported_Functions_Group1 3353 * @{ 3354 */ 3355 3356 /* Initialization and de-initialization functions ******************************/ 3357 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3358 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3359 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3360 3361 /** 3362 * @} 3363 */ 3364 3365 /** @addtogroup RCC_Exported_Functions_Group2 3366 * @{ 3367 */ 3368 3369 /* Peripheral Control functions ************************************************/ 3370 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3371 void HAL_RCC_EnableCSS(void); 3372 void HAL_RCC_EnableLSECSS(void); 3373 void HAL_RCC_DisableLSECSS(void); 3374 uint32_t HAL_RCC_GetSysClockFreq(void); 3375 uint32_t HAL_RCC_GetHCLKFreq(void); 3376 uint32_t HAL_RCC_GetPCLK1Freq(void); 3377 uint32_t HAL_RCC_GetPCLK2Freq(void); 3378 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3379 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3380 /* CSS NMI IRQ handler */ 3381 void HAL_RCC_NMI_IRQHandler(void); 3382 /* User Callbacks in non blocking mode (IT mode) */ 3383 void HAL_RCC_CSSCallback(void); 3384 3385 /** 3386 * @} 3387 */ 3388 3389 /** 3390 * @} 3391 */ 3392 3393 /** 3394 * @} 3395 */ 3396 3397 /** 3398 * @} 3399 */ 3400 3401 #ifdef __cplusplus 3402 } 3403 #endif 3404 3405 #endif /* STM32G4xx_HAL_RCC_H */ 3406 3407
