1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F4xx_HAL_RCC_H 20 #define __STM32F4xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f4xx_hal_def.h" 28 29 /* Include RCC HAL Extended module */ 30 /* (include on top of file since RCC structures are defined in extended file) */ 31 #include "stm32f4xx_hal_rcc_ex.h" 32 33 /** @addtogroup STM32F4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup RCC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup RCC_Exported_Types RCC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t OscillatorType; /*!< The oscillators to be configured. 52 This parameter can be a value of @ref RCC_Oscillator_Type */ 53 54 uint32_t HSEState; /*!< The new state of the HSE. 55 This parameter can be a value of @ref RCC_HSE_Config */ 56 57 uint32_t LSEState; /*!< The new state of the LSE. 58 This parameter can be a value of @ref RCC_LSE_Config */ 59 60 uint32_t HSIState; /*!< The new state of the HSI. 61 This parameter can be a value of @ref RCC_HSI_Config */ 62 63 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 64 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 65 66 uint32_t LSIState; /*!< The new state of the LSI. 67 This parameter can be a value of @ref RCC_LSI_Config */ 68 69 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 70 }RCC_OscInitTypeDef; 71 72 /** 73 * @brief RCC System, AHB and APB busses clock configuration structure definition 74 */ 75 typedef struct 76 { 77 uint32_t ClockType; /*!< The clock to be configured. 78 This parameter can be a value of @ref RCC_System_Clock_Type */ 79 80 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 81 This parameter can be a value of @ref RCC_System_Clock_Source */ 82 83 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 84 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 85 86 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 87 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 88 89 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 90 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 91 92 }RCC_ClkInitTypeDef; 93 94 /** 95 * @} 96 */ 97 98 /* Exported constants --------------------------------------------------------*/ 99 /** @defgroup RCC_Exported_Constants RCC Exported Constants 100 * @{ 101 */ 102 103 /** @defgroup RCC_Oscillator_Type Oscillator Type 104 * @{ 105 */ 106 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 107 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 108 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 109 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 110 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 111 /** 112 * @} 113 */ 114 115 /** @defgroup RCC_HSE_Config HSE Config 116 * @{ 117 */ 118 #define RCC_HSE_OFF 0x00000000U 119 #define RCC_HSE_ON RCC_CR_HSEON 120 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) 121 /** 122 * @} 123 */ 124 125 /** @defgroup RCC_LSE_Config LSE Config 126 * @{ 127 */ 128 #define RCC_LSE_OFF 0x00000000U 129 #define RCC_LSE_ON RCC_BDCR_LSEON 130 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) 131 /** 132 * @} 133 */ 134 135 /** @defgroup RCC_HSI_Config HSI Config 136 * @{ 137 */ 138 #define RCC_HSI_OFF ((uint8_t)0x00) 139 #define RCC_HSI_ON ((uint8_t)0x01) 140 141 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 142 /** 143 * @} 144 */ 145 146 /** @defgroup RCC_LSI_Config LSI Config 147 * @{ 148 */ 149 #define RCC_LSI_OFF ((uint8_t)0x00) 150 #define RCC_LSI_ON ((uint8_t)0x01) 151 /** 152 * @} 153 */ 154 155 /** @defgroup RCC_PLL_Config PLL Config 156 * @{ 157 */ 158 #define RCC_PLL_NONE ((uint8_t)0x00) 159 #define RCC_PLL_OFF ((uint8_t)0x01) 160 #define RCC_PLL_ON ((uint8_t)0x02) 161 /** 162 * @} 163 */ 164 165 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 166 * @{ 167 */ 168 #define RCC_PLLP_DIV2 0x00000002U 169 #define RCC_PLLP_DIV4 0x00000004U 170 #define RCC_PLLP_DIV6 0x00000006U 171 #define RCC_PLLP_DIV8 0x00000008U 172 /** 173 * @} 174 */ 175 176 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 177 * @{ 178 */ 179 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI 180 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE 181 /** 182 * @} 183 */ 184 185 /** @defgroup RCC_System_Clock_Type System Clock Type 186 * @{ 187 */ 188 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U 189 #define RCC_CLOCKTYPE_HCLK 0x00000002U 190 #define RCC_CLOCKTYPE_PCLK1 0x00000004U 191 #define RCC_CLOCKTYPE_PCLK2 0x00000008U 192 /** 193 * @} 194 */ 195 196 /** @defgroup RCC_System_Clock_Source System Clock Source 197 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for 198 * STM32F446xx devices. 199 * @{ 200 */ 201 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI 202 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE 203 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL 204 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) 205 /** 206 * @} 207 */ 208 209 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 210 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for 211 * STM32F446xx devices. 212 * @{ 213 */ 214 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 215 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 216 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 217 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ 218 /** 219 * @} 220 */ 221 222 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 223 * @{ 224 */ 225 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 226 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 227 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 228 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 229 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 230 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 231 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 232 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 233 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source 239 * @{ 240 */ 241 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 242 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 243 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 244 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 245 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 251 * @{ 252 */ 253 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U 254 #define RCC_RTCCLKSOURCE_LSE 0x00000100U 255 #define RCC_RTCCLKSOURCE_LSI 0x00000200U 256 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U 257 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U 258 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U 259 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U 260 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U 261 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U 262 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U 263 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U 264 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U 265 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U 266 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U 267 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U 268 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U 269 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U 270 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U 271 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U 272 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U 273 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U 274 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U 275 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U 276 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U 277 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U 278 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U 279 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U 280 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U 281 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U 282 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U 283 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U 284 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U 285 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U 286 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U 287 /** 288 * @} 289 */ 290 291 /** @defgroup RCC_MCO_Index MCO Index 292 * @{ 293 */ 294 #define RCC_MCO1 0x00000000U 295 #define RCC_MCO2 0x00000001U 296 /** 297 * @} 298 */ 299 300 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 301 * @{ 302 */ 303 #define RCC_MCO1SOURCE_HSI 0x00000000U 304 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 305 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 306 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 307 /** 308 * @} 309 */ 310 311 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 312 * @{ 313 */ 314 #define RCC_MCODIV_1 0x00000000U 315 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 316 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) 317 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) 318 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE 319 /** 320 * @} 321 */ 322 323 /** @defgroup RCC_Interrupt Interrupts 324 * @{ 325 */ 326 #define RCC_IT_LSIRDY ((uint8_t)0x01) 327 #define RCC_IT_LSERDY ((uint8_t)0x02) 328 #define RCC_IT_HSIRDY ((uint8_t)0x04) 329 #define RCC_IT_HSERDY ((uint8_t)0x08) 330 #define RCC_IT_PLLRDY ((uint8_t)0x10) 331 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 332 #define RCC_IT_CSS ((uint8_t)0x80) 333 /** 334 * @} 335 */ 336 337 /** @defgroup RCC_Flag Flags 338 * Elements values convention: 0XXYYYYYb 339 * - YYYYY : Flag position in the register 340 * - 0XX : Register index 341 * - 01: CR register 342 * - 10: BDCR register 343 * - 11: CSR register 344 * @{ 345 */ 346 /* Flags in the CR register */ 347 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 348 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 349 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 350 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 351 352 /* Flags in the BDCR register */ 353 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 354 355 /* Flags in the CSR register */ 356 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 357 #define RCC_FLAG_BORRST ((uint8_t)0x79) 358 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 359 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 360 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 361 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 362 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 363 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 364 /** 365 * @} 366 */ 367 368 /** 369 * @} 370 */ 371 372 /* Exported macro ------------------------------------------------------------*/ 373 /** @defgroup RCC_Exported_Macros RCC Exported Macros 374 * @{ 375 */ 376 377 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 378 * @brief Enable or disable the AHB1 peripheral clock. 379 * @note After reset, the peripheral clock (used for registers read/write access) 380 * is disabled and the application software has to enable this clock before 381 * using it. 382 * @{ 383 */ 384 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 385 __IO uint32_t tmpreg = 0x00U; \ 386 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 387 /* Delay after an RCC peripheral clock enabling */ \ 388 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ 389 UNUSED(tmpreg); \ 390 } while(0U) 391 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 392 __IO uint32_t tmpreg = 0x00U; \ 393 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 394 /* Delay after an RCC peripheral clock enabling */ \ 395 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ 396 UNUSED(tmpreg); \ 397 } while(0U) 398 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 399 __IO uint32_t tmpreg = 0x00U; \ 400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 401 /* Delay after an RCC peripheral clock enabling */ \ 402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ 403 UNUSED(tmpreg); \ 404 } while(0U) 405 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 406 __IO uint32_t tmpreg = 0x00U; \ 407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 408 /* Delay after an RCC peripheral clock enabling */ \ 409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ 410 UNUSED(tmpreg); \ 411 } while(0U) 412 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 413 __IO uint32_t tmpreg = 0x00U; \ 414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 415 /* Delay after an RCC peripheral clock enabling */ \ 416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ 417 UNUSED(tmpreg); \ 418 } while(0U) 419 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 420 __IO uint32_t tmpreg = 0x00U; \ 421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 422 /* Delay after an RCC peripheral clock enabling */ \ 423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ 424 UNUSED(tmpreg); \ 425 } while(0U) 426 427 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) 428 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) 429 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) 430 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) 431 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) 432 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) 433 /** 434 * @} 435 */ 436 437 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 438 * @brief Get the enable or disable status of the AHB1 peripheral clock. 439 * @note After reset, the peripheral clock (used for registers read/write access) 440 * is disabled and the application software has to enable this clock before 441 * using it. 442 * @{ 443 */ 444 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) 445 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) 446 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) 447 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) 448 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) 449 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) 450 451 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) 452 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) 453 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) 454 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) 455 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) 456 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) 457 /** 458 * @} 459 */ 460 461 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 462 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 463 * @note After reset, the peripheral clock (used for registers read/write access) 464 * is disabled and the application software has to enable this clock before 465 * using it. 466 * @{ 467 */ 468 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 469 __IO uint32_t tmpreg = 0x00U; \ 470 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 471 /* Delay after an RCC peripheral clock enabling */ \ 472 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 473 UNUSED(tmpreg); \ 474 } while(0U) 475 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 476 __IO uint32_t tmpreg = 0x00U; \ 477 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 478 /* Delay after an RCC peripheral clock enabling */ \ 479 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 480 UNUSED(tmpreg); \ 481 } while(0U) 482 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 483 __IO uint32_t tmpreg = 0x00U; \ 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 485 /* Delay after an RCC peripheral clock enabling */ \ 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 487 UNUSED(tmpreg); \ 488 } while(0U) 489 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 490 __IO uint32_t tmpreg = 0x00U; \ 491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 492 /* Delay after an RCC peripheral clock enabling */ \ 493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 494 UNUSED(tmpreg); \ 495 } while(0U) 496 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 497 __IO uint32_t tmpreg = 0x00U; \ 498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 499 /* Delay after an RCC peripheral clock enabling */ \ 500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 501 UNUSED(tmpreg); \ 502 } while(0U) 503 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 504 __IO uint32_t tmpreg = 0x00U; \ 505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 506 /* Delay after an RCC peripheral clock enabling */ \ 507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 508 UNUSED(tmpreg); \ 509 } while(0U) 510 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 511 __IO uint32_t tmpreg = 0x00U; \ 512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 513 /* Delay after an RCC peripheral clock enabling */ \ 514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 515 UNUSED(tmpreg); \ 516 } while(0U) 517 518 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 519 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 520 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 521 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 522 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 523 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 524 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 530 * @brief Get the enable or disable status of the APB1 peripheral clock. 531 * @note After reset, the peripheral clock (used for registers read/write access) 532 * is disabled and the application software has to enable this clock before 533 * using it. 534 * @{ 535 */ 536 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 537 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 538 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 539 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 540 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 541 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 542 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 543 544 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 545 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 546 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 547 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 548 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 549 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 550 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 551 /** 552 * @} 553 */ 554 555 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 556 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 557 * @note After reset, the peripheral clock (used for registers read/write access) 558 * is disabled and the application software has to enable this clock before 559 * using it. 560 * @{ 561 */ 562 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 563 __IO uint32_t tmpreg = 0x00U; \ 564 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 565 /* Delay after an RCC peripheral clock enabling */ \ 566 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 567 UNUSED(tmpreg); \ 568 } while(0U) 569 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 570 __IO uint32_t tmpreg = 0x00U; \ 571 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 572 /* Delay after an RCC peripheral clock enabling */ \ 573 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 574 UNUSED(tmpreg); \ 575 } while(0U) 576 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 577 __IO uint32_t tmpreg = 0x00U; \ 578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 579 /* Delay after an RCC peripheral clock enabling */ \ 580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ 581 UNUSED(tmpreg); \ 582 } while(0U) 583 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 584 __IO uint32_t tmpreg = 0x00U; \ 585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 586 /* Delay after an RCC peripheral clock enabling */ \ 587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 588 UNUSED(tmpreg); \ 589 } while(0U) 590 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 591 __IO uint32_t tmpreg = 0x00U; \ 592 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 593 /* Delay after an RCC peripheral clock enabling */ \ 594 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 595 UNUSED(tmpreg); \ 596 } while(0U) 597 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 598 __IO uint32_t tmpreg = 0x00U; \ 599 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 600 /* Delay after an RCC peripheral clock enabling */ \ 601 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ 602 UNUSED(tmpreg); \ 603 } while(0U) 604 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 605 __IO uint32_t tmpreg = 0x00U; \ 606 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 607 /* Delay after an RCC peripheral clock enabling */ \ 608 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 609 UNUSED(tmpreg); \ 610 } while(0U) 611 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 612 __IO uint32_t tmpreg = 0x00U; \ 613 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 614 /* Delay after an RCC peripheral clock enabling */ \ 615 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 616 UNUSED(tmpreg); \ 617 } while(0U) 618 619 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 620 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 621 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) 622 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 623 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 624 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) 625 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 626 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 627 /** 628 * @} 629 */ 630 631 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 632 * @brief Get the enable or disable status of the APB2 peripheral clock. 633 * @note After reset, the peripheral clock (used for registers read/write access) 634 * is disabled and the application software has to enable this clock before 635 * using it. 636 * @{ 637 */ 638 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 639 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 640 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) 641 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 642 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 643 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) 644 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 645 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 646 647 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 648 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 649 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) 650 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 651 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 652 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) 653 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 654 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 655 /** 656 * @} 657 */ 658 659 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset 660 * @brief Force or release AHB1 peripheral reset. 661 * @{ 662 */ 663 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) 664 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) 665 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) 666 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) 667 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) 668 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) 669 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) 670 671 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) 672 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) 673 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) 674 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) 675 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) 676 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) 677 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) 678 /** 679 * @} 680 */ 681 682 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 683 * @brief Force or release APB1 peripheral reset. 684 * @{ 685 */ 686 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 687 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 688 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 689 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 690 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 691 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 692 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 693 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 694 695 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) 696 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 697 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 698 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 699 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 700 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 701 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 702 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 703 /** 704 * @} 705 */ 706 707 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 708 * @brief Force or release APB2 peripheral reset. 709 * @{ 710 */ 711 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 712 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 713 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 714 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) 715 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) 716 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 717 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) 718 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 719 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 720 721 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) 722 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 723 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 724 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) 725 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) 726 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 727 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) 728 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 729 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 730 /** 731 * @} 732 */ 733 734 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 735 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 736 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 737 * power consumption. 738 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 739 * @note By default, all peripheral clocks are enabled during SLEEP mode. 740 * @{ 741 */ 742 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) 743 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) 744 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) 745 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) 746 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) 747 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) 748 749 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) 750 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) 751 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) 752 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) 753 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) 754 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) 755 /** 756 * @} 757 */ 758 759 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 760 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 761 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 762 * power consumption. 763 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 764 * @note By default, all peripheral clocks are enabled during SLEEP mode. 765 * @{ 766 */ 767 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) 768 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) 769 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) 770 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) 771 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) 772 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) 773 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) 774 775 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) 776 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) 777 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) 778 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) 779 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) 780 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) 781 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) 782 /** 783 * @} 784 */ 785 786 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 787 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 788 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 789 * power consumption. 790 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. 791 * @note By default, all peripheral clocks are enabled during SLEEP mode. 792 * @{ 793 */ 794 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) 795 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) 796 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) 797 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) 798 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) 799 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) 800 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) 801 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) 802 803 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) 804 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) 805 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) 806 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) 807 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) 808 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) 809 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) 810 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) 811 /** 812 * @} 813 */ 814 815 /** @defgroup RCC_HSI_Configuration HSI Configuration 816 * @{ 817 */ 818 819 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 820 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 821 * It is used (enabled by hardware) as system clock source after startup 822 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure 823 * of the HSE used directly or indirectly as system clock (if the Clock 824 * Security System CSS is enabled). 825 * @note HSI can not be stopped if it is used as system clock source. In this case, 826 * you have to select another source of the system clock then stop the HSI. 827 * @note After enabling the HSI, the application software should wait on HSIRDY 828 * flag to be set indicating that HSI clock is stable and can be used as 829 * system clock source. 830 * This parameter can be: ENABLE or DISABLE. 831 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 832 * clock cycles. 833 */ 834 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 835 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 836 837 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 838 * @note The calibration is used to compensate for the variations in voltage 839 * and temperature that influence the frequency of the internal HSI RC. 840 * @param __HSICalibrationValue__ specifies the calibration trimming value. 841 * (default is RCC_HSICALIBRATION_DEFAULT). 842 * This parameter must be a number between 0 and 0x1F. 843 */ 844 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ 845 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) 846 /** 847 * @} 848 */ 849 850 /** @defgroup RCC_LSI_Configuration LSI Configuration 851 * @{ 852 */ 853 854 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 855 * @note After enabling the LSI, the application software should wait on 856 * LSIRDY flag to be set indicating that LSI clock is stable and can 857 * be used to clock the IWDG and/or the RTC. 858 * @note LSI can not be disabled if the IWDG is running. 859 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 860 * clock cycles. 861 */ 862 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 863 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 864 /** 865 * @} 866 */ 867 868 /** @defgroup RCC_HSE_Configuration HSE Configuration 869 * @{ 870 */ 871 872 /** 873 * @brief Macro to configure the External High Speed oscillator (HSE). 874 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 875 * User should request a transition to HSE Off first and then HSE On or HSE Bypass. 876 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 877 * software should wait on HSERDY flag to be set indicating that HSE clock 878 * is stable and can be used to clock the PLL and/or system clock. 879 * @note HSE state can not be changed if it is used directly or through the 880 * PLL as system clock. In this case, you have to select another source 881 * of the system clock then change the HSE state (ex. disable it). 882 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 883 * @note This function reset the CSSON bit, so if the clock security system(CSS) 884 * was previously enabled you have to enable it again after calling this 885 * function. 886 * @param __STATE__ specifies the new state of the HSE. 887 * This parameter can be one of the following values: 888 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 889 * 6 HSE oscillator clock cycles. 890 * @arg RCC_HSE_ON: turn ON the HSE oscillator. 891 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. 892 */ 893 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 894 do { \ 895 if ((__STATE__) == RCC_HSE_ON) \ 896 { \ 897 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 898 } \ 899 else if ((__STATE__) == RCC_HSE_BYPASS) \ 900 { \ 901 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 902 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 903 } \ 904 else \ 905 { \ 906 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 907 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 908 } \ 909 } while(0U) 910 /** 911 * @} 912 */ 913 914 /** @defgroup RCC_LSE_Configuration LSE Configuration 915 * @{ 916 */ 917 918 /** 919 * @brief Macro to configure the External Low Speed oscillator (LSE). 920 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 921 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 922 * @note As the LSE is in the Backup domain and write access is denied to 923 * this domain after reset, you have to enable write access using 924 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 925 * (to be done once after reset). 926 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 927 * software should wait on LSERDY flag to be set indicating that LSE clock 928 * is stable and can be used to clock the RTC. 929 * @param __STATE__ specifies the new state of the LSE. 930 * This parameter can be one of the following values: 931 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 932 * 6 LSE oscillator clock cycles. 933 * @arg RCC_LSE_ON: turn ON the LSE oscillator. 934 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. 935 */ 936 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 937 do { \ 938 if((__STATE__) == RCC_LSE_ON) \ 939 { \ 940 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 941 } \ 942 else if((__STATE__) == RCC_LSE_BYPASS) \ 943 { \ 944 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 945 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 946 } \ 947 else \ 948 { \ 949 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 950 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 951 } \ 952 } while(0U) 953 /** 954 * @} 955 */ 956 957 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration 958 * @{ 959 */ 960 961 /** @brief Macros to enable or disable the RTC clock. 962 * @note These macros must be used only after the RTC clock source was selected. 963 */ 964 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 965 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 966 967 /** @brief Macros to configure the RTC clock (RTCCLK). 968 * @note As the RTC clock configuration bits are in the Backup domain and write 969 * access is denied to this domain after reset, you have to enable write 970 * access using the Power Backup Access macro before to configure 971 * the RTC clock source (to be done once after reset). 972 * @note Once the RTC clock is configured it can't be changed unless the 973 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 974 * a Power On Reset (POR). 975 * @param __RTCCLKSource__ specifies the RTC clock source. 976 * This parameter can be one of the following values: 977 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock. 978 * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock. 979 * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock. 980 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 981 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 982 * work in STOP and STANDBY modes, and can be used as wake-up source. 983 * However, when the HSE clock is used as RTC clock source, the RTC 984 * cannot be used in STOP and STANDBY modes. 985 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 986 * RTC clock source). 987 */ 988 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 989 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) 990 991 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 992 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 993 } while(0U) 994 995 /** @brief Macro to get the RTC clock source. 996 * @retval The clock source can be one of the following values: 997 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 998 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 999 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 1000 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1001 */ 1002 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 1003 1004 /** 1005 * @brief Get the RTC and HSE clock divider (RTCPRE). 1006 * @retval Returned value can be one of the following values: 1007 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() 1008 */ 1009 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) 1010 1011 /** @brief Macros to force or release the Backup domain reset. 1012 * @note This function resets the RTC peripheral (including the backup registers) 1013 * and the RTC clock source selection in RCC_CSR register. 1014 * @note The BKPSRAM is not affected by this reset. 1015 */ 1016 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 1017 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 1018 /** 1019 * @} 1020 */ 1021 1022 /** @defgroup RCC_PLL_Configuration PLL Configuration 1023 * @{ 1024 */ 1025 1026 /** @brief Macros to enable or disable the main PLL. 1027 * @note After enabling the main PLL, the application software should wait on 1028 * PLLRDY flag to be set indicating that PLL clock is stable and can 1029 * be used as system clock source. 1030 * @note The main PLL can not be disabled if it is used as system clock source 1031 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 1032 */ 1033 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 1034 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 1035 1036 /** @brief Macro to configure the PLL clock source. 1037 * @note This function must be used only when the main PLL is disabled. 1038 * @param __PLLSOURCE__ specifies the PLL entry clock source. 1039 * This parameter can be one of the following values: 1040 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 1041 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 1042 * 1043 */ 1044 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 1045 1046 /** @brief Macro to configure the PLL multiplication factor. 1047 * @note This function must be used only when the main PLL is disabled. 1048 * @param __PLLM__ specifies the division factor for PLL VCO input clock 1049 * This parameter must be a number between Min_Data = 2 and Max_Data = 63. 1050 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 1051 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency 1052 * of 2 MHz to limit PLL jitter. 1053 * 1054 */ 1055 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) 1056 /** 1057 * @} 1058 */ 1059 1060 /** @defgroup RCC_Get_Clock_source Get Clock source 1061 * @{ 1062 */ 1063 /** 1064 * @brief Macro to configure the system clock source. 1065 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. 1066 * This parameter can be one of the following values: 1067 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 1068 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 1069 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 1070 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This 1071 * parameter is available only for STM32F446xx devices. 1072 */ 1073 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) 1074 1075 /** @brief Macro to get the clock source used as system clock. 1076 * @retval The clock source used as system clock. The returned value can be one 1077 * of the following: 1078 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 1079 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 1080 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 1081 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter 1082 * is available only for STM32F446xx devices. 1083 */ 1084 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 1085 1086 /** @brief Macro to get the oscillator used as PLL clock source. 1087 * @retval The oscillator used as PLL clock source. The returned value can be one 1088 * of the following: 1089 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 1090 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 1091 */ 1092 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 1093 /** 1094 * @} 1095 */ 1096 1097 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 1098 * @{ 1099 */ 1100 1101 /** @brief Macro to configure the MCO1 clock. 1102 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1103 * This parameter can be one of the following values: 1104 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 1105 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 1106 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 1107 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source 1108 * @param __MCODIV__ specifies the MCO clock prescaler. 1109 * This parameter can be one of the following values: 1110 * @arg RCC_MCODIV_1: no division applied to MCOx clock 1111 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1112 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1113 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1114 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1115 */ 1116 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1117 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1118 1119 /** @brief Macro to configure the MCO2 clock. 1120 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1121 * This parameter can be one of the following values: 1122 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 1123 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 1124 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices 1125 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 1126 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source 1127 * @param __MCODIV__ specifies the MCO clock prescaler. 1128 * This parameter can be one of the following values: 1129 * @arg RCC_MCODIV_1: no division applied to MCOx clock 1130 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock 1131 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock 1132 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock 1133 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock 1134 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have 1135 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). 1136 */ 1137 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1138 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); 1139 /** 1140 * @} 1141 */ 1142 1143 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1144 * @brief macros to manage the specified RCC Flags and interrupts. 1145 * @{ 1146 */ 1147 1148 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 1149 * the selected interrupts). 1150 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1151 * This parameter can be any combination of the following values: 1152 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1153 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1154 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1155 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1156 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1157 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1158 */ 1159 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1160 1161 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 1162 * the selected interrupts). 1163 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1164 * This parameter can be any combination of the following values: 1165 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1166 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1167 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1168 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1169 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1170 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1171 */ 1172 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1173 1174 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 1175 * bits to clear the selected interrupt pending bits. 1176 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1177 * This parameter can be any combination of the following values: 1178 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1179 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1180 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1181 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1182 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1183 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1184 * @arg RCC_IT_CSS: Clock Security System interrupt 1185 */ 1186 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1187 1188 /** @brief Check the RCC's interrupt has occurred or not. 1189 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1190 * This parameter can be one of the following values: 1191 * @arg RCC_IT_LSIRDY: LSI ready interrupt. 1192 * @arg RCC_IT_LSERDY: LSE ready interrupt. 1193 * @arg RCC_IT_HSIRDY: HSI ready interrupt. 1194 * @arg RCC_IT_HSERDY: HSE ready interrupt. 1195 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. 1196 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. 1197 * @arg RCC_IT_CSS: Clock Security System interrupt 1198 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1199 */ 1200 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1201 1202 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 1203 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 1204 */ 1205 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 1206 1207 /** @brief Check RCC flag is set or not. 1208 * @param __FLAG__ specifies the flag to check. 1209 * This parameter can be one of the following values: 1210 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. 1211 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. 1212 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. 1213 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. 1214 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. 1215 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. 1216 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. 1217 * @arg RCC_FLAG_PINRST: Pin reset. 1218 * @arg RCC_FLAG_PORRST: POR/PDR reset. 1219 * @arg RCC_FLAG_SFTRST: Software reset. 1220 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. 1221 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. 1222 * @arg RCC_FLAG_LPWRRST: Low Power reset. 1223 * @retval The new state of __FLAG__ (TRUE or FALSE). 1224 */ 1225 #define RCC_FLAG_MASK ((uint8_t)0x1FU) 1226 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) 1227 1228 /** 1229 * @} 1230 */ 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /* Exported functions --------------------------------------------------------*/ 1237 /** @addtogroup RCC_Exported_Functions 1238 * @{ 1239 */ 1240 1241 /** @addtogroup RCC_Exported_Functions_Group1 1242 * @{ 1243 */ 1244 /* Initialization and de-initialization functions ******************************/ 1245 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1246 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1247 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1248 /** 1249 * @} 1250 */ 1251 1252 /** @addtogroup RCC_Exported_Functions_Group2 1253 * @{ 1254 */ 1255 /* Peripheral Control functions ************************************************/ 1256 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1257 void HAL_RCC_EnableCSS(void); 1258 void HAL_RCC_DisableCSS(void); 1259 uint32_t HAL_RCC_GetSysClockFreq(void); 1260 uint32_t HAL_RCC_GetHCLKFreq(void); 1261 uint32_t HAL_RCC_GetPCLK1Freq(void); 1262 uint32_t HAL_RCC_GetPCLK2Freq(void); 1263 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1264 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1265 1266 /* CSS NMI IRQ handler */ 1267 void HAL_RCC_NMI_IRQHandler(void); 1268 1269 /* User Callbacks in non blocking mode (IT mode) */ 1270 void HAL_RCC_CSSCallback(void); 1271 1272 /** 1273 * @} 1274 */ 1275 1276 /** 1277 * @} 1278 */ 1279 1280 /* Private types -------------------------------------------------------------*/ 1281 /* Private variables ---------------------------------------------------------*/ 1282 /* Private constants ---------------------------------------------------------*/ 1283 /** @defgroup RCC_Private_Constants RCC Private Constants 1284 * @{ 1285 */ 1286 1287 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion 1288 * @brief RCC registers bit address in the alias region 1289 * @{ 1290 */ 1291 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 1292 /* --- CR Register --- */ 1293 /* Alias word address of HSION bit */ 1294 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) 1295 #define RCC_HSION_BIT_NUMBER 0x00U 1296 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) 1297 /* Alias word address of CSSON bit */ 1298 #define RCC_CSSON_BIT_NUMBER 0x13U 1299 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) 1300 /* Alias word address of PLLON bit */ 1301 #define RCC_PLLON_BIT_NUMBER 0x18U 1302 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) 1303 1304 /* --- BDCR Register --- */ 1305 /* Alias word address of RTCEN bit */ 1306 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) 1307 #define RCC_RTCEN_BIT_NUMBER 0x0FU 1308 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) 1309 /* Alias word address of BDRST bit */ 1310 #define RCC_BDRST_BIT_NUMBER 0x10U 1311 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) 1312 1313 /* --- CSR Register --- */ 1314 /* Alias word address of LSION bit */ 1315 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) 1316 #define RCC_LSION_BIT_NUMBER 0x00U 1317 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) 1318 1319 /* CR register byte 3 (Bits[23:16]) base address */ 1320 #define RCC_CR_BYTE2_ADDRESS 0x40023802U 1321 1322 /* CIR register byte 2 (Bits[15:8]) base address */ 1323 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) 1324 1325 /* CIR register byte 3 (Bits[23:16]) base address */ 1326 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) 1327 1328 /* BDCR register base address */ 1329 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) 1330 1331 #define RCC_DBP_TIMEOUT_VALUE 2U 1332 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 1333 1334 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 1335 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */ 1336 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */ 1337 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ 1338 1339 /** 1340 * @} 1341 */ 1342 1343 /** 1344 * @} 1345 */ 1346 1347 /* Private macros ------------------------------------------------------------*/ 1348 /** @defgroup RCC_Private_Macros RCC Private Macros 1349 * @{ 1350 */ 1351 1352 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 1353 * @{ 1354 */ 1355 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) 1356 1357 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 1358 ((HSE) == RCC_HSE_BYPASS)) 1359 1360 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 1361 ((LSE) == RCC_LSE_BYPASS)) 1362 1363 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) 1364 1365 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) 1366 1367 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) 1368 1369 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ 1370 ((SOURCE) == RCC_PLLSOURCE_HSE)) 1371 1372 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ 1373 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ 1374 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ 1375 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) 1376 1377 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 1378 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 1379 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 1380 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 1381 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 1382 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 1383 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ 1384 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 1385 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 1386 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 1387 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ 1388 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 1389 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ 1390 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 1391 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ 1392 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 1393 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ 1394 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 1395 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ 1396 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 1397 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) 1409 1410 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) 1411 1412 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) 1413 1414 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) 1415 1416 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ 1417 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ 1418 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ 1419 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ 1420 ((HCLK) == RCC_SYSCLK_DIV512)) 1421 1422 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) 1423 1424 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ 1425 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ 1426 ((PCLK) == RCC_HCLK_DIV16)) 1427 1428 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 1429 1430 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 1431 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) 1432 1433 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 1434 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 1435 ((DIV) == RCC_MCODIV_5)) 1436 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) 1437 1438 /** 1439 * @} 1440 */ 1441 1442 /** 1443 * @} 1444 */ 1445 1446 /** 1447 * @} 1448 */ 1449 1450 /** 1451 * @} 1452 */ 1453 1454 #ifdef __cplusplus 1455 } 1456 #endif 1457 1458 #endif /* __STM32F4xx_HAL_RCC_H */ 1459 1460
