Home
last modified time | relevance | path

Searched full:pclk (Results 1 – 25 of 72) sorted by relevance

123

/Zephyr-latest/dts/bindings/display/
Dftdi,ft800.yaml15 pclk:
19 The value to divide the main clock by for PCLK. If the
20 typical main clock was 48MHz and this value is 5, the PCLK
27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
28 the rising edge. If it is set to one, PCLK polarity is on
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
38 changes a PCLK clock early and B[7:2] a PCLK clock later,
83 description: Number of PCLK cycles per visible part of horizontal line
89 Number of PCLK cycles before pixels are scanned out for
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi114 compatible = "renesas,ra-cgc-pclk-block";
124 compatible = "renesas,ra-cgc-pclk";
131 compatible = "renesas,ra-cgc-pclk";
138 compatible = "renesas,ra-cgc-pclk";
145 compatible = "renesas,ra-cgc-pclk";
152 compatible = "renesas,ra-cgc-pclk";
159 compatible = "renesas,ra-cgc-pclk";
166 compatible = "renesas,ra-cgc-pclk";
173 compatible = "renesas,ra-cgc-pclk";
186 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa8m1xh.dtsi117 compatible = "renesas,ra-cgc-pclk-block";
127 compatible = "renesas,ra-cgc-pclk";
134 compatible = "renesas,ra-cgc-pclk";
141 compatible = "renesas,ra-cgc-pclk";
148 compatible = "renesas,ra-cgc-pclk";
155 compatible = "renesas,ra-cgc-pclk";
162 compatible = "renesas,ra-cgc-pclk";
169 compatible = "renesas,ra-cgc-pclk";
176 compatible = "renesas,ra-cgc-pclk";
189 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa8d1xh.dtsi147 compatible = "renesas,ra-cgc-pclk-block";
157 compatible = "renesas,ra-cgc-pclk";
164 compatible = "renesas,ra-cgc-pclk";
171 compatible = "renesas,ra-cgc-pclk";
178 compatible = "renesas,ra-cgc-pclk";
185 compatible = "renesas,ra-cgc-pclk";
192 compatible = "renesas,ra-cgc-pclk";
199 compatible = "renesas,ra-cgc-pclk";
206 compatible = "renesas,ra-cgc-pclk";
219 compatible = "renesas,ra-cgc-pclk";
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dr7fa4e2b93cfm.dtsi134 compatible = "renesas,ra-cgc-pclk-block";
144 compatible = "renesas,ra-cgc-pclk";
151 compatible = "renesas,ra-cgc-pclk";
158 compatible = "renesas,ra-cgc-pclk";
165 compatible = "renesas,ra-cgc-pclk";
172 compatible = "renesas,ra-cgc-pclk";
179 compatible = "renesas,ra-cgc-pclk";
186 compatible = "renesas,ra-cgc-pclk";
192 compatible = "renesas,ra-cgc-pclk";
198 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa4w1ad2cng.dtsi117 compatible = "renesas,ra-cgc-pclk-block";
127 compatible = "renesas,ra-cgc-pclk";
134 compatible = "renesas,ra-cgc-pclk";
141 compatible = "renesas,ra-cgc-pclk";
148 compatible = "renesas,ra-cgc-pclk";
155 compatible = "renesas,ra-cgc-pclk";
162 compatible = "renesas,ra-cgc-pclk";
169 compatible = "renesas,ra-cgc-pclk";
175 compatible = "renesas,ra-cgc-pclk";
Dr7fa4m3ax.dtsi213 compatible = "renesas,ra-cgc-pclk-block";
223 compatible = "renesas,ra-cgc-pclk";
230 compatible = "renesas,ra-cgc-pclk";
237 compatible = "renesas,ra-cgc-pclk";
244 compatible = "renesas,ra-cgc-pclk";
251 compatible = "renesas,ra-cgc-pclk";
258 compatible = "renesas,ra-cgc-pclk";
265 compatible = "renesas,ra-cgc-pclk";
271 compatible = "renesas,ra-cgc-pclk";
Dr7fa4m2ax.dtsi202 compatible = "renesas,ra-cgc-pclk-block";
212 compatible = "renesas,ra-cgc-pclk";
219 compatible = "renesas,ra-cgc-pclk";
226 compatible = "renesas,ra-cgc-pclk";
233 compatible = "renesas,ra-cgc-pclk";
240 compatible = "renesas,ra-cgc-pclk";
247 compatible = "renesas,ra-cgc-pclk";
254 compatible = "renesas,ra-cgc-pclk";
260 compatible = "renesas,ra-cgc-pclk";
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dr7fa6e2bx.dtsi143 compatible = "renesas,ra-cgc-pclk-block";
153 compatible = "renesas,ra-cgc-pclk";
160 compatible = "renesas,ra-cgc-pclk";
167 compatible = "renesas,ra-cgc-pclk";
174 compatible = "renesas,ra-cgc-pclk";
181 compatible = "renesas,ra-cgc-pclk";
188 compatible = "renesas,ra-cgc-pclk";
195 compatible = "renesas,ra-cgc-pclk";
201 compatible = "renesas,ra-cgc-pclk";
207 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa6m1ad3cfp.dtsi92 compatible = "renesas,ra-cgc-pclk-block";
102 compatible = "renesas,ra-cgc-pclk";
109 compatible = "renesas,ra-cgc-pclk";
116 compatible = "renesas,ra-cgc-pclk";
123 compatible = "renesas,ra-cgc-pclk";
130 compatible = "renesas,ra-cgc-pclk";
137 compatible = "renesas,ra-cgc-pclk";
150 compatible = "renesas,ra-cgc-pclk";
157 compatible = "renesas,ra-cgc-pclk";
164 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m2ax.dtsi136 compatible = "renesas,ra-cgc-pclk-block";
146 compatible = "renesas,ra-cgc-pclk";
153 compatible = "renesas,ra-cgc-pclk";
160 compatible = "renesas,ra-cgc-pclk";
167 compatible = "renesas,ra-cgc-pclk";
174 compatible = "renesas,ra-cgc-pclk";
181 compatible = "renesas,ra-cgc-pclk";
194 compatible = "renesas,ra-cgc-pclk";
201 compatible = "renesas,ra-cgc-pclk";
208 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m3ax.dtsi190 compatible = "renesas,ra-cgc-pclk-block";
200 compatible = "renesas,ra-cgc-pclk";
207 compatible = "renesas,ra-cgc-pclk";
214 compatible = "renesas,ra-cgc-pclk";
221 compatible = "renesas,ra-cgc-pclk";
228 compatible = "renesas,ra-cgc-pclk";
235 compatible = "renesas,ra-cgc-pclk";
248 compatible = "renesas,ra-cgc-pclk";
255 compatible = "renesas,ra-cgc-pclk";
262 compatible = "renesas,ra-cgc-pclk";
Dr7fa6e10x.dtsi180 compatible = "renesas,ra-cgc-pclk-block";
190 compatible = "renesas,ra-cgc-pclk";
197 compatible = "renesas,ra-cgc-pclk";
204 compatible = "renesas,ra-cgc-pclk";
211 compatible = "renesas,ra-cgc-pclk";
218 compatible = "renesas,ra-cgc-pclk";
225 compatible = "renesas,ra-cgc-pclk";
232 compatible = "renesas,ra-cgc-pclk";
238 compatible = "renesas,ra-cgc-pclk";
Dr7fa6m5xh.dtsi340 compatible = "renesas,ra-cgc-pclk-block";
350 compatible = "renesas,ra-cgc-pclk";
357 compatible = "renesas,ra-cgc-pclk";
364 compatible = "renesas,ra-cgc-pclk";
371 compatible = "renesas,ra-cgc-pclk";
378 compatible = "renesas,ra-cgc-pclk";
385 compatible = "renesas,ra-cgc-pclk";
398 compatible = "renesas,ra-cgc-pclk";
405 compatible = "renesas,ra-cgc-pclk";
411 compatible = "renesas,ra-cgc-pclk";
[all …]
Dr7fa6m4ax.dtsi289 compatible = "renesas,ra-cgc-pclk-block";
299 compatible = "renesas,ra-cgc-pclk";
306 compatible = "renesas,ra-cgc-pclk";
313 compatible = "renesas,ra-cgc-pclk";
320 compatible = "renesas,ra-cgc-pclk";
327 compatible = "renesas,ra-cgc-pclk";
334 compatible = "renesas,ra-cgc-pclk";
347 compatible = "renesas,ra-cgc-pclk";
354 compatible = "renesas,ra-cgc-pclk";
360 compatible = "renesas,ra-cgc-pclk";
[all …]
/Zephyr-latest/dts/bindings/clock/
Drenesas,ra-cgc-pclk-block.yaml4 description: Renesas RA Clock Control node pclk block
6 compatible: "renesas,ra-cgc-pclk-block"
Drenesas,ra-cgc-pclk.yaml6 compatible: "renesas,ra-cgc-pclk"
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dsoc.h14 /* On FU740, peripherals are clocked by PCLK. */
16 DT_PROP(DT_NODELABEL(pclk), clock_frequency)
Dclock.c15 BUILD_ASSERT(KHZ(125125) == DT_PROP(DT_NODELABEL(pclk), clock_frequency),
16 "Unsupported PCLK frequency");
62 /* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */ in soc_early_init_hook()
/Zephyr-latest/dts/bindings/video/
Dnxp,video-smartdma.yaml25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dr7fa2a1xh.dtsi133 compatible = "renesas,ra-cgc-pclk-block";
143 compatible = "renesas,ra-cgc-pclk";
150 compatible = "renesas,ra-cgc-pclk";
157 compatible = "renesas,ra-cgc-pclk";
164 compatible = "renesas,ra-cgc-pclk";
171 compatible = "renesas,ra-cgc-pclk";
178 compatible = "renesas,ra-cgc-pclk";
/Zephyr-latest/dts/arm/renesas/ra/
Dra-cm4-common.dtsi89 compatible = "renesas,ra-cgc-pclk-block";
94 compatible = "renesas,ra-cgc-pclk-block";
100 compatible = "renesas,ra-cgc-pclk";
107 compatible = "renesas,ra-cgc-pclk";
114 compatible = "renesas,ra-cgc-pclk";
121 compatible = "renesas,ra-cgc-pclk";
128 compatible = "renesas,ra-cgc-pclk";
135 compatible = "renesas,ra-cgc-pclk";
142 compatible = "renesas,ra-cgc-pclk";
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdgt_gd32.c47 * timeout = pclk * INTERNAL_DIVIDER * (2^prescaler_exp) * (count + 1)
49 * count = (timeout * pclk / INTERNAL_DIVIDER * (2^prescaler_exp) ) - 1
57 uint32_t pclk; in gd32_wwdgt_calc_ticks() local
61 &pclk); in gd32_wwdgt_calc_ticks()
63 return ((timeout * pclk) in gd32_wwdgt_calc_ticks()
/Zephyr-latest/drivers/pwm/
Dpwm_rpi_pico.c55 uint32_t pclk; in pwm_rpi_get_cycles_per_sec() local
64 ret = clock_control_get_rate(cfg->clk_dev, cfg->clk_id, &pclk); in pwm_rpi_get_cycles_per_sec()
65 if (ret < 0 || pclk == 0) { in pwm_rpi_get_cycles_per_sec()
70 *cycles = pclk; in pwm_rpi_get_cycles_per_sec()
75 *cycles = (uint64_t)pclk * 16 / in pwm_rpi_get_cycles_per_sec()
/Zephyr-latest/drivers/misc/ft8xx/
Dft8xx.c43 uint8_t pclk; member
55 .pclk = DT_INST_PROP(0, pclk),
165 ft8xx_wr8(FT800_REG_PCLK, config->pclk); in ft8xx_init()

123