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Searched refs:rctl (Results 1 – 25 of 114) sorted by relevance

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/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi50 rctl: reset-controller { label
51 compatible = "gd,gd32-rctl";
76 resets = <&rctl GD32_RESET_USART0>;
85 resets = <&rctl GD32_RESET_USART1>;
94 resets = <&rctl GD32_RESET_USART2>;
103 resets = <&rctl GD32_RESET_UART3>;
112 resets = <&rctl GD32_RESET_UART4>;
121 resets = <&rctl GD32_RESET_USART5>;
130 resets = <&rctl GD32_RESET_UART6>;
139 resets = <&rctl GD32_RESET_UART7>;
[all …]
Dgd32f450.dtsi17 resets = <&rctl GD32_RESET_SPI3>;
28 resets = <&rctl GD32_RESET_SPI4>;
39 resets = <&rctl GD32_RESET_SPI5>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi51 rctl: reset-controller { label
52 compatible = "gd,gd32-rctl";
78 resets = <&rctl GD32_RESET_USART0>;
87 resets = <&rctl GD32_RESET_USART1>;
96 resets = <&rctl GD32_RESET_USART2>;
105 resets = <&rctl GD32_RESET_UART3>;
114 resets = <&rctl GD32_RESET_UART4>;
123 resets = <&rctl GD32_RESET_SPI0>;
134 resets = <&rctl GD32_RESET_SPI1>;
145 resets = <&rctl GD32_RESET_SPI2>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi45 rctl: reset-controller { label
46 compatible = "gd,gd32-rctl";
71 resets = <&rctl GD32_RESET_USART0>;
80 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_USART2>;
98 resets = <&rctl GD32_RESET_UART3>;
107 resets = <&rctl GD32_RESET_UART4>;
115 resets = <&rctl GD32_RESET_DAC>;
130 resets = <&rctl GD32_RESET_I2C0>;
143 resets = <&rctl GD32_RESET_I2C1>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi51 rctl: reset-controller { label
52 compatible = "gd,gd32-rctl";
79 resets = <&rctl GD32_RESET_USART0>;
88 resets = <&rctl GD32_RESET_USART1>;
97 resets = <&rctl GD32_RESET_USART2>;
105 resets = <&rctl GD32_RESET_DAC>;
120 resets = <&rctl GD32_RESET_I2C0>;
133 resets = <&rctl GD32_RESET_I2C1>;
142 resets = <&rctl GD32_RESET_SPI0>;
153 resets = <&rctl GD32_RESET_SPI1>;
[all …]
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi72 rctl: reset-controller { label
73 compatible = "gd,gd32-rctl";
98 resets = <&rctl GD32_RESET_USART0>;
107 resets = <&rctl GD32_RESET_USART1>;
116 resets = <&rctl GD32_RESET_USART2>;
125 resets = <&rctl GD32_RESET_UART3>;
134 resets = <&rctl GD32_RESET_UART4>;
143 resets = <&rctl GD32_RESET_ADC0>;
154 resets = <&rctl GD32_RESET_ADC1>;
164 resets = <&rctl GD32_RESET_DAC>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi45 rctl: reset-controller { label
46 compatible = "gd,gd32-rctl";
84 resets = <&rctl GD32_RESET_USART0>;
93 resets = <&rctl GD32_RESET_USART1>;
102 resets = <&rctl GD32_RESET_USART2>;
111 resets = <&rctl GD32_RESET_UART3>;
120 resets = <&rctl GD32_RESET_UART4>;
130 resets = <&rctl GD32_RESET_USART5>;
138 resets = <&rctl GD32_RESET_DAC>;
153 resets = <&rctl GD32_RESET_I2C0>;
[all …]
Dgd32e507xe.dtsi18 resets = <&rctl GD32_RESET_TIMER7>;
36 resets = <&rctl GD32_RESET_TIMER8>;
53 resets = <&rctl GD32_RESET_TIMER9>;
70 resets = <&rctl GD32_RESET_TIMER10>;
87 resets = <&rctl GD32_RESET_TIMER11>;
104 resets = <&rctl GD32_RESET_TIMER12>;
121 resets = <&rctl GD32_RESET_TIMER13>;
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi43 rctl: reset-controller { label
44 compatible = "gd,gd32-rctl";
70 resets = <&rctl GD32_RESET_USART0>;
79 resets = <&rctl GD32_RESET_USART1>;
89 resets = <&rctl GD32_RESET_ADC>;
115 resets = <&rctl GD32_RESET_WWDGT>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi43 rctl: reset-controller { label
44 compatible = "gd,gd32-rctl";
74 resets = <&rctl GD32_RESET_USART0>;
83 resets = <&rctl GD32_RESET_USART1>;
92 resets = <&rctl GD32_RESET_UART3>;
101 resets = <&rctl GD32_RESET_ADC>;
133 resets = <&rctl GD32_RESET_GPIOA>;
143 resets = <&rctl GD32_RESET_GPIOB>;
153 resets = <&rctl GD32_RESET_GPIOC>;
163 resets = <&rctl GD32_RESET_GPIOD>;
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f413.dtsi17 resets = <&rctl STM32_RESET(APB1, 19U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
62 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f405.dtsi50 resets = <&rctl STM32_RESET(APB1, 18U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 4U)>;
93 resets = <&rctl STM32_RESET(APB1, 5U)>;
109 resets = <&rctl STM32_RESET(APB2, 1U)>;
132 resets = <&rctl STM32_RESET(APB1, 6U)>;
154 resets = <&rctl STM32_RESET(APB1, 7U)>;
176 resets = <&rctl STM32_RESET(APB1, 8U)>;
/Zephyr-latest/dts/arm/st/f0/
Dstm32f030Xc.dtsi33 resets = <&rctl STM32_RESET(APB1, 18U)>;
42 resets = <&rctl STM32_RESET(APB1, 19U)>;
51 resets = <&rctl STM32_RESET(APB1, 20U)>;
60 resets = <&rctl STM32_RESET(APB2, 5U)>;
69 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f091.dtsi23 resets = <&rctl STM32_RESET(APB1, 20U)>;
32 resets = <&rctl STM32_RESET(APB2, 5U)>;
41 resets = <&rctl STM32_RESET(APB2, 6U)>;
50 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f070Xb.dtsi32 resets = <&rctl STM32_RESET(APB1, 18U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
72 resets = <&rctl STM32_RESET(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 5U)>;
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi130 resets = <&rctl STM32_RESET(APB1L, 19U)>;
139 resets = <&rctl STM32_RESET(APB1L, 20U)>;
148 resets = <&rctl STM32_RESET(APB1L, 30U)>;
157 resets = <&rctl STM32_RESET(APB1L, 31U)>;
166 resets = <&rctl STM32_RESET(APB1H, 0U)>;
175 resets = <&rctl STM32_RESET(APB1L, 25U)>;
184 resets = <&rctl STM32_RESET(APB1L, 26U)>;
193 resets = <&rctl STM32_RESET(APB1L, 27U)>;
202 resets = <&rctl STM32_RESET(APB1H, 1U)>;
294 resets = <&rctl STM32_RESET(APB1L, 2U)>;
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi36 resets = <&rctl STM32_RESET(APB2, 19U)>;
53 resets = <&rctl STM32_RESET(APB2, 20U)>;
70 resets = <&rctl STM32_RESET(APB2, 21U)>;
87 resets = <&rctl STM32_RESET(APB1, 6U)>;
104 resets = <&rctl STM32_RESET(APB1, 7U)>;
121 resets = <&rctl STM32_RESET(APB1, 8U)>;
Dstm32f103Xc.dtsi30 resets = <&rctl STM32_RESET(APB1, 19U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
144 resets = <&rctl STM32_RESET(APB2, 13U)>;
/Zephyr-latest/dts/arm/st/g0/
Dstm32g070.dtsi18 resets = <&rctl STM32_RESET(APB1L, 18U)>;
27 resets = <&rctl STM32_RESET(APB1L, 19U)>;
36 resets = <&rctl STM32_RESET(APB1H, 16U)>;
Dstm32g051.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
32 resets = <&rctl STM32_RESET(APB1L, 5U)>;
48 resets = <&rctl STM32_RESET(APB1H, 16U)>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi61 resets = <&rctl STM32_RESET(APB1, 1U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
115 resets = <&rctl STM32_RESET(APB2, 5U)>;
137 resets = <&rctl STM32_RESET(APB2, 14U)>;
146 resets = <&rctl STM32_RESET(APB1, 19U)>;
155 resets = <&rctl STM32_RESET(APB1, 20U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l471.dtsi52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
111 resets = <&rctl STM32_RESET(APB1L, 1U)>;
133 resets = <&rctl STM32_RESET(APB1L, 2U)>;
155 resets = <&rctl STM32_RESET(APB1L, 3U)>;
177 resets = <&rctl STM32_RESET(APB1L, 5U)>;
193 resets = <&rctl STM32_RESET(APB2, 13U)>;
210 resets = <&rctl STM32_RESET(APB2, 18U)>;
242 resets = <&rctl STM32_RESET(APB2, 10U)>;
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi100 rctl: reset-controller { label
101 compatible = "st,stm32-rcc-rctl";
235 resets = <&rctl STM32_RESET(APB2, 4U)>;
244 resets = <&rctl STM32_RESET(APB1, 17U)>;
253 resets = <&rctl STM32_RESET(APB1, 18U)>;
262 resets = <&rctl STM32_RESET(APB2, 5U)>;
271 resets = <&rctl STM32_RESET(APB1, 19U)>;
280 resets = <&rctl STM32_RESET(APB1, 20U)>;
413 resets = <&rctl STM32_RESET(APB2, 0U)>;
430 resets = <&rctl STM32_RESET(APB1, 0U)>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi72 resets = <&rctl STM32_RESET(APB1, 2U)>;
89 resets = <&rctl STM32_RESET(APB1, 3U)>;
106 resets = <&rctl STM32_RESET(APB1, 6U)>;
123 resets = <&rctl STM32_RESET(APB1, 7U)>;
140 resets = <&rctl STM32_RESET(APB1, 8U)>;
157 resets = <&rctl STM32_RESET(APB1, 9U)>;
174 resets = <&rctl STM32_RESET(APB2, 19U)>;
/Zephyr-latest/dts/arm/st/u0/
Dstm32u0.dtsi118 rctl: reset-controller { label
119 compatible = "st,stm32-rcc-rctl";
195 resets = <&rctl STM32_RESET(APB1H, 14U)>;
204 resets = <&rctl STM32_RESET(APB1L, 17U)>;
213 resets = <&rctl STM32_RESET(APB1L, 18U)>;
222 resets = <&rctl STM32_RESET(APB1L, 20U)>;
231 resets = <&rctl STM32_RESET(APB1L, 7U)>;
375 resets = <&rctl STM32_RESET(AHB1, 16U)>;
396 resets = <&rctl STM32_RESET(APB1H, 11U)>;
418 resets = <&rctl STM32_RESET(APB1L, 0U)>;
[all …]

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