1/*
2 * Copyright (c) 2021 YuLong Yao <feilongphone@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/pwm/pwm.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13#include <zephyr/dt-bindings/reset/gd32e10x.h>
14
15/ {
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			clock-frequency = <DT_FREQ_M(120)>;
22			compatible = "arm,cortex-m4f";
23			reg = <0>;
24			#address-cells = <1>;
25			#size-cells = <1>;
26		};
27	};
28
29	soc {
30		sram0: memory@20000000 {
31			compatible = "mmio-sram";
32		};
33
34		rcu: reset-clock-controller@40021000 {
35			compatible = "gd,gd32-rcu";
36			reg = <0x40021000 0x400>;
37			status = "okay";
38
39			cctl: clock-controller {
40				compatible = "gd,gd32-cctl";
41				#clock-cells = <1>;
42				status = "okay";
43			};
44
45			rctl: reset-controller {
46				compatible = "gd,gd32-rctl";
47				#reset-cells = <1>;
48				status = "okay";
49			};
50		};
51
52		fmc: flash-controller@40022000 {
53			compatible = "gd,gd32-flash-controller";
54			reg = <0x40022000 0x400>;
55			#address-cells = <1>;
56			#size-cells = <1>;
57
58			flash0: flash@8000000 {
59				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
60				write-block-size = <2>;
61				max-erase-time-ms = <4>;
62				page-size = <DT_SIZE_K(1)>;
63			};
64		};
65
66		usart0: usart@40013800 {
67			compatible = "gd,gd32-usart";
68			reg = <0x40013800 0x400>;
69			interrupts = <37 0>;
70			clocks = <&cctl GD32_CLOCK_USART0>;
71			resets = <&rctl GD32_RESET_USART0>;
72			status = "disabled";
73		};
74
75		usart1: usart@40004400 {
76			compatible = "gd,gd32-usart";
77			reg = <0x40004400 0x400>;
78			interrupts = <38 0>;
79			clocks = <&cctl GD32_CLOCK_USART1>;
80			resets = <&rctl GD32_RESET_USART1>;
81			status = "disabled";
82		};
83
84		usart2: usart@40004800 {
85			compatible = "gd,gd32-usart";
86			reg = <0x40004800 0x400>;
87			interrupts = <39 0>;
88			clocks = <&cctl GD32_CLOCK_USART2>;
89			resets = <&rctl GD32_RESET_USART2>;
90			status = "disabled";
91		};
92
93		uart3: usart@40004c00 {
94			compatible = "gd,gd32-usart";
95			reg = <0x40004c00 0x400>;
96			interrupts = <52 0>;
97			clocks = <&cctl GD32_CLOCK_UART3>;
98			resets = <&rctl GD32_RESET_UART3>;
99			status = "disabled";
100		};
101
102		uart4: usart@40005000 {
103			compatible = "gd,gd32-usart";
104			reg = <0x40005000 0x400>;
105			interrupts = <53 0>;
106			clocks = <&cctl GD32_CLOCK_UART4>;
107			resets = <&rctl GD32_RESET_UART4>;
108			status = "disabled";
109		};
110
111		dac: dac@40007400 {
112			compatible = "gd,gd32-dac";
113			reg = <0x40007400 0x400>;
114			clocks = <&cctl GD32_CLOCK_DAC>;
115			resets = <&rctl GD32_RESET_DAC>;
116			num-channels = <2>;
117			status = "disabled";
118			#io-channel-cells = <1>;
119		};
120
121		i2c0: i2c@40005400 {
122			compatible = "gd,gd32-i2c";
123			reg = <0x40005400 0x400>;
124			#address-cells = <1>;
125			#size-cells = <0>;
126			clock-frequency = <I2C_BITRATE_STANDARD>;
127			interrupts = <31 0>, <32 0>;
128			interrupt-names = "event", "error";
129			clocks = <&cctl GD32_CLOCK_I2C0>;
130			resets = <&rctl GD32_RESET_I2C0>;
131			status = "disabled";
132		};
133
134		i2c1: i2c@40005800 {
135			compatible = "gd,gd32-i2c";
136			reg = <0x40005800 0x400>;
137			#address-cells = <1>;
138			#size-cells = <0>;
139			clock-frequency = <I2C_BITRATE_STANDARD>;
140			interrupts = <33 0>, <34 0>;
141			interrupt-names = "event", "error";
142			clocks = <&cctl GD32_CLOCK_I2C1>;
143			resets = <&rctl GD32_RESET_I2C1>;
144			status = "disabled";
145		};
146
147		afio: afio@40010000 {
148			compatible = "gd,gd32-afio";
149			reg = <0x40010000 0x400>;
150			clocks = <&cctl GD32_CLOCK_AFIO>;
151			status = "okay";
152		};
153
154		exti: interrupt-controller@40010400 {
155			compatible = "gd,gd32-exti";
156			interrupt-controller;
157			#interrupt-cells = <1>;
158			reg = <0x40010400 0x400>;
159			num-lines = <19>;
160			interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
161				     <40 0>;
162			interrupt-names = "line0", "line1", "line2", "line3",
163					  "line4", "line5-9", "line10-15";
164			status = "okay";
165		};
166
167		fwdgt: watchdog@40003000 {
168			compatible = "gd,gd32-fwdgt";
169			reg = <0x40003000 0x400>;
170			status = "disabled";
171		};
172
173		wwdgt: watchdog@40002c00 {
174			compatible = "gd,gd32-wwdgt";
175			reg = <0x40002C00 0x400>;
176			clocks = <&cctl GD32_CLOCK_WWDGT>;
177			resets = <&rctl GD32_RESET_WWDGT>;
178			interrupts = <0 0>;
179			status = "disabled";
180		};
181
182		pinctrl: pin-controller@40010800 {
183			compatible = "gd,gd32-pinctrl-afio";
184			reg = <0x40010800 0x1c00>;
185			#address-cells = <1>;
186			#size-cells = <1>;
187			status = "okay";
188
189			gpioa: gpio@40010800 {
190				compatible = "gd,gd32-gpio";
191				gpio-controller;
192				#gpio-cells = <2>;
193				reg = <0x40010800 0x400>;
194				clocks = <&cctl GD32_CLOCK_GPIOA>;
195				resets = <&rctl GD32_RESET_GPIOA>;
196				status = "disabled";
197			};
198
199			gpiob: gpio@40010c00 {
200				compatible = "gd,gd32-gpio";
201				gpio-controller;
202				#gpio-cells = <2>;
203				reg = <0x40010c00 0x400>;
204				clocks = <&cctl GD32_CLOCK_GPIOB>;
205				resets = <&rctl GD32_RESET_GPIOB>;
206				status = "disabled";
207			};
208
209			gpioc: gpio@40011000 {
210				compatible = "gd,gd32-gpio";
211				gpio-controller;
212				#gpio-cells = <2>;
213				reg = <0x40011000 0x400>;
214				clocks = <&cctl GD32_CLOCK_GPIOC>;
215				resets = <&rctl GD32_RESET_GPIOC>;
216				status = "disabled";
217			};
218
219			gpiod: gpio@40011400 {
220				compatible = "gd,gd32-gpio";
221				gpio-controller;
222				#gpio-cells = <2>;
223				reg = <0x40011400 0x400>;
224				clocks = <&cctl GD32_CLOCK_GPIOD>;
225				resets = <&rctl GD32_RESET_GPIOD>;
226				status = "disabled";
227			};
228
229			gpioe: gpio@40011800 {
230				compatible = "gd,gd32-gpio";
231				gpio-controller;
232				#gpio-cells = <2>;
233				reg = <0x40011800 0x400>;
234				clocks = <&cctl GD32_CLOCK_GPIOE>;
235				resets = <&rctl GD32_RESET_GPIOE>;
236				status = "disabled";
237			};
238		};
239
240		timer0: timer@40012c00 {
241			compatible = "gd,gd32-timer";
242			reg = <0x40012c00 0x400>;
243			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
244			interrupt-names = "brk", "up", "trgcom", "cc";
245			clocks = <&cctl GD32_CLOCK_TIMER0>;
246			resets = <&rctl GD32_RESET_TIMER0>;
247			is-advanced;
248			channels = <4>;
249			status = "disabled";
250
251			pwm {
252				compatible = "gd,gd32-pwm";
253				status = "disabled";
254				#pwm-cells = <3>;
255			};
256		};
257
258		timer1: timer@40000000 {
259			compatible = "gd,gd32-timer";
260			reg = <0x40000000 0x400>;
261			interrupts = <28 0>;
262			interrupt-names = "global";
263			clocks = <&cctl GD32_CLOCK_TIMER1>;
264			resets = <&rctl GD32_RESET_TIMER1>;
265			channels = <4>;
266			status = "disabled";
267
268			pwm {
269				compatible = "gd,gd32-pwm";
270				status = "disabled";
271				#pwm-cells = <3>;
272			};
273		};
274
275		timer2: timer@40000400 {
276			compatible = "gd,gd32-timer";
277			reg = <0x40000400 0x400>;
278			interrupts = <29 0>;
279			interrupt-names = "global";
280			clocks = <&cctl GD32_CLOCK_TIMER2>;
281			resets = <&rctl GD32_RESET_TIMER2>;
282			channels = <4>;
283			status = "disabled";
284
285			pwm {
286				compatible = "gd,gd32-pwm";
287				status = "disabled";
288				#pwm-cells = <3>;
289			};
290		};
291
292		timer3: timer@40000800 {
293			compatible = "gd,gd32-timer";
294			reg = <0x40000800 0x400>;
295			interrupts = <30 0>;
296			interrupt-names = "global";
297			clocks = <&cctl GD32_CLOCK_TIMER3>;
298			resets = <&rctl GD32_RESET_TIMER3>;
299			channels = <4>;
300			status = "disabled";
301
302			pwm {
303				compatible = "gd,gd32-pwm";
304				status = "disabled";
305				#pwm-cells = <3>;
306			};
307		};
308
309		timer4: timer@40000c00 {
310			compatible = "gd,gd32-timer";
311			reg = <0x40000c00 0x400>;
312			interrupts = <50 0>;
313			interrupt-names = "global";
314			clocks = <&cctl GD32_CLOCK_TIMER4>;
315			resets = <&rctl GD32_RESET_TIMER4>;
316			channels = <4>;
317			status = "disabled";
318
319			pwm {
320				compatible = "gd,gd32-pwm";
321				status = "disabled";
322				#pwm-cells = <3>;
323			};
324		};
325
326		timer5: timer@40001000 {
327			compatible = "gd,gd32-timer";
328			reg = <0x40001000 0x400>;
329			interrupts = <54 0>;
330			interrupt-names = "global";
331			clocks = <&cctl GD32_CLOCK_TIMER5>;
332			resets = <&rctl GD32_RESET_TIMER5>;
333			channels = <0>;
334			status = "disabled";
335		};
336
337		timer6: timer@40001400 {
338			compatible = "gd,gd32-timer";
339			reg = <0x40001400 0x400>;
340			interrupts = <55 0>;
341			interrupt-names = "global";
342			clocks = <&cctl GD32_CLOCK_TIMER6>;
343			resets = <&rctl GD32_RESET_TIMER6>;
344			channels = <0>;
345			status = "disabled";
346		};
347
348		timer7: timer@40013400 {
349			compatible = "gd,gd32-timer";
350			reg = <0x40013400 0x400>;
351			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
352			interrupt-names = "brk", "up", "trgcom", "cc";
353			clocks = <&cctl GD32_CLOCK_TIMER7>;
354			resets = <&rctl GD32_RESET_TIMER7>;
355			is-advanced;
356			channels = <4>;
357			status = "disabled";
358
359			pwm {
360				compatible = "gd,gd32-pwm";
361				status = "disabled";
362				#pwm-cells = <3>;
363			};
364		};
365
366		timer8: timer@40014c00 {
367			compatible = "gd,gd32-timer";
368			reg = <0x40014c00 0x400>;
369			interrupts = <24 0>;
370			interrupt-names = "global";
371			clocks = <&cctl GD32_CLOCK_TIMER8>;
372			resets = <&rctl GD32_RESET_TIMER8>;
373			channels = <2>;
374			status = "disabled";
375
376			pwm {
377				compatible = "gd,gd32-pwm";
378				status = "disabled";
379				#pwm-cells = <3>;
380			};
381		};
382
383		timer9: timer@40015000 {
384			compatible = "gd,gd32-timer";
385			reg = <0x40015000 0x400>;
386			interrupts = <25 0>;
387			interrupt-names = "global";
388			clocks = <&cctl GD32_CLOCK_TIMER9>;
389			resets = <&rctl GD32_RESET_TIMER9>;
390			channels = <1>;
391			status = "disabled";
392
393			pwm {
394				compatible = "gd,gd32-pwm";
395				status = "disabled";
396				#pwm-cells = <3>;
397			};
398		};
399
400		timer10: timer@40015400 {
401			compatible = "gd,gd32-timer";
402			reg = <0x40015400 0x400>;
403			interrupts = <26 0>;
404			interrupt-names = "global";
405			clocks = <&cctl GD32_CLOCK_TIMER10>;
406			resets = <&rctl GD32_RESET_TIMER10>;
407			channels = <1>;
408			status = "disabled";
409
410			pwm {
411				compatible = "gd,gd32-pwm";
412				status = "disabled";
413				#pwm-cells = <3>;
414			};
415		};
416
417		timer11: timer@40001800 {
418			compatible = "gd,gd32-timer";
419			reg = <0x40001800 0x400>;
420			interrupts = <43 0>;
421			interrupt-names = "global";
422			clocks = <&cctl GD32_CLOCK_TIMER11>;
423			resets = <&rctl GD32_RESET_TIMER11>;
424			channels = <2>;
425			status = "disabled";
426
427			pwm {
428				compatible = "gd,gd32-pwm";
429				status = "disabled";
430				#pwm-cells = <3>;
431			};
432		};
433
434		timer12: timer@40001c00 {
435			compatible = "gd,gd32-timer";
436			reg = <0x40001c00 0x400>;
437			interrupts = <44 0>;
438			interrupt-names = "global";
439			clocks = <&cctl GD32_CLOCK_TIMER12>;
440			resets = <&rctl GD32_RESET_TIMER12>;
441			channels = <1>;
442			status = "disabled";
443
444			pwm {
445				compatible = "gd,gd32-pwm";
446				status = "disabled";
447				#pwm-cells = <3>;
448			};
449		};
450
451		timer13: timer@40002000 {
452			compatible = "gd,gd32-timer";
453			reg = <0x40002000 0x400>;
454			interrupts = <45 0>;
455			interrupt-names = "global";
456			clocks = <&cctl GD32_CLOCK_TIMER13>;
457			resets = <&rctl GD32_RESET_TIMER13>;
458			channels = <1>;
459			status = "disabled";
460
461			pwm {
462				compatible = "gd,gd32-pwm";
463				status = "disabled";
464				#pwm-cells = <3>;
465			};
466		};
467
468		dma0: dma@40020000 {
469			compatible = "gd,gd32-dma";
470			reg = <0x40020000 0x400>;
471			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
472				     <15 0>, <16 0>, <17 0>;
473			clocks = <&cctl GD32_CLOCK_DMA0>;
474			dma-channels = <7>;
475			#dma-cells = <2>;
476			status = "disabled";
477		};
478
479		dma1: dma@40020400 {
480			compatible = "gd,gd32-dma";
481			reg = <0x40020400 0x400>;
482			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
483				     <60 0>;
484			clocks = <&cctl GD32_CLOCK_DMA1>;
485			dma-channels = <5>;
486			#dma-cells = <2>;
487			status = "disabled";
488		};
489
490	};
491};
492
493&nvic {
494	arm,num-irq-priority-bits = <4>;
495};
496