1/*
2 * Copyright (c) Bobby Noelte
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f0/stm32f071.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32f091", "st,stm32f0", "simple-bus";
12
13		/*
14		 * USARTs 3-8 share the same IRQ on stm32f091xx devices. This
15		 * configuration is not currently supported, so at most one of
16		 * these may be enabled at a time. Enabling more than one will
17		 * result in a build failure.
18		 */
19		usart5: serial@40005000 {
20			compatible = "st,stm32-usart", "st,stm32-uart";
21			reg = <0x40005000 0x400>;
22			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
23			resets = <&rctl STM32_RESET(APB1, 20U)>;
24			interrupts = <29 0>;
25			status = "disabled";
26		};
27
28		usart6: serial@40011400 {
29			compatible = "st,stm32-usart", "st,stm32-uart";
30			reg = <0x40011400 0x400>;
31			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
32			resets = <&rctl STM32_RESET(APB2, 5U)>;
33			interrupts = <29 0>;
34			status = "disabled";
35		};
36
37		usart7: serial@40011800 {
38			compatible = "st,stm32-usart", "st,stm32-uart";
39			reg = <0x40011800 0x400>;
40			clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
41			resets = <&rctl STM32_RESET(APB2, 6U)>;
42			interrupts = <29 0>;
43			status = "disabled";
44		};
45
46		usart8: serial@40011c00 {
47			compatible = "st,stm32-usart", "st,stm32-uart";
48			reg = <0x40011c00 0x400>;
49			clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
50			resets = <&rctl STM32_RESET(APB2, 7U)>;
51			interrupts = <29 0>;
52			status = "disabled";
53		};
54
55		can1: can@40006400 {
56			compatible = "st,stm32-bxcan";
57			reg = <0x40006400 0x400>;
58			interrupts = <30 0>;
59			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
60			status = "disabled";
61		};
62
63		dma2: dma@40020400 {
64			compatible = "st,stm32-dma-v2bis";
65			#dma-cells = <2>;
66			reg = <0x40020400 0x400>;
67			interrupts = <10 0 10 0 11 0 11 0 11 0>;
68			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
69			status = "disabled";
70		};
71	};
72};
73