1/*
2 * Copyright (c) 2021 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/adc/gd32f3x0.h>
12#include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13#include <zephyr/dt-bindings/reset/gd32f3x0.h>
14
15/ {
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			clock-frequency = <DT_FREQ_M(108)>;
22			compatible = "arm,cortex-m4f";
23			reg = <0>;
24		};
25	};
26
27	soc {
28		sram0: memory@20000000 {
29			compatible = "mmio-sram";
30		};
31
32		rcu: reset-clock-controller@40021000 {
33			compatible = "gd,gd32-rcu";
34			reg = <0x40021000 0x400>;
35			status = "okay";
36
37			cctl: clock-controller {
38				compatible = "gd,gd32-cctl";
39				#clock-cells = <1>;
40				status = "okay";
41			};
42
43			rctl: reset-controller {
44				compatible = "gd,gd32-rctl";
45				#reset-cells = <1>;
46				status = "okay";
47			};
48		};
49
50		fmc: flash-controller@40022000 {
51			compatible = "gd,gd32-flash-controller";
52			reg = <0x40022000 0x400>;
53
54			#address-cells = <1>;
55			#size-cells = <1>;
56
57			flash0: flash@8000000 {
58				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
59				write-block-size = <2>;
60				max-erase-time-ms = <300>;
61				page-size = <DT_SIZE_K(1)>;
62			};
63		};
64
65		usart0: usart@40013800 {
66			compatible = "gd,gd32-usart";
67			reg = <0x40013800 0x400>;
68			interrupts = <27 0>;
69			clocks = <&cctl GD32_CLOCK_USART0>;
70			resets = <&rctl GD32_RESET_USART0>;
71			status = "disabled";
72		};
73
74		usart1: usart@40004400 {
75			compatible = "gd,gd32-usart";
76			reg = <0x40004400 0x400>;
77			interrupts = <28 0>;
78			clocks = <&cctl GD32_CLOCK_USART1>;
79			resets = <&rctl GD32_RESET_USART1>;
80			status = "disabled";
81		};
82
83		adc0: adc@40012400 {
84			compatible = "gd,gd32-adc";
85			reg = <0x40012400 0x400>;
86			interrupts = <12 0>;
87			rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
88			clocks = <&cctl GD32_CLOCK_ADC>;
89			resets = <&rctl GD32_RESET_ADC>;
90			channels = <16>;
91			status = "disabled";
92			#io-channel-cells = <1>;
93		};
94
95		dma: dma@40020000 {
96			compatible = "gd,gd32-dma";
97			reg = <0x40020000 0x400>;
98			interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
99			clocks = <&cctl GD32_CLOCK_DMA>;
100			dma-channels = <7>;
101			#dma-cells = <2>;
102			status = "disabled";
103		};
104
105		fwdgt: watchdog@40003000 {
106			compatible = "gd,gd32-fwdgt";
107			reg = <0x40003000 0x400>;
108			status = "disabled";
109		};
110
111		wwdgt: watchdog@40002c00 {
112			compatible = "gd,gd32-wwdgt";
113			reg = <0x40002C00 0x400>;
114			clocks = <&cctl GD32_CLOCK_WWDGT>;
115			resets = <&rctl GD32_RESET_WWDGT>;
116			interrupts = <0 0>;
117			status = "disabled";
118		};
119
120		pinctrl: pin-controller@48000000 {
121			compatible = "gd,gd32-pinctrl-af";
122			reg = <0x48000000 0x1800>;
123			#address-cells = <1>;
124			#size-cells = <1>;
125			status = "okay";
126
127			gpioa: gpio@48000000 {
128				compatible = "gd,gd32-gpio";
129				gpio-controller;
130				#gpio-cells = <2>;
131				reg = <0x48000000 0x400>;
132				clocks = <&cctl GD32_CLOCK_GPIOA>;
133				resets = <&rctl GD32_RESET_GPIOA>;
134				status = "disabled";
135			};
136
137			gpiob: gpio@48000400 {
138				compatible = "gd,gd32-gpio";
139				gpio-controller;
140				#gpio-cells = <2>;
141				reg = <0x48000400 0x400>;
142				clocks = <&cctl GD32_CLOCK_GPIOB>;
143				resets = <&rctl GD32_RESET_GPIOB>;
144				status = "disabled";
145			};
146
147			gpioc: gpio@48000800 {
148				compatible = "gd,gd32-gpio";
149				gpio-controller;
150				#gpio-cells = <2>;
151				reg = <0x48000800 0x400>;
152				clocks = <&cctl GD32_CLOCK_GPIOC>;
153				resets = <&rctl GD32_RESET_GPIOC>;
154				status = "disabled";
155			};
156
157			gpiod: gpio@48000c00 {
158				compatible = "gd,gd32-gpio";
159				gpio-controller;
160				#gpio-cells = <2>;
161				reg = <0x48000c00 0x400>;
162				clocks = <&cctl GD32_CLOCK_GPIOD>;
163				resets = <&rctl GD32_RESET_GPIOD>;
164				status = "disabled";
165			};
166
167			gpiof: gpio@48001400 {
168				compatible = "gd,gd32-gpio";
169				gpio-controller;
170				#gpio-cells = <2>;
171				reg = <0x48001400 0x400>;
172				clocks = <&cctl GD32_CLOCK_GPIOF>;
173				resets = <&rctl GD32_RESET_GPIOF>;
174				status = "disabled";
175			};
176		};
177	};
178};
179
180&nvic {
181	arm,num-irq-priority-bits = <4>;
182};
183