1/*
2 * Copyright (c) 2021, ATL Electronics
3 * Copyright (c) 2021, Teslabs Engineering S.L.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <freq.h>
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/adc/adc.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32f403.h>
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-m4f";
23			clock-frequency = <DT_FREQ_M(168)>;
24			reg = <0>;
25			#address-cells = <1>;
26			#size-cells = <1>;
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv7m-mpu";
30				reg = <0xe000ed90 0x40>;
31			};
32		};
33	};
34
35	soc {
36		sram0: memory@20000000 {
37			compatible = "mmio-sram";
38		};
39
40		rcu: reset-clock-controller@40021000 {
41			compatible = "gd,gd32-rcu";
42			reg = <0x40021000 0x400>;
43			status = "okay";
44
45			cctl: clock-controller {
46				compatible = "gd,gd32-cctl";
47				#clock-cells = <1>;
48				status = "okay";
49			};
50
51			rctl: reset-controller {
52				compatible = "gd,gd32-rctl";
53				#reset-cells = <1>;
54				status = "okay";
55			};
56		};
57
58		fmc: flash-controller@40022000 {
59			compatible = "gd,gd32-flash-controller";
60			reg = <0x40022000 0x400>;
61			#address-cells = <1>;
62			#size-cells = <1>;
63
64			flash0: flash@8000000 {
65				compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
66				write-block-size = <2>;
67				max-erase-time-ms = <300>;
68				bank0-page-size = <DT_SIZE_K(2)>;
69				bank1-page-size = <DT_SIZE_K(4)>;
70			};
71		};
72
73		usart0: usart@40013800 {
74			compatible = "gd,gd32-usart";
75			reg = <0x40013800 0x400>;
76			interrupts = <37 0>;
77			clocks = <&cctl GD32_CLOCK_USART0>;
78			resets = <&rctl GD32_RESET_USART0>;
79			status = "disabled";
80		};
81
82		usart1: usart@40004400 {
83			compatible = "gd,gd32-usart";
84			reg = <0x40004400 0x400>;
85			interrupts = <38 0>;
86			clocks = <&cctl GD32_CLOCK_USART1>;
87			resets = <&rctl GD32_RESET_USART1>;
88			status = "disabled";
89		};
90
91		usart2: usart@40004800 {
92			compatible = "gd,gd32-usart";
93			reg = <0x40004800 0x400>;
94			interrupts = <39 0>;
95			clocks = <&cctl GD32_CLOCK_USART2>;
96			resets = <&rctl GD32_RESET_USART2>;
97			status = "disabled";
98		};
99
100		uart3: usart@40004c00 {
101			compatible = "gd,gd32-usart";
102			reg = <0x40004c00 0x400>;
103			interrupts = <52 0>;
104			clocks = <&cctl GD32_CLOCK_UART3>;
105			resets = <&rctl GD32_RESET_UART3>;
106			status = "disabled";
107		};
108
109		uart4: usart@40005000 {
110			compatible = "gd,gd32-usart";
111			reg = <0x40005000 0x400>;
112			interrupts = <53 0>;
113			clocks = <&cctl GD32_CLOCK_UART4>;
114			resets = <&rctl GD32_RESET_UART4>;
115			status = "disabled";
116		};
117
118		spi0: spi@40013000 {
119			compatible = "gd,gd32-spi";
120			reg = <0x40013000 0x400>;
121			interrupts = <35 0>;
122			clocks = <&cctl GD32_CLOCK_SPI0>;
123			resets = <&rctl GD32_RESET_SPI0>;
124			status = "disabled";
125			#address-cells = <1>;
126			#size-cells = <0>;
127		};
128
129		spi1: spi@40003800 {
130			compatible = "gd,gd32-spi";
131			reg = <0x40003800 0x400>;
132			interrupts = <36 0>;
133			clocks = <&cctl GD32_CLOCK_SPI1>;
134			resets = <&rctl GD32_RESET_SPI1>;
135			status = "disabled";
136			#address-cells = <1>;
137			#size-cells = <0>;
138		};
139
140		spi2: spi@40003c00 {
141			compatible = "gd,gd32-spi";
142			reg = <0x40003c00 0x400>;
143			interrupts = <51 0>;
144			clocks = <&cctl GD32_CLOCK_SPI2>;
145			resets = <&rctl GD32_RESET_SPI2>;
146			status = "disabled";
147			#address-cells = <1>;
148			#size-cells = <0>;
149		};
150
151		adc0: adc@40012400 {
152			compatible = "gd,gd32-adc";
153			reg = <0x40012400 0x400>;
154			interrupts = <18 0>;
155			clocks = <&cctl GD32_CLOCK_ADC0>;
156			resets = <&rctl GD32_RESET_ADC0>;
157			channels = <16>;
158			status = "disabled";
159			#io-channel-cells = <1>;
160		};
161
162		adc1: adc@40012800 {
163			compatible = "gd,gd32-adc";
164			reg = <0x40012800 0x400>;
165			interrupts = <18 0>;
166			clocks = <&cctl GD32_CLOCK_ADC1>;
167			resets = <&rctl GD32_RESET_ADC1>;
168			channels = <16>;
169			status = "disabled";
170			#io-channel-cells = <1>;
171		};
172
173		adc2: adc@40013c00 {
174			compatible = "gd,gd32-adc";
175			reg = <0x40013c00 0x400>;
176			interrupts = <47 0>;
177			clocks = <&cctl GD32_CLOCK_ADC2>;
178			resets = <&rctl GD32_RESET_ADC2>;
179			channels = <16>;
180			status = "disabled";
181			#io-channel-cells = <1>;
182		};
183
184		exti: interrupt-controller@40010400 {
185			compatible = "gd,gd32-exti";
186			interrupt-controller;
187			#interrupt-cells = <1>;
188			reg = <0x40010400 0x400>;
189			num-lines = <19>;
190			interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
191				     <40 0>;
192			interrupt-names = "line0", "line1", "line2",
193					  "line3", "line4", "line5-9",
194					  "line10-15";
195			status = "okay";
196		};
197
198		afio: afio@40010000 {
199			compatible = "gd,gd32-afio";
200			reg = <0x40010000 0x400>;
201			clocks = <&cctl GD32_CLOCK_AFIO>;
202			status = "okay";
203		};
204
205		fwdgt: watchdog@40003000 {
206			compatible = "gd,gd32-fwdgt";
207			reg = <0x40003000 0x400>;
208			status = "disabled";
209		};
210
211		wwdgt: watchdog@40002c00 {
212			compatible = "gd,gd32-wwdgt";
213			reg = <0x40002C00 0x400>;
214			clocks = <&cctl GD32_CLOCK_WWDGT>;
215			resets = <&rctl GD32_RESET_WWDGT>;
216			interrupts = <0 0>;
217			status = "disabled";
218		};
219
220		pinctrl: pin-controller@40010800 {
221			compatible = "gd,gd32-pinctrl-afio";
222			reg = <0x40010800 0x1c00>;
223			#address-cells = <1>;
224			#size-cells = <1>;
225			status = "okay";
226
227			gpioa: gpio@40010800 {
228				compatible = "gd,gd32-gpio";
229				gpio-controller;
230				#gpio-cells = <2>;
231				reg = <0x40010800 0x400>;
232				clocks = <&cctl GD32_CLOCK_GPIOA>;
233				resets = <&rctl GD32_RESET_GPIOA>;
234				status = "disabled";
235			};
236
237			gpiob: gpio@40010c00 {
238				compatible = "gd,gd32-gpio";
239				gpio-controller;
240				#gpio-cells = <2>;
241				reg = <0x40010c00 0x400>;
242				clocks = <&cctl GD32_CLOCK_GPIOB>;
243				resets = <&rctl GD32_RESET_GPIOB>;
244				status = "disabled";
245			};
246
247			gpioc: gpio@40011000 {
248				compatible = "gd,gd32-gpio";
249				gpio-controller;
250				#gpio-cells = <2>;
251				reg = <0x40011000 0x400>;
252				clocks = <&cctl GD32_CLOCK_GPIOC>;
253				resets = <&rctl GD32_RESET_GPIOC>;
254				status = "disabled";
255			};
256
257			gpiod: gpio@40011400 {
258				compatible = "gd,gd32-gpio";
259				gpio-controller;
260				#gpio-cells = <2>;
261				reg = <0x40011400 0x400>;
262				clocks = <&cctl GD32_CLOCK_GPIOD>;
263				resets = <&rctl GD32_RESET_GPIOD>;
264				status = "disabled";
265			};
266
267			gpioe: gpio@40011800 {
268				compatible = "gd,gd32-gpio";
269				gpio-controller;
270				#gpio-cells = <2>;
271				reg = <0x40011800 0x400>;
272				clocks = <&cctl GD32_CLOCK_GPIOE>;
273				resets = <&rctl GD32_RESET_GPIOE>;
274				status = "disabled";
275			};
276
277			gpiof: gpio@40011c00 {
278				compatible = "gd,gd32-gpio";
279				gpio-controller;
280				#gpio-cells = <2>;
281				reg = <0x40011c00 0x400>;
282				clocks = <&cctl GD32_CLOCK_GPIOF>;
283				resets = <&rctl GD32_RESET_GPIOF>;
284				status = "disabled";
285			};
286
287			gpiog: gpio@40012000 {
288				compatible = "gd,gd32-gpio";
289				gpio-controller;
290				#gpio-cells = <2>;
291				reg = <0x40012000 0x400>;
292				clocks = <&cctl GD32_CLOCK_GPIOG>;
293				resets = <&rctl GD32_RESET_GPIOG>;
294				status = "disabled";
295			};
296		};
297
298		timer0: timer@40012c00 {
299			compatible = "gd,gd32-timer";
300			reg = <0x40012c00 0x400>;
301			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
302			interrupt-names = "brk", "up", "trgcom", "cc";
303			clocks = <&cctl GD32_CLOCK_TIMER0>;
304			resets = <&rctl GD32_RESET_TIMER0>;
305			is-advanced;
306			channels = <4>;
307			status = "disabled";
308
309			pwm {
310				compatible = "gd,gd32-pwm";
311				status = "disabled";
312				#pwm-cells = <3>;
313			};
314		};
315
316		timer2: timer@40000400 {
317			compatible = "gd,gd32-timer";
318			reg = <0x40000400 0x400>;
319			interrupts = <29 0>;
320			interrupt-names = "global";
321			clocks = <&cctl GD32_CLOCK_TIMER2>;
322			resets = <&rctl GD32_RESET_TIMER2>;
323			channels = <4>;
324			status = "disabled";
325
326			pwm {
327				compatible = "gd,gd32-pwm";
328				status = "disabled";
329				#pwm-cells = <3>;
330			};
331		};
332
333		timer3: timer@40000800 {
334			compatible = "gd,gd32-timer";
335			reg = <0x40000800 0x400>;
336			interrupts = <30 0>;
337			interrupt-names = "global";
338			clocks = <&cctl GD32_CLOCK_TIMER3>;
339			resets = <&rctl GD32_RESET_TIMER3>;
340			channels = <4>;
341			status = "disabled";
342
343			pwm {
344				compatible = "gd,gd32-pwm";
345				status = "disabled";
346				#pwm-cells = <3>;
347			};
348		};
349
350		timer5: timer@40001000 {
351			compatible = "gd,gd32-timer";
352			reg = <0x40001000 0x400>;
353			interrupts = <54 0>;
354			interrupt-names = "global";
355			clocks = <&cctl GD32_CLOCK_TIMER5>;
356			resets = <&rctl GD32_RESET_TIMER5>;
357			channels = <0>;
358			status = "disabled";
359		};
360
361		timer6: timer@40001400 {
362			compatible = "gd,gd32-timer";
363			reg = <0x40001400 0x400>;
364			interrupts = <55 0>;
365			interrupt-names = "global";
366			clocks = <&cctl GD32_CLOCK_TIMER6>;
367			resets = <&rctl GD32_RESET_TIMER6>;
368			channels = <0>;
369			status = "disabled";
370		};
371
372		timer7: timer@40013400 {
373			compatible = "gd,gd32-timer";
374			reg = <0x40013400 0x400>;
375			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
376			interrupt-names = "brk", "up", "trgcom", "cc";
377			clocks = <&cctl GD32_CLOCK_TIMER7>;
378			resets = <&rctl GD32_RESET_TIMER7>;
379			is-advanced;
380			channels = <4>;
381			status = "disabled";
382
383			pwm {
384				compatible = "gd,gd32-pwm";
385				status = "disabled";
386				#pwm-cells = <3>;
387			};
388		};
389
390		timer8: timer@40014c00 {
391			compatible = "gd,gd32-timer";
392			reg = <0x40014c00 0x400>;
393			interrupts = <24 0>;
394			interrupt-names = "global";
395			clocks = <&cctl GD32_CLOCK_TIMER8>;
396			resets = <&rctl GD32_RESET_TIMER8>;
397			channels = <2>;
398			status = "disabled";
399
400			pwm {
401				compatible = "gd,gd32-pwm";
402				status = "disabled";
403				#pwm-cells = <3>;
404			};
405		};
406
407		timer9: timer@40015000 {
408			compatible = "gd,gd32-timer";
409			reg = <0x40015000 0x400>;
410			interrupts = <25 0>;
411			interrupt-names = "global";
412			clocks = <&cctl GD32_CLOCK_TIMER9>;
413			resets = <&rctl GD32_RESET_TIMER9>;
414			channels = <1>;
415			status = "disabled";
416
417			pwm {
418				compatible = "gd,gd32-pwm";
419				status = "disabled";
420				#pwm-cells = <3>;
421			};
422		};
423
424		timer10: timer@40015400 {
425			compatible = "gd,gd32-timer";
426			reg = <0x40015400 0x400>;
427			interrupts = <26 0>;
428			interrupt-names = "global";
429			clocks = <&cctl GD32_CLOCK_TIMER10>;
430			resets = <&rctl GD32_RESET_TIMER10>;
431			channels = <1>;
432			status = "disabled";
433
434			pwm {
435				compatible = "gd,gd32-pwm";
436				status = "disabled";
437				#pwm-cells = <3>;
438			};
439		};
440
441		timer11: timer@40001800 {
442			compatible = "gd,gd32-timer";
443			reg = <0x40001800 0x400>;
444			interrupts = <43 0>;
445			interrupt-names = "global";
446			clocks = <&cctl GD32_CLOCK_TIMER11>;
447			resets = <&rctl GD32_RESET_TIMER11>;
448			channels = <2>;
449			status = "disabled";
450
451			pwm {
452				compatible = "gd,gd32-pwm";
453				status = "disabled";
454				#pwm-cells = <3>;
455			};
456		};
457
458		timer12: timer@40001c00 {
459			compatible = "gd,gd32-timer";
460			reg = <0x40001c00 0x400>;
461			interrupts = <44 0>;
462			interrupt-names = "global";
463			clocks = <&cctl GD32_CLOCK_TIMER12>;
464			resets = <&rctl GD32_RESET_TIMER12>;
465			channels = <1>;
466			status = "disabled";
467
468			pwm {
469				compatible = "gd,gd32-pwm";
470				status = "disabled";
471				#pwm-cells = <3>;
472			};
473		};
474
475		timer13: timer@40002000 {
476			compatible = "gd,gd32-timer";
477			reg = <0x40002000 0x400>;
478			interrupts = <45 0>;
479			interrupt-names = "global";
480			clocks = <&cctl GD32_CLOCK_TIMER13>;
481			resets = <&rctl GD32_RESET_TIMER13>;
482			channels = <1>;
483			status = "disabled";
484
485			pwm {
486				compatible = "gd,gd32-pwm";
487				status = "disabled";
488				#pwm-cells = <3>;
489			};
490		};
491
492		dma0: dma@40020000 {
493			compatible = "gd,gd32-dma";
494			reg = <0x40020000 0x400>;
495			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
496				     <15 0>, <16 0>, <17 0>;
497			clocks = <&cctl GD32_CLOCK_DMA0>;
498			dma-channels = <7>;
499			gd,mem2mem;
500			#dma-cells = <2>;
501			status = "disabled";
502		};
503
504		dma1: dma@40020400 {
505			compatible = "gd,gd32-dma";
506			reg = <0x40020400 0x400>;
507			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
508				     <60 0>;
509			clocks = <&cctl GD32_CLOCK_DMA1>;
510			dma-channels = <5>;
511			gd,mem2mem;
512			#dma-cells = <2>;
513			status = "disabled";
514		};
515	};
516};
517
518&nvic {
519	arm,num-irq-priority-bits = <4>;
520};
521