1/*
2 * Copyright (c) 2022, Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12#include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
13#include <zephyr/dt-bindings/reset/gd32e50x.h>
14
15/ {
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-m33";
22			reg = <0>;
23			#address-cells = <1>;
24			#size-cells = <1>;
25			clock-frequency = <DT_FREQ_M(180)>;
26		};
27	};
28
29	soc {
30		sram0: memory@20000000 {
31			compatible = "mmio-sram";
32		};
33
34		rcu: reset-clock-controller@40021000 {
35			compatible = "gd,gd32-rcu";
36			reg = <0x40021000 0x400>;
37			status = "okay";
38
39			cctl: clock-controller {
40				compatible = "gd,gd32-cctl";
41				#clock-cells = <1>;
42				status = "okay";
43			};
44
45			rctl: reset-controller {
46				compatible = "gd,gd32-rctl";
47				#reset-cells = <1>;
48				status = "okay";
49			};
50		};
51
52		fmc: flash-controller@40022000 {
53			compatible = "gd,gd32-flash-controller";
54			reg = <0x40022000 0x400>;
55
56			#address-cells = <1>;
57			#size-cells = <1>;
58
59			flash0: flash@8000000 {
60				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
61				write-block-size = <2>;
62				/* GD32E50x DataSheet not defined the maximum page erase time
63				 * for flash memory.
64				 * From other GD32 DataSheets, we can find 1KB page normally have a
65				 * 300ms max time.
66				 * Assume GD32E50x use the worst implementation, set the max erase
67				 * time to 8 times of 1KB page.
68				 */
69				max-erase-time-ms = <2400>;
70				page-size = <DT_SIZE_K(8)>;
71			};
72		};
73
74		mpu: mpu@e000ed90 {
75			compatible = "arm,armv8m-mpu";
76			reg = <0xe000ed90 0x40>;
77		};
78
79		usart0: usart@40013800 {
80			compatible = "gd,gd32-usart";
81			reg = <0x40013800 0x400>;
82			interrupts = <37 0>;
83			clocks = <&cctl GD32_CLOCK_USART0>;
84			resets = <&rctl GD32_RESET_USART0>;
85			status = "disabled";
86		};
87
88		usart1: usart@40004400 {
89			compatible = "gd,gd32-usart";
90			reg = <0x40004400 0x400>;
91			interrupts = <38 0>;
92			clocks = <&cctl GD32_CLOCK_USART1>;
93			resets = <&rctl GD32_RESET_USART1>;
94			status = "disabled";
95		};
96
97		usart2: usart@40004800 {
98			compatible = "gd,gd32-usart";
99			reg = <0x40004800 0x400>;
100			interrupts = <39 0>;
101			clocks = <&cctl GD32_CLOCK_USART2>;
102			resets = <&rctl GD32_RESET_USART2>;
103			status = "disabled";
104		};
105
106		uart3: usart@40004c00 {
107			compatible = "gd,gd32-usart";
108			reg = <0x40004c00 0x400>;
109			interrupts = <52 0>;
110			clocks = <&cctl GD32_CLOCK_UART3>;
111			resets = <&rctl GD32_RESET_UART3>;
112			status = "disabled";
113		};
114
115		uart4: usart@40005000 {
116			compatible = "gd,gd32-usart";
117			reg = <0x40005000 0x400>;
118			interrupts = <53 0>;
119			clocks = <&cctl GD32_CLOCK_UART4>;
120			resets = <&rctl GD32_RESET_UART4>;
121			status = "disabled";
122		};
123
124		usart5: usart@40017000 {
125			compatible = "gd,gd32-usart";
126			reg = <0x40017000 0x400>;
127			interrupts = <84 0>, <86 0>;
128			interrupt-names = "global", "wkup";
129			clocks = <&cctl GD32_CLOCK_USART5>;
130			resets = <&rctl GD32_RESET_USART5>;
131			status = "disabled";
132		};
133
134		dac: dac@40007400 {
135			compatible = "gd,gd32-dac";
136			reg = <0x40007400 0x400>;
137			clocks = <&cctl GD32_CLOCK_DAC>;
138			resets = <&rctl GD32_RESET_DAC>;
139			num-channels = <2>;
140			status = "disabled";
141			#io-channel-cells = <1>;
142		};
143
144		i2c0: i2c@40005400 {
145			compatible = "gd,gd32-i2c";
146			reg = <0x40005400 0x400>;
147			#address-cells = <1>;
148			#size-cells = <0>;
149			clock-frequency = <I2C_BITRATE_STANDARD>;
150			interrupts = <31 0>, <32 0>;
151			interrupt-names = "event", "error";
152			clocks = <&cctl GD32_CLOCK_I2C0>;
153			resets = <&rctl GD32_RESET_I2C0>;
154			status = "disabled";
155		};
156
157		i2c1: i2c@40005800 {
158			compatible = "gd,gd32-i2c";
159			reg = <0x40005800 0x400>;
160			#address-cells = <1>;
161			#size-cells = <0>;
162			clock-frequency = <I2C_BITRATE_STANDARD>;
163			interrupts = <33 0>, <34 0>;
164			interrupt-names = "event", "error";
165			clocks = <&cctl GD32_CLOCK_I2C1>;
166			resets = <&rctl GD32_RESET_I2C1>;
167			status = "disabled";
168		};
169
170		i2c2: i2c@4000c000 {
171			compatible = "gd,gd32-i2c";
172			reg = <0x4000c000 0x400>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175			clock-frequency = <I2C_BITRATE_STANDARD>;
176			interrupts = <82 0>, <83 0>;
177			interrupt-names = "event", "error";
178			clocks = <&cctl GD32_CLOCK_I2C2>;
179			resets = <&rctl GD32_RESET_I2C2>;
180			status = "disabled";
181		};
182
183		exti: interrupt-controller@40010400 {
184			compatible = "gd,gd32-exti";
185			interrupt-controller;
186			#interrupt-cells = <1>;
187			reg = <0x40010400 0x400>;
188			num-lines = <22>;
189			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
190				     <10 0>, <23 0>, <40 0>;
191			interrupt-names = "line0", "line1", "line2", "line3",
192					  "line4", "line5-9", "line10-15";
193			status = "okay";
194		};
195
196		afio: afio@40010000 {
197			compatible = "gd,gd32-afio";
198			reg = <0x40010000 0x400>;
199			clocks = <&cctl GD32_CLOCK_AFIO>;
200			status = "okay";
201		};
202
203		fwdgt: watchdog@40003000 {
204			compatible = "gd,gd32-fwdgt";
205			reg = <0x40003000 0x400>;
206			status = "disabled";
207		};
208
209		wwdgt: watchdog@40002c00 {
210			compatible = "gd,gd32-wwdgt";
211			reg = <0x40002C00 0x400>;
212			clocks = <&cctl GD32_CLOCK_WWDGT>;
213			resets = <&rctl GD32_RESET_WWDGT>;
214			interrupts = <0 0>;
215			status = "disabled";
216		};
217
218		pinctrl: pin-controller@40010800 {
219			compatible = "gd,gd32-pinctrl-afio";
220			reg = <0x40010800 0x2400>;
221			#address-cells = <1>;
222			#size-cells = <1>;
223			status = "okay";
224
225			gpioa: gpio@40010800 {
226				compatible = "gd,gd32-gpio";
227				gpio-controller;
228				#gpio-cells = <2>;
229				reg = <0x40010800 0x400>;
230				clocks = <&cctl GD32_CLOCK_GPIOA>;
231				resets = <&rctl GD32_RESET_GPIOA>;
232				status = "disabled";
233			};
234
235			gpiob: gpio@40010c00 {
236				compatible = "gd,gd32-gpio";
237				gpio-controller;
238				#gpio-cells = <2>;
239				reg = <0x40010c00 0x400>;
240				clocks = <&cctl GD32_CLOCK_GPIOB>;
241				resets = <&rctl GD32_RESET_GPIOB>;
242				status = "disabled";
243			};
244
245			gpioc: gpio@40011000 {
246				compatible = "gd,gd32-gpio";
247				gpio-controller;
248				#gpio-cells = <2>;
249				reg = <0x40011000 0x400>;
250				clocks = <&cctl GD32_CLOCK_GPIOC>;
251				resets = <&rctl GD32_RESET_GPIOC>;
252				status = "disabled";
253			};
254
255			gpiod: gpio@40011400 {
256				compatible = "gd,gd32-gpio";
257				gpio-controller;
258				#gpio-cells = <2>;
259				reg = <0x40011400 0x400>;
260				clocks = <&cctl GD32_CLOCK_GPIOD>;
261				resets = <&rctl GD32_RESET_GPIOD>;
262				status = "disabled";
263			};
264
265			gpioe: gpio@40011800 {
266				compatible = "gd,gd32-gpio";
267				gpio-controller;
268				#gpio-cells = <2>;
269				reg = <0x40011800 0x400>;
270				clocks = <&cctl GD32_CLOCK_GPIOE>;
271				resets = <&rctl GD32_RESET_GPIOE>;
272				status = "disabled";
273			};
274
275			gpiof: gpio@40011c00 {
276				compatible = "gd,gd32-gpio";
277				gpio-controller;
278				#gpio-cells = <2>;
279				reg = <0x40011c00 0x400>;
280				clocks = <&cctl GD32_CLOCK_GPIOF>;
281				resets = <&rctl GD32_RESET_GPIOF>;
282				status = "disabled";
283			};
284
285			gpiog: gpio@40012000 {
286				compatible = "gd,gd32-gpio";
287				gpio-controller;
288				#gpio-cells = <2>;
289				reg = <0x40012000 0x400>;
290				clocks = <&cctl GD32_CLOCK_GPIOG>;
291				resets = <&rctl GD32_RESET_GPIOG>;
292				status = "disabled";
293			};
294		};
295
296		timer0: timer@40012c00 {
297			compatible = "gd,gd32-timer";
298			reg = <0x40012c00 0x400>;
299			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
300			interrupt-names = "brk", "up", "trgcom", "cc";
301			clocks = <&cctl GD32_CLOCK_TIMER0>;
302			resets = <&rctl GD32_RESET_TIMER0>;
303			is-advanced;
304			channels = <4>;
305			status = "disabled";
306
307			pwm {
308				compatible = "gd,gd32-pwm";
309				status = "disabled";
310				#pwm-cells = <3>;
311			};
312		};
313
314		timer1: timer@40000000 {
315			compatible = "gd,gd32-timer";
316			reg = <0x40000000 0x400>;
317			interrupts = <28 0>;
318			interrupt-names = "global";
319			clocks = <&cctl GD32_CLOCK_TIMER1>;
320			resets = <&rctl GD32_RESET_TIMER1>;
321			is-32bit;
322			channels = <4>;
323			status = "disabled";
324
325			pwm {
326				compatible = "gd,gd32-pwm";
327				status = "disabled";
328				#pwm-cells = <3>;
329			};
330		};
331
332		timer2: timer@40000400 {
333			compatible = "gd,gd32-timer";
334			reg = <0x40000400 0x400>;
335			interrupts = <29 0>;
336			interrupt-names = "global";
337			clocks = <&cctl GD32_CLOCK_TIMER2>;
338			resets = <&rctl GD32_RESET_TIMER2>;
339			channels = <4>;
340			status = "disabled";
341
342			pwm {
343				compatible = "gd,gd32-pwm";
344				status = "disabled";
345				#pwm-cells = <3>;
346			};
347		};
348
349		timer3: timer@40000800 {
350			compatible = "gd,gd32-timer";
351			reg = <0x40000800 0x400>;
352			interrupts = <30 0>;
353			interrupt-names = "global";
354			clocks = <&cctl GD32_CLOCK_TIMER3>;
355			resets = <&rctl GD32_RESET_TIMER3>;
356			channels = <4>;
357			status = "disabled";
358
359			pwm {
360				compatible = "gd,gd32-pwm";
361				status = "disabled";
362				#pwm-cells = <3>;
363			};
364		};
365
366		timer4: timer@40000c00 {
367			compatible = "gd,gd32-timer";
368			reg = <0x40000c00 0x400>;
369			interrupts = <50 0>;
370			interrupt-names = "global";
371			clocks = <&cctl GD32_CLOCK_TIMER4>;
372			resets = <&rctl GD32_RESET_TIMER4>;
373			is-32bit;
374			channels = <4>;
375			status = "disabled";
376
377			pwm {
378				compatible = "gd,gd32-pwm";
379				status = "disabled";
380				#pwm-cells = <3>;
381			};
382		};
383
384		timer5: timer@40001000 {
385			compatible = "gd,gd32-timer";
386			reg = <0x40001000 0x400>;
387			interrupts = <54 0>;
388			interrupt-names = "global";
389			clocks = <&cctl GD32_CLOCK_TIMER5>;
390			resets = <&rctl GD32_RESET_TIMER5>;
391			channels = <0>;
392			status = "disabled";
393		};
394
395		timer6: timer@40001400 {
396			compatible = "gd,gd32-timer";
397			reg = <0x40001400 0x400>;
398			interrupts = <55 0>;
399			interrupt-names = "global";
400			clocks = <&cctl GD32_CLOCK_TIMER6>;
401			resets = <&rctl GD32_RESET_TIMER6>;
402			channels = <0>;
403			status = "disabled";
404		};
405
406		dma0: dma@40020000 {
407			compatible = "gd,gd32-dma";
408			reg = <0x40020000 0x400>;
409			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
410				     <15 0>, <16 0>, <17 0>;
411			clocks = <&cctl GD32_CLOCK_DMA0>;
412			dma-channels = <7>;
413			gd,mem2mem;
414			#dma-cells = <2>;
415			status = "disabled";
416		};
417
418		dma1: dma@40020400 {
419			compatible = "gd,gd32-dma";
420			reg = <0x40020400 0x400>;
421			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
422				     <60 0>;
423			clocks = <&cctl GD32_CLOCK_DMA1>;
424			dma-channels = <5>;
425			gd,mem2mem;
426			#dma-cells = <2>;
427			status = "disabled";
428		};
429	};
430};
431
432&nvic {
433	arm,num-irq-priority-bits = <4>;
434};
435