1/*
2 * Copyright (c) 2018 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/f0/stm32f030X8.dtsi>
9
10/ {
11	sram0: memory@20000000 {
12		reg = <0x20000000 DT_SIZE_K(32)>;
13	};
14
15	soc {
16		flash-controller@40022000 {
17			flash0: flash@8000000 {
18				erase-block-size = <2048>;
19				reg = <0x08000000 DT_SIZE_K(256)>;
20			};
21		};
22
23		/*
24		 * USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
25		 * configuration is not currently supported, so at most one of
26		 * these may be enabled at a time. Enabling more than one will
27		 * result in a build failure.
28		 */
29		usart3: serial@40004800 {
30			compatible = "st,stm32-usart", "st,stm32-uart";
31			reg = <0x40004800 0x400>;
32			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
33			resets = <&rctl STM32_RESET(APB1, 18U)>;
34			interrupts = <29 0>;
35			status = "disabled";
36		};
37
38		usart4: serial@40004c00 {
39			compatible = "st,stm32-usart", "st,stm32-uart";
40			reg = <0x40004c00 0x400>;
41			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
42			resets = <&rctl STM32_RESET(APB1, 19U)>;
43			interrupts = <29 0>;
44			status = "disabled";
45		};
46
47		usart5: serial@40005000 {
48			compatible = "st,stm32-usart", "st,stm32-uart";
49			reg = <0x40005000 0x400>;
50			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
51			resets = <&rctl STM32_RESET(APB1, 20U)>;
52			interrupts = <29 0>;
53			status = "disabled";
54		};
55
56		usart6: serial@40011400 {
57			compatible = "st,stm32-usart", "st,stm32-uart";
58			reg = <0x40011400 0x400>;
59			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
60			resets = <&rctl STM32_RESET(APB2, 5U)>;
61			interrupts = <29 0>;
62			status = "disabled";
63		};
64
65		timers7: timers@40001400 {
66			compatible = "st,stm32-timers";
67			reg = <0x40001400 0x400>;
68			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
69			resets = <&rctl STM32_RESET(APB1, 5U)>;
70			interrupts = <18 0>;
71			interrupt-names = "global";
72			st,prescaler = <0>;
73			status = "disabled";
74		};
75	};
76};
77