1/*
2 * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32a50x.h>
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-m33f";
23			reg = <0>;
24			#address-cells = <1>;
25			#size-cells = <1>;
26			clock-frequency = <DT_FREQ_M(100)>;
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv8m-mpu";
30				reg = <0xe000ed90 0x40>;
31			};
32		};
33	};
34
35	soc {
36		sram0: memory@20000000 {
37			compatible = "mmio-sram";
38		};
39
40		rcu: reset-clock-controller@40021000 {
41			compatible = "gd,gd32-rcu";
42			reg = <0x40021000 0x400>;
43			status = "okay";
44
45			cctl: clock-controller {
46				compatible = "gd,gd32-cctl";
47				#clock-cells = <1>;
48				status = "okay";
49			};
50
51			rctl: reset-controller {
52				compatible = "gd,gd32-rctl";
53				#reset-cells = <1>;
54				status = "okay";
55			};
56		};
57
58		fmc: flash-controller@40022000 {
59			compatible = "gd,gd32-flash-controller";
60			reg = <0x40022000 0x400>;
61
62			#address-cells = <1>;
63			#size-cells = <1>;
64
65			flash0: flash@8000000 {
66				compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
67				write-block-size = <4>;
68				max-erase-time-ms = <2578>;
69				bank0-page-size = <DT_SIZE_K(1)>;
70				bank1-page-size = <DT_SIZE_K(1)>;
71			};
72		};
73
74		usart0: usart@40013800 {
75			compatible = "gd,gd32-usart";
76			reg = <0x40013800 0x400>;
77			interrupts = <37 0>;
78			clocks = <&cctl GD32_CLOCK_USART0>;
79			resets = <&rctl GD32_RESET_USART0>;
80			status = "disabled";
81		};
82
83		usart1: usart@40004400 {
84			compatible = "gd,gd32-usart";
85			reg = <0x40004400 0x400>;
86			interrupts = <38 0>;
87			clocks = <&cctl GD32_CLOCK_USART1>;
88			resets = <&rctl GD32_RESET_USART1>;
89			status = "disabled";
90		};
91
92		usart2: usart@40004800 {
93			compatible = "gd,gd32-usart";
94			reg = <0x40004800 0x400>;
95			interrupts = <39 0>;
96			clocks = <&cctl GD32_CLOCK_USART2>;
97			resets = <&rctl GD32_RESET_USART2>;
98			status = "disabled";
99		};
100
101		dac: dac@40007400 {
102			compatible = "gd,gd32-dac";
103			reg = <0x40007400 0x400>;
104			clocks = <&cctl GD32_CLOCK_DAC>;
105			resets = <&rctl GD32_RESET_DAC>;
106			num-channels = <1>;
107			status = "disabled";
108			#io-channel-cells = <1>;
109		};
110
111		i2c0: i2c@40005400 {
112			compatible = "gd,gd32-i2c";
113			reg = <0x40005400 0x400>;
114			#address-cells = <1>;
115			#size-cells = <0>;
116			clock-frequency = <I2C_BITRATE_STANDARD>;
117			interrupts = <31 0>, <32 0>;
118			interrupt-names = "event", "error";
119			clocks = <&cctl GD32_CLOCK_I2C0>;
120			resets = <&rctl GD32_RESET_I2C0>;
121			status = "disabled";
122		};
123
124		i2c1: i2c@40005800 {
125			compatible = "gd,gd32-i2c";
126			reg = <0x40005800 0x400>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129			clock-frequency = <I2C_BITRATE_STANDARD>;
130			interrupts = <33 0>, <34 0>;
131			interrupt-names = "event", "error";
132			clocks = <&cctl GD32_CLOCK_I2C1>;
133			resets = <&rctl GD32_RESET_I2C1>;
134			status = "disabled";
135		};
136
137		spi0: spi@40013000 {
138			compatible = "gd,gd32-spi";
139			reg = <0x40013000 0x400>;
140			interrupts = <35 0>;
141			clocks = <&cctl GD32_CLOCK_SPI0>;
142			resets = <&rctl GD32_RESET_SPI0>;
143			status = "disabled";
144			#address-cells = <1>;
145			#size-cells = <0>;
146		};
147
148		spi1: spi@40003800 {
149			compatible = "gd,gd32-spi";
150			reg = <0x40003800 0x400>;
151			interrupts = <36 0>;
152			clocks = <&cctl GD32_CLOCK_SPI1>;
153			resets = <&rctl GD32_RESET_SPI1>;
154			status = "disabled";
155			#address-cells = <1>;
156			#size-cells = <0>;
157		};
158
159		adc0: adc@40012400 {
160			compatible = "gd,gd32-adc";
161			reg = <0x40012400 0x100>;
162			interrupts = <18 0>;
163			clocks = <&cctl GD32_CLOCK_ADC0>;
164			resets = <&rctl GD32_RESET_ADC0>;
165			channels = <16>;
166			status = "disabled";
167			#io-channel-cells = <1>;
168		};
169
170		adc1: adc@40012800 {
171			compatible = "gd,gd32-adc";
172			reg = <0x40012800 0x100>;
173			interrupts = <18 0>;
174			clocks = <&cctl GD32_CLOCK_ADC1>;
175			resets = <&rctl GD32_RESET_ADC1>;
176			channels = <16>;
177			status = "disabled";
178			#io-channel-cells = <1>;
179		};
180
181		syscfg: syscfg@40010000 {
182			compatible = "gd,gd32-syscfg";
183			reg = <0x40010000 0x400>;
184			clocks = <&cctl GD32_CLOCK_SYSCFG>;
185		};
186
187		exti: interrupt-controller@40010400 {
188			compatible = "gd,gd32-exti";
189			interrupt-controller;
190			#interrupt-cells = <1>;
191			reg = <0x40010400 0x400>;
192			num-lines = <25>;
193			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
194				     <10 0>, <41 0>, <40 0>;
195			interrupt-names = "line0",  "line1", "line2", "line3",
196					  "line4", "line5-9", "line10-15";
197			status = "okay";
198		};
199
200		fwdgt: watchdog@40003000 {
201			compatible = "gd,gd32-fwdgt";
202			reg = <0x40003000 0x400>;
203			status = "disabled";
204		};
205
206		wwdgt: watchdog@40002c00 {
207			compatible = "gd,gd32-wwdgt";
208			reg = <0x40002C00 0x400>;
209			clocks = <&cctl GD32_CLOCK_WWDGT>;
210			resets = <&rctl GD32_RESET_WWDGT>;
211			interrupts = <0 0>;
212			status = "disabled";
213		};
214
215		pinctrl: pin-controller@48000000 {
216			compatible = "gd,gd32-pinctrl-af";
217			reg = <0x48000000 0x1800>;
218			#address-cells = <1>;
219			#size-cells = <1>;
220			status = "okay";
221
222			gpioa: gpio@48000000 {
223				compatible = "gd,gd32-gpio";
224				gpio-controller;
225				#gpio-cells = <2>;
226				reg = <0x48000000 0x400>;
227				clocks = <&cctl GD32_CLOCK_GPIOA>;
228				resets = <&rctl GD32_RESET_GPIOA>;
229				status = "disabled";
230			};
231
232			gpiob: gpio@48000400 {
233				compatible = "gd,gd32-gpio";
234				gpio-controller;
235				#gpio-cells = <2>;
236				reg = <0x48000400 0x400>;
237				clocks = <&cctl GD32_CLOCK_GPIOB>;
238				resets = <&rctl GD32_RESET_GPIOB>;
239				status = "disabled";
240			};
241
242			gpioc: gpio@48000800 {
243				compatible = "gd,gd32-gpio";
244				gpio-controller;
245				#gpio-cells = <2>;
246				reg = <0x48000800 0x400>;
247				clocks = <&cctl GD32_CLOCK_GPIOC>;
248				resets = <&rctl GD32_RESET_GPIOC>;
249				status = "disabled";
250			};
251
252			gpiod: gpio@48000c00 {
253				compatible = "gd,gd32-gpio";
254				gpio-controller;
255				#gpio-cells = <2>;
256				reg = <0x48000c00 0x400>;
257				clocks = <&cctl GD32_CLOCK_GPIOD>;
258				resets = <&rctl GD32_RESET_GPIOD>;
259				status = "disabled";
260			};
261
262			gpioe: gpio@48001000 {
263				compatible = "gd,gd32-gpio";
264				gpio-controller;
265				#gpio-cells = <2>;
266				reg = <0x48001000 0x400>;
267				clocks = <&cctl GD32_CLOCK_GPIOE>;
268				resets = <&rctl GD32_RESET_GPIOE>;
269				status = "disabled";
270			};
271
272			gpiof: gpio@48001400 {
273				compatible = "gd,gd32-gpio";
274				gpio-controller;
275				#gpio-cells = <2>;
276				reg = <0x48001400 0x400>;
277				clocks = <&cctl GD32_CLOCK_GPIOF>;
278				resets = <&rctl GD32_RESET_GPIOF>;
279				status = "disabled";
280			};
281		};
282
283		timer0: timer@40012c00 {
284			compatible = "gd,gd32-timer";
285			reg = <0x40012c00 0x400>;
286			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
287			interrupt-names = "brk", "up", "trgcom", "cc";
288			clocks = <&cctl GD32_CLOCK_TIMER0>;
289			resets = <&rctl GD32_RESET_TIMER0>;
290			is-advanced;
291			channels = <4>;
292			status = "disabled";
293
294			pwm {
295				compatible = "gd,gd32-pwm";
296				status = "disabled";
297				#pwm-cells = <3>;
298			};
299		};
300
301		timer1: timer@40000000 {
302			compatible = "gd,gd32-timer";
303			reg = <0x40000000 0x400>;
304			interrupts = <28 0>;
305			interrupt-names = "global";
306			clocks = <&cctl GD32_CLOCK_TIMER1>;
307			resets = <&rctl GD32_RESET_TIMER1>;
308			is-32bit;
309			channels = <4>;
310			status = "disabled";
311
312			pwm {
313				compatible = "gd,gd32-pwm";
314				status = "disabled";
315				#pwm-cells = <3>;
316			};
317		};
318
319		timer5: timer@40001000 {
320			compatible = "gd,gd32-timer";
321			reg = <0x40001000 0x400>;
322			interrupts = <54 0>;
323			interrupt-names = "global";
324			clocks = <&cctl GD32_CLOCK_TIMER5>;
325			resets = <&rctl GD32_RESET_TIMER5>;
326			channels = <0>;
327			status = "disabled";
328		};
329
330		timer6: timer@40001400 {
331			compatible = "gd,gd32-timer";
332			reg = <0x40001400 0x400>;
333			interrupts = <55 0>;
334			interrupt-names = "global";
335			clocks = <&cctl GD32_CLOCK_TIMER6>;
336			resets = <&rctl GD32_RESET_TIMER6>;
337			channels = <0>;
338			status = "disabled";
339		};
340
341		timer7: timer@40013400 {
342			compatible = "gd,gd32-timer";
343			reg = <0x40013400 0x400>;
344			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
345			interrupt-names = "brk", "up", "trgcom", "cc";
346			clocks = <&cctl GD32_CLOCK_TIMER7>;
347			resets = <&rctl GD32_RESET_TIMER7>;
348			is-advanced;
349			channels = <4>;
350			status = "disabled";
351
352			pwm {
353				compatible = "gd,gd32-pwm";
354				status = "disabled";
355				#pwm-cells = <3>;
356			};
357		};
358
359		timer19: timer@40015000 {
360			compatible = "gd,gd32-timer";
361			reg = <0x40015000 0x400>;
362			interrupts = <43 0>;
363			interrupt-names = "global";
364			clocks = <&cctl GD32_CLOCK_TIMER19>;
365			resets = <&rctl GD32_RESET_TIMER19>;
366			channels = <2>;
367			status = "disabled";
368
369			pwm {
370				compatible = "gd,gd32-pwm";
371				status = "disabled";
372				#pwm-cells = <3>;
373			};
374		};
375
376		timer20: timer@40015400 {
377			compatible = "gd,gd32-timer";
378			reg = <0x40015400 0x400>;
379			interrupts = <44 0>;
380			interrupt-names = "global";
381			clocks = <&cctl GD32_CLOCK_TIMER20>;
382			resets = <&rctl GD32_RESET_TIMER20>;
383			channels = <1>;
384			status = "disabled";
385
386			pwm {
387				compatible = "gd,gd32-pwm";
388				status = "disabled";
389				#pwm-cells = <3>;
390			};
391		};
392
393		dma0: dma@40020000 {
394			compatible = "gd,gd32-dma";
395			reg = <0x40020000 0x400>;
396			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
397				     <15 0>, <16 0>, <17 0>, <47 0>;
398			clocks = <&cctl GD32_CLOCK_DMA0>;
399			dma-channels = <7>;
400			gd,mem2mem;
401			#dma-cells = <2>;
402			status = "disabled";
403		};
404
405		dma1: dma@40020400 {
406			compatible = "gd,gd32-dma";
407			reg = <0x40020400 0x400>;
408			interrupts = <56 0>, <57 0>, <58 0>,
409				     <59 0>, <60 0>;
410			clocks = <&cctl GD32_CLOCK_DMA1>;
411			dma-channels = <5>;
412			gd,mem2mem;
413			#dma-cells = <2>;
414			status = "disabled";
415		};
416	};
417};
418
419&nvic {
420	arm,num-irq-priority-bits = <4>;
421};
422