1/*
2 * Copyright (c) 2022 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/clock/gd32l23x-clocks.h>
12#include <zephyr/dt-bindings/reset/gd32l23x.h>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-m23";
21			reg = <0>;
22			clock-frequency = <DT_FREQ_M(64)>;
23		};
24	};
25
26	soc {
27		sram0: memory@20000000 {
28			compatible = "mmio-sram";
29			reg = <0x20000000 DT_SIZE_K(16)>;
30		};
31
32		rcu: reset-clock-controller@40021000 {
33			compatible = "gd,gd32-rcu";
34			reg = <0x40021000 0x400>;
35			status = "okay";
36
37			cctl: clock-controller {
38				compatible = "gd,gd32-cctl";
39				#clock-cells = <1>;
40				status = "okay";
41			};
42
43			rctl: reset-controller {
44				compatible = "gd,gd32-rctl";
45				#reset-cells = <1>;
46				status = "okay";
47			};
48		};
49
50		syscfg: syscfg@40010000 {
51			compatible = "gd,gd32-syscfg";
52			reg = <0x40010000 0x400>;
53			clocks = <&cctl GD32_CLOCK_SYSCFG>;
54		};
55
56		fmc: flash-controller@40022000 {
57			compatible = "gd,gd32-flash-controller";
58			reg = <0x40022000 0x400>;
59
60			#address-cells = <1>;
61			#size-cells = <1>;
62
63			flash0: flash@8000000 {
64				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
65				write-block-size = <2>;
66			};
67		};
68
69		usart0: usart@40013800 {
70			compatible = "gd,gd32-usart";
71			reg = <0x40013800 0x400>;
72			interrupts = <27 0>;
73			clocks = <&cctl GD32_CLOCK_USART0>;
74			resets = <&rctl GD32_RESET_USART0>;
75			status = "disabled";
76		};
77
78		usart1: usart@40004400 {
79			compatible = "gd,gd32-usart";
80			reg = <0x40004400 0x400>;
81			interrupts = <28 0>;
82			clocks = <&cctl GD32_CLOCK_USART1>;
83			resets = <&rctl GD32_RESET_USART1>;
84			status = "disabled";
85		};
86
87		uart3: usart@40004c00 {
88			compatible = "gd,gd32-usart";
89			reg = <0x40004c00 0x400>;
90			interrupts = <39 0>;
91			clocks = <&cctl GD32_CLOCK_UART3>;
92			resets = <&rctl GD32_RESET_UART3>;
93			status = "disabled";
94		};
95
96		adc0: adc@40012400 {
97			compatible = "gd,gd32-adc";
98			reg = <0x40012400 0x400>;
99			interrupts = <18 0>;
100			clocks = <&cctl GD32_CLOCK_ADC>;
101			resets = <&rctl GD32_RESET_ADC>;
102			channels = <16>;
103			status = "disabled";
104			#io-channel-cells = <1>;
105		};
106
107		exti: interrupt-controller@40010400 {
108			compatible = "gd,gd32-exti";
109			interrupt-controller;
110			#interrupt-cells = <1>;
111			reg = <0x40010400 0x400>;
112			num-lines = <30>;
113			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
114				     <10 0>, <43 0>, <47 0>;
115			interrupt-names = "line0", "line1", "line2", "line3",
116					  "line4", "line5-9", "line10-15";
117			status = "okay";
118		};
119
120		pinctrl: pin-controller@48000000 {
121			compatible = "gd,gd32-pinctrl-af";
122			reg = <0x48000000 0x1400>;
123			#address-cells = <1>;
124			#size-cells = <1>;
125			status = "okay";
126
127			gpioa: gpio@48000000 {
128				compatible = "gd,gd32-gpio";
129				gpio-controller;
130				#gpio-cells = <2>;
131				reg = <0x48000000 0x400>;
132				clocks = <&cctl GD32_CLOCK_GPIOA>;
133				resets = <&rctl GD32_RESET_GPIOA>;
134				status = "disabled";
135			};
136
137			gpiob: gpio@48000400 {
138				compatible = "gd,gd32-gpio";
139				gpio-controller;
140				#gpio-cells = <2>;
141				reg = <0x48000400 0x400>;
142				clocks = <&cctl GD32_CLOCK_GPIOB>;
143				resets = <&rctl GD32_RESET_GPIOB>;
144				status = "disabled";
145			};
146
147			gpioc: gpio@48000800 {
148				compatible = "gd,gd32-gpio";
149				gpio-controller;
150				#gpio-cells = <2>;
151				reg = <0x48000800 0x400>;
152				clocks = <&cctl GD32_CLOCK_GPIOC>;
153				resets = <&rctl GD32_RESET_GPIOC>;
154				status = "disabled";
155			};
156
157			gpiod: gpio@48000c00 {
158				compatible = "gd,gd32-gpio";
159				gpio-controller;
160				#gpio-cells = <2>;
161				reg = <0x48000c00 0x400>;
162				clocks = <&cctl GD32_CLOCK_GPIOD>;
163				resets = <&rctl GD32_RESET_GPIOD>;
164				status = "disabled";
165			};
166
167			gpiof: gpio@48001400 {
168				compatible = "gd,gd32-gpio";
169				gpio-controller;
170				#gpio-cells = <2>;
171				reg = <0x48001400 0x400>;
172				clocks = <&cctl GD32_CLOCK_GPIOF>;
173				resets = <&rctl GD32_RESET_GPIOF>;
174				status = "disabled";
175			};
176		};
177
178	};
179};
180
181&nvic {
182	arm,num-irq-priority-bits = <2>;
183};
184