1/*
2 * Copyright (c) 2021, Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12#include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
13#include <zephyr/dt-bindings/reset/gd32f4xx.h>
14
15/ {
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			compatible = "arm,cortex-m4f";
22			reg = <0>;
23			#address-cells = <1>;
24			#size-cells = <1>;
25
26			mpu: mpu@e000ed90 {
27				compatible = "arm,armv7m-mpu";
28				reg = <0xe000ed90 0x40>;
29			};
30		};
31	};
32
33	soc {
34		sram0: memory@20000000 {
35			compatible = "mmio-sram";
36			reg = <0x20000000 DT_SIZE_K(112)>;
37		};
38
39		rcu: reset-clock-controller@40023800 {
40			compatible = "gd,gd32-rcu";
41			reg = <0x40023800 0x400>;
42			status = "okay";
43
44			cctl: clock-controller {
45				compatible = "gd,gd32-cctl";
46				#clock-cells = <1>;
47				status = "okay";
48			};
49
50			rctl: reset-controller {
51				compatible = "gd,gd32-rctl";
52				#reset-cells = <1>;
53				status = "okay";
54			};
55		};
56
57		fmc: flash-controller@40023c00 {
58			compatible = "gd,gd32-flash-controller";
59			reg = <0x40023c00 0x400>;
60
61			#address-cells = <1>;
62			#size-cells = <1>;
63
64			flash0: flash@8000000 {
65				compatible = "gd,gd32-nv-flash-v3", "soc-nv-flash";
66				write-block-size = <2>;
67				max-erase-time-ms = <8000>;
68			};
69		};
70
71		usart0: usart@40011000 {
72			compatible = "gd,gd32-usart";
73			reg = <0x40011000 0x400>;
74			interrupts = <37 0>;
75			clocks = <&cctl GD32_CLOCK_USART0>;
76			resets = <&rctl GD32_RESET_USART0>;
77			status = "disabled";
78		};
79
80		usart1: usart@40004400 {
81			compatible = "gd,gd32-usart";
82			reg = <0x40004400 0x400>;
83			interrupts = <38 0>;
84			clocks = <&cctl GD32_CLOCK_USART1>;
85			resets = <&rctl GD32_RESET_USART1>;
86			status = "disabled";
87		};
88
89		usart2: usart@40004800 {
90			compatible = "gd,gd32-usart";
91			reg = <0x40004800 0x400>;
92			interrupts = <39 0>;
93			clocks = <&cctl GD32_CLOCK_USART2>;
94			resets = <&rctl GD32_RESET_USART2>;
95			status = "disabled";
96		};
97
98		uart3: usart@40004c00 {
99			compatible = "gd,gd32-usart";
100			reg = <0x40004c00 0x400>;
101			interrupts = <52 0>;
102			clocks = <&cctl GD32_CLOCK_UART3>;
103			resets = <&rctl GD32_RESET_UART3>;
104			status = "disabled";
105		};
106
107		uart4: usart@40005000 {
108			compatible = "gd,gd32-usart";
109			reg = <0x40005000 0x400>;
110			interrupts = <53 0>;
111			clocks = <&cctl GD32_CLOCK_UART4>;
112			resets = <&rctl GD32_RESET_UART4>;
113			status = "disabled";
114		};
115
116		usart5: usart@40011400 {
117			compatible = "gd,gd32-usart";
118			reg = <0x40011400 0x400>;
119			interrupts = <71 0>;
120			clocks = <&cctl GD32_CLOCK_USART5>;
121			resets = <&rctl GD32_RESET_USART5>;
122			status = "disabled";
123		};
124
125		uart6: usart@40007800 {
126			compatible = "gd,gd32-usart";
127			reg = <0x40007800 0x400>;
128			interrupts = <82 0>;
129			clocks = <&cctl GD32_CLOCK_UART6>;
130			resets = <&rctl GD32_RESET_UART6>;
131			status = "disabled";
132		};
133
134		uart7: usart@40007c00 {
135			compatible = "gd,gd32-usart";
136			reg = <0x40007c00 0x400>;
137			interrupts = <83 0>;
138			clocks = <&cctl GD32_CLOCK_UART7>;
139			resets = <&rctl GD32_RESET_UART7>;
140			status = "disabled";
141		};
142
143		dac: dac@40007400 {
144			compatible = "gd,gd32-dac";
145			reg = <0x40007400 0x400>;
146			clocks = <&cctl GD32_CLOCK_DAC>;
147			resets = <&rctl GD32_RESET_DAC>;
148			num-channels = <2>;
149			status = "disabled";
150			#io-channel-cells = <1>;
151		};
152
153		i2c0: i2c@40005400 {
154			compatible = "gd,gd32-i2c";
155			reg = <0x40005400 0x400>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158			clock-frequency = <I2C_BITRATE_STANDARD>;
159			interrupts = <31 0>, <32 0>;
160			interrupt-names = "event", "error";
161			clocks = <&cctl GD32_CLOCK_I2C0>;
162			resets = <&rctl GD32_RESET_I2C0>;
163			status = "disabled";
164		};
165
166		i2c1: i2c@40005800 {
167			compatible = "gd,gd32-i2c";
168			reg = <0x40005800 0x400>;
169			#address-cells = <1>;
170			#size-cells = <0>;
171			clock-frequency = <I2C_BITRATE_STANDARD>;
172			interrupts = <33 0>, <34 0>;
173			interrupt-names = "event", "error";
174			clocks = <&cctl GD32_CLOCK_I2C1>;
175			resets = <&rctl GD32_RESET_I2C1>;
176			status = "disabled";
177		};
178
179		i2c2: i2c@40005c00 {
180			compatible = "gd,gd32-i2c";
181			reg = <0x40005c00 0x400>;
182			#address-cells = <1>;
183			#size-cells = <0>;
184			clock-frequency = <I2C_BITRATE_STANDARD>;
185			interrupts = <72 0>, <73 0>;
186			interrupt-names = "event", "error";
187			clocks = <&cctl GD32_CLOCK_I2C2>;
188			resets = <&rctl GD32_RESET_I2C2>;
189			status = "disabled";
190		};
191
192		spi0: spi@40013000 {
193			compatible = "gd,gd32-spi";
194			reg = <0x40013000 0x400>;
195			interrupts = <35 0>;
196			clocks = <&cctl GD32_CLOCK_SPI0>;
197			resets = <&rctl GD32_RESET_SPI0>;
198			status = "disabled";
199			#address-cells = <1>;
200			#size-cells = <0>;
201		};
202
203		spi1: spi@40003800 {
204			compatible = "gd,gd32-spi";
205			reg = <0x40003800 0x400>;
206			interrupts = <36 0>;
207			clocks = <&cctl GD32_CLOCK_SPI1>;
208			resets = <&rctl GD32_RESET_SPI1>;
209			status = "disabled";
210			#address-cells = <1>;
211			#size-cells = <0>;
212		};
213
214		spi2: spi@40003c00 {
215			compatible = "gd,gd32-spi";
216			reg = <0x40003c00 0x400>;
217			interrupts = <51 0>;
218			clocks = <&cctl GD32_CLOCK_SPI2>;
219			resets = <&rctl GD32_RESET_SPI2>;
220			status = "disabled";
221			#address-cells = <1>;
222			#size-cells = <0>;
223		};
224
225		adc0: adc@40012000 {
226			compatible = "gd,gd32-adc";
227			reg = <0x40012000 0x100>;
228			interrupts = <18 0>;
229			clocks = <&cctl GD32_CLOCK_ADC0>;
230			resets = <&rctl GD32_RESET_ADC0>;
231			channels = <16>;
232			status = "disabled";
233			#io-channel-cells = <1>;
234		};
235
236		adc1: adc@40012100 {
237			compatible = "gd,gd32-adc";
238			reg = <0x40012100 0x100>;
239			interrupts = <18 0>;
240			clocks = <&cctl GD32_CLOCK_ADC1>;
241			resets = <&rctl GD32_RESET_ADC1>;
242			channels = <16>;
243			status = "disabled";
244			#io-channel-cells = <1>;
245		};
246
247		adc2: adc@40012200 {
248			compatible = "gd,gd32-adc";
249			reg = <0x40012200 0x100>;
250			interrupts = <18 0>;
251			clocks = <&cctl GD32_CLOCK_ADC2>;
252			resets = <&rctl GD32_RESET_ADC2>;
253			channels = <16>;
254			status = "disabled";
255			#io-channel-cells = <1>;
256		};
257
258		syscfg: syscfg@40013800 {
259			compatible = "gd,gd32-syscfg";
260			reg = <0x40013800 0x400>;
261			clocks = <&cctl GD32_CLOCK_SYSCFG>;
262		};
263
264		exti: interrupt-controller@40013c00 {
265			compatible = "gd,gd32-exti";
266			interrupt-controller;
267			#interrupt-cells = <1>;
268			reg = <0x40013c00 0x400>;
269			num-lines = <23>;
270			interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
271				     <40 0>;
272			interrupt-names = "line0", "line1", "line2", "line3",
273					  "line4", "line5-9", "line10-15";
274			status = "okay";
275		};
276
277		fwdgt: watchdog@40003000 {
278			compatible = "gd,gd32-fwdgt";
279			reg = <0x40003000 0x400>;
280			status = "disabled";
281		};
282
283		wwdgt: watchdog@40002c00 {
284			compatible = "gd,gd32-wwdgt";
285			reg = <0x40002C00 0x400>;
286			clocks = <&cctl GD32_CLOCK_WWDGT>;
287			resets = <&rctl GD32_RESET_WWDGT>;
288			interrupts = <0 0>;
289			status = "disabled";
290		};
291
292		pinctrl: pin-controller@40020000 {
293			compatible = "gd,gd32-pinctrl-af";
294			reg = <0x40020000 0x2400>;
295			#address-cells = <1>;
296			#size-cells = <1>;
297			status = "okay";
298
299			gpioa: gpio@40020000 {
300				compatible = "gd,gd32-gpio";
301				gpio-controller;
302				#gpio-cells = <2>;
303				reg = <0x40020000 0x400>;
304				clocks = <&cctl GD32_CLOCK_GPIOA>;
305				resets = <&rctl GD32_RESET_GPIOA>;
306				status = "disabled";
307			};
308
309			gpiob: gpio@40020400 {
310				compatible = "gd,gd32-gpio";
311				gpio-controller;
312				#gpio-cells = <2>;
313				reg = <0x40020400 0x400>;
314				clocks = <&cctl GD32_CLOCK_GPIOB>;
315				resets = <&rctl GD32_RESET_GPIOB>;
316				status = "disabled";
317			};
318
319			gpioc: gpio@40020800 {
320				compatible = "gd,gd32-gpio";
321				gpio-controller;
322				#gpio-cells = <2>;
323				reg = <0x40020800 0x400>;
324				clocks = <&cctl GD32_CLOCK_GPIOC>;
325				resets = <&rctl GD32_RESET_GPIOC>;
326				status = "disabled";
327			};
328
329			gpiod: gpio@40020c00 {
330				compatible = "gd,gd32-gpio";
331				gpio-controller;
332				#gpio-cells = <2>;
333				reg = <0x40020c00 0x400>;
334				clocks = <&cctl GD32_CLOCK_GPIOD>;
335				resets = <&rctl GD32_RESET_GPIOD>;
336				status = "disabled";
337			};
338
339			gpioe: gpio@40021000 {
340				compatible = "gd,gd32-gpio";
341				gpio-controller;
342				#gpio-cells = <2>;
343				reg = <0x40021000 0x400>;
344				clocks = <&cctl GD32_CLOCK_GPIOE>;
345				resets = <&rctl GD32_RESET_GPIOE>;
346				status = "disabled";
347			};
348
349			gpiof: gpio@40021400 {
350				compatible = "gd,gd32-gpio";
351				gpio-controller;
352				#gpio-cells = <2>;
353				reg = <0x40021400 0x400>;
354				clocks = <&cctl GD32_CLOCK_GPIOF>;
355				resets = <&rctl GD32_RESET_GPIOF>;
356				status = "disabled";
357			};
358
359			gpiog: gpio@40021800 {
360				compatible = "gd,gd32-gpio";
361				gpio-controller;
362				#gpio-cells = <2>;
363				reg = <0x40021800 0x400>;
364				clocks = <&cctl GD32_CLOCK_GPIOG>;
365				resets = <&rctl GD32_RESET_GPIOG>;
366				status = "disabled";
367			};
368
369			gpioh: gpio@40021c00 {
370				compatible = "gd,gd32-gpio";
371				gpio-controller;
372				#gpio-cells = <2>;
373				reg = <0x40021c00 0x400>;
374				clocks = <&cctl GD32_CLOCK_GPIOH>;
375				resets = <&rctl GD32_RESET_GPIOH>;
376				status = "disabled";
377			};
378
379			gpioi: gpio@40022000 {
380				compatible = "gd,gd32-gpio";
381				gpio-controller;
382				#gpio-cells = <2>;
383				reg = <0x40022000 0x400>;
384				clocks = <&cctl GD32_CLOCK_GPIOI>;
385				resets = <&rctl GD32_RESET_GPIOI>;
386				status = "disabled";
387			};
388		};
389
390		timer0: timer@40010000 {
391			compatible = "gd,gd32-timer";
392			reg = <0x40010000 0x400>;
393			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
394			interrupt-names = "brk", "up", "trgcom", "cc";
395			clocks = <&cctl GD32_CLOCK_TIMER0>;
396			resets = <&rctl GD32_RESET_TIMER0>;
397			is-advanced;
398			channels = <4>;
399			status = "disabled";
400
401			pwm {
402				compatible = "gd,gd32-pwm";
403				status = "disabled";
404				#pwm-cells = <3>;
405			};
406		};
407
408		timer1: timer@40000000 {
409			compatible = "gd,gd32-timer";
410			reg = <0x40000000 0x400>;
411			interrupts = <28 0>;
412			interrupt-names = "global";
413			clocks = <&cctl GD32_CLOCK_TIMER1>;
414			resets = <&rctl GD32_RESET_TIMER1>;
415			is-32bit;
416			channels = <4>;
417			status = "disabled";
418
419			pwm {
420				compatible = "gd,gd32-pwm";
421				status = "disabled";
422				#pwm-cells = <3>;
423			};
424		};
425
426		timer2: timer@40000400 {
427			compatible = "gd,gd32-timer";
428			reg = <0x40000400 0x400>;
429			interrupts = <29 0>;
430			interrupt-names = "global";
431			clocks = <&cctl GD32_CLOCK_TIMER2>;
432			resets = <&rctl GD32_RESET_TIMER2>;
433			channels = <4>;
434			status = "disabled";
435
436			pwm {
437				compatible = "gd,gd32-pwm";
438				status = "disabled";
439				#pwm-cells = <3>;
440			};
441		};
442
443		timer3: timer@40000800 {
444			compatible = "gd,gd32-timer";
445			reg = <0x40000800 0x400>;
446			interrupts = <30 0>;
447			interrupt-names = "global";
448			clocks = <&cctl GD32_CLOCK_TIMER3>;
449			resets = <&rctl GD32_RESET_TIMER3>;
450			channels = <4>;
451			status = "disabled";
452
453			pwm {
454				compatible = "gd,gd32-pwm";
455				status = "disabled";
456				#pwm-cells = <3>;
457			};
458		};
459
460		timer4: timer@40000c00 {
461			compatible = "gd,gd32-timer";
462			reg = <0x40000c00 0x400>;
463			interrupts = <50 0>;
464			interrupt-names = "global";
465			clocks = <&cctl GD32_CLOCK_TIMER4>;
466			resets = <&rctl GD32_RESET_TIMER4>;
467			is-32bit;
468			channels = <4>;
469			status = "disabled";
470
471			pwm {
472				compatible = "gd,gd32-pwm";
473				status = "disabled";
474				#pwm-cells = <3>;
475			};
476		};
477
478		timer5: timer@40001000 {
479			compatible = "gd,gd32-timer";
480			reg = <0x40001000 0x400>;
481			interrupts = <54 0>;
482			interrupt-names = "global";
483			clocks = <&cctl GD32_CLOCK_TIMER5>;
484			resets = <&rctl GD32_RESET_TIMER5>;
485			channels = <0>;
486			status = "disabled";
487		};
488
489		timer6: timer@40001400 {
490			compatible = "gd,gd32-timer";
491			reg = <0x40001400 0x400>;
492			interrupts = <55 0>;
493			interrupt-names = "global";
494			clocks = <&cctl GD32_CLOCK_TIMER6>;
495			resets = <&rctl GD32_RESET_TIMER6>;
496			channels = <0>;
497			status = "disabled";
498		};
499
500		timer7: timer@40010400 {
501			compatible = "gd,gd32-timer";
502			reg = <0x40010400 0x400>;
503			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
504			interrupt-names = "brk", "up", "trgcom", "cc";
505			clocks = <&cctl GD32_CLOCK_TIMER7>;
506			resets = <&rctl GD32_RESET_TIMER7>;
507			is-advanced;
508			channels = <4>;
509			status = "disabled";
510
511			pwm {
512				compatible = "gd,gd32-pwm";
513				status = "disabled";
514				#pwm-cells = <3>;
515			};
516		};
517
518		timer8: timer@40014000 {
519			compatible = "gd,gd32-timer";
520			reg = <0x40014000 0x400>;
521			interrupts = <24 0>;
522			interrupt-names = "global";
523			clocks = <&cctl GD32_CLOCK_TIMER8>;
524			resets = <&rctl GD32_RESET_TIMER8>;
525			channels = <2>;
526			status = "disabled";
527
528			pwm {
529				compatible = "gd,gd32-pwm";
530				status = "disabled";
531				#pwm-cells = <3>;
532			};
533		};
534
535		timer9: timer@40014400 {
536			compatible = "gd,gd32-timer";
537			reg = <0x40014400 0x400>;
538			interrupts = <25 0>;
539			interrupt-names = "global";
540			clocks = <&cctl GD32_CLOCK_TIMER9>;
541			resets = <&rctl GD32_RESET_TIMER9>;
542			channels = <1>;
543			status = "disabled";
544
545			pwm {
546				compatible = "gd,gd32-pwm";
547				status = "disabled";
548				#pwm-cells = <3>;
549			};
550		};
551
552		timer10: timer@40014800 {
553			compatible = "gd,gd32-timer";
554			reg = <0x40014800 0x400>;
555			interrupts = <26 0>;
556			interrupt-names = "global";
557			clocks = <&cctl GD32_CLOCK_TIMER10>;
558			resets = <&rctl GD32_RESET_TIMER10>;
559			channels = <1>;
560			status = "disabled";
561
562			pwm {
563				compatible = "gd,gd32-pwm";
564				status = "disabled";
565				#pwm-cells = <3>;
566			};
567		};
568
569		timer11: timer@40001800 {
570			compatible = "gd,gd32-timer";
571			reg = <0x40001800 0x400>;
572			interrupts = <43 0>;
573			interrupt-names = "global";
574			clocks = <&cctl GD32_CLOCK_TIMER11>;
575			resets = <&rctl GD32_RESET_TIMER11>;
576			channels = <2>;
577			status = "disabled";
578
579			pwm {
580				compatible = "gd,gd32-pwm";
581				status = "disabled";
582				#pwm-cells = <3>;
583			};
584		};
585
586		timer12: timer@40001c00 {
587			compatible = "gd,gd32-timer";
588			reg = <0x40001c00 0x400>;
589			interrupts = <44 0>;
590			interrupt-names = "global";
591			clocks = <&cctl GD32_CLOCK_TIMER12>;
592			resets = <&rctl GD32_RESET_TIMER12>;
593			channels = <1>;
594			status = "disabled";
595
596			pwm {
597				compatible = "gd,gd32-pwm";
598				status = "disabled";
599				#pwm-cells = <3>;
600			};
601		};
602
603		timer13: timer@40002000 {
604			compatible = "gd,gd32-timer";
605			reg = <0x40002000 0x400>;
606			interrupts = <45 0>;
607			interrupt-names = "global";
608			clocks = <&cctl GD32_CLOCK_TIMER13>;
609			resets = <&rctl GD32_RESET_TIMER13>;
610			channels = <1>;
611			status = "disabled";
612
613			pwm {
614				compatible = "gd,gd32-pwm";
615				status = "disabled";
616				#pwm-cells = <3>;
617			};
618		};
619
620		dma0: dma@40026000 {
621			compatible = "gd,gd32-dma-v1";
622			reg = <0x40026000 0x400>;
623			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
624				     <15 0>, <16 0>, <17 0>, <47 0>;
625			clocks = <&cctl GD32_CLOCK_DMA0>;
626			resets = <&rctl GD32_RESET_DMA0>;
627			dma-channels = <8>;
628			gd,mem2mem;
629			#dma-cells = <4>;
630			status = "disabled";
631		};
632
633		dma1: dma@40026400 {
634			compatible = "gd,gd32-dma-v1";
635			reg = <0x40026400 0x400>;
636			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
637				     <60 0>, <68 0>, <69 0>, <70 0>;
638			clocks = <&cctl GD32_CLOCK_DMA1>;
639			resets = <&rctl GD32_RESET_DMA1>;
640			dma-channels = <8>;
641			gd,mem2mem;
642			#dma-cells = <4>;
643			status = "disabled";
644		};
645	};
646};
647
648&nvic {
649	arm,num-irq-priority-bits = <4>;
650};
651