Lines Matching refs:rctl
50 rctl: reset-controller { label
51 compatible = "gd,gd32-rctl";
76 resets = <&rctl GD32_RESET_USART0>;
85 resets = <&rctl GD32_RESET_USART1>;
94 resets = <&rctl GD32_RESET_USART2>;
103 resets = <&rctl GD32_RESET_UART3>;
112 resets = <&rctl GD32_RESET_UART4>;
121 resets = <&rctl GD32_RESET_USART5>;
130 resets = <&rctl GD32_RESET_UART6>;
139 resets = <&rctl GD32_RESET_UART7>;
147 resets = <&rctl GD32_RESET_DAC>;
162 resets = <&rctl GD32_RESET_I2C0>;
175 resets = <&rctl GD32_RESET_I2C1>;
188 resets = <&rctl GD32_RESET_I2C2>;
197 resets = <&rctl GD32_RESET_SPI0>;
208 resets = <&rctl GD32_RESET_SPI1>;
219 resets = <&rctl GD32_RESET_SPI2>;
230 resets = <&rctl GD32_RESET_ADC0>;
241 resets = <&rctl GD32_RESET_ADC1>;
252 resets = <&rctl GD32_RESET_ADC2>;
287 resets = <&rctl GD32_RESET_WWDGT>;
305 resets = <&rctl GD32_RESET_GPIOA>;
315 resets = <&rctl GD32_RESET_GPIOB>;
325 resets = <&rctl GD32_RESET_GPIOC>;
335 resets = <&rctl GD32_RESET_GPIOD>;
345 resets = <&rctl GD32_RESET_GPIOE>;
355 resets = <&rctl GD32_RESET_GPIOF>;
365 resets = <&rctl GD32_RESET_GPIOG>;
375 resets = <&rctl GD32_RESET_GPIOH>;
385 resets = <&rctl GD32_RESET_GPIOI>;
396 resets = <&rctl GD32_RESET_TIMER0>;
414 resets = <&rctl GD32_RESET_TIMER1>;
432 resets = <&rctl GD32_RESET_TIMER2>;
449 resets = <&rctl GD32_RESET_TIMER3>;
466 resets = <&rctl GD32_RESET_TIMER4>;
484 resets = <&rctl GD32_RESET_TIMER5>;
495 resets = <&rctl GD32_RESET_TIMER6>;
506 resets = <&rctl GD32_RESET_TIMER7>;
524 resets = <&rctl GD32_RESET_TIMER8>;
541 resets = <&rctl GD32_RESET_TIMER9>;
558 resets = <&rctl GD32_RESET_TIMER10>;
575 resets = <&rctl GD32_RESET_TIMER11>;
592 resets = <&rctl GD32_RESET_TIMER12>;
609 resets = <&rctl GD32_RESET_TIMER13>;
626 resets = <&rctl GD32_RESET_DMA0>;
639 resets = <&rctl GD32_RESET_DMA1>;