1/* SPDX-License-Identifier: Apache-2.0
2 *
3 * Copyright (c) 2020 Google, LLC
4 *
5 * SoC device tree include for STM32F103xG SoCs
6 * where 'x' is replaced for specific SoCs like {R,V,Z}
7 */
8
9#include <mem.h>
10#include <st/f1/stm32f103Xe.dtsi>
11
12/ {
13	sram0: memory@20000000 {
14		reg = <0x20000000 DT_SIZE_K(96)>;
15	};
16
17	soc {
18		flash-controller@40022000 {
19			flash0: flash@8000000 {
20				/* Note that there are actually two banks of
21				 * flash (512KB each) and two flash controllers.
22				 * This matters if you're doing in-application
23				 * flash programming and you need the
24				 * read-while-write capabilities, but is
25				 * otherwise a non-issue.
26				 */
27				reg = <0x08000000 DT_SIZE_K(1024)>;
28				erase-block-size = <DT_SIZE_K(2)>;
29			};
30		};
31
32		timers9: timers@40014c00 {
33			compatible = "st,stm32-timers";
34			reg = <0x40014c00 0x400>;
35			clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
36			resets = <&rctl STM32_RESET(APB2, 19U)>;
37			/* Shared with TIM1_BRK */
38			interrupts = <24 0>;
39			st,prescaler = <0>;
40			status = "disabled";
41
42			pwm {
43				compatible = "st,stm32-pwm";
44				status = "disabled";
45				#pwm-cells = <3>;
46			};
47		};
48
49		timers10: timers@40015000 {
50			compatible = "st,stm32-timers";
51			reg = <0x40015000 0x400>;
52			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
53			resets = <&rctl STM32_RESET(APB2, 20U)>;
54			/* Shared with TIM1_UP */
55			interrupts = <25 0>;
56			st,prescaler = <0>;
57			status = "disabled";
58
59			pwm {
60				compatible = "st,stm32-pwm";
61				status = "disabled";
62				#pwm-cells = <3>;
63			};
64		};
65
66		timers11: timers@40015400 {
67			compatible = "st,stm32-timers";
68			reg = <0x40015400 0x400>;
69			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
70			resets = <&rctl STM32_RESET(APB2, 21U)>;
71			/* Shared with TIM1_TRG_COM */
72			interrupts = <26 0>;
73			st,prescaler = <0>;
74			status = "disabled";
75
76			pwm {
77				compatible = "st,stm32-pwm";
78				status = "disabled";
79				#pwm-cells = <3>;
80			};
81		};
82
83		timers12: timers@40001800 {
84			compatible = "st,stm32-timers";
85			reg = <0x40001800 0x400>;
86			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
87			resets = <&rctl STM32_RESET(APB1, 6U)>;
88			/* Shared with TIM8_BRK */
89			interrupts = <43 0>;
90			st,prescaler = <0>;
91			status = "disabled";
92
93			pwm {
94				compatible = "st,stm32-pwm";
95				status = "disabled";
96				#pwm-cells = <3>;
97			};
98		};
99
100		timers13: timers@40001c00 {
101			compatible = "st,stm32-timers";
102			reg = <0x40001c00 0x400>;
103			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
104			resets = <&rctl STM32_RESET(APB1, 7U)>;
105			/* Shared with TIM8_UP */
106			interrupts = <44 0>;
107			st,prescaler = <0>;
108			status = "disabled";
109
110			pwm {
111				compatible = "st,stm32-pwm";
112				status = "disabled";
113				#pwm-cells = <3>;
114			};
115		};
116
117		timers14: timers@40002000 {
118			compatible = "st,stm32-timers";
119			reg = <0x40002000 0x400>;
120			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
121			resets = <&rctl STM32_RESET(APB1, 8U)>;
122			/* Shared with TIM8_TRG_COM */
123			interrupts = <45 0>;
124			st,prescaler = <0>;
125			status = "disabled";
126
127			pwm {
128				compatible = "st,stm32-pwm";
129				status = "disabled";
130				#pwm-cells = <3>;
131			};
132		};
133
134	};
135};
136