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Searched +full:xtal +full:- +full:freq (Results 1 – 25 of 27) sorted by relevance

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/Zephyr-latest/dts/bindings/cpu/
Despressif,riscv.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Espressif RISC-V CPU
11 clock-source:
16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
19 - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
22 - 0
23 - 1
24 - 2
26 xtal-freq:
[all …]
Despressif,xtensa-lx6.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,xtensa-lx6"
8 include: cdns,tensilica-xtensa-lx6.yaml
11 clock-source:
16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
19 - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
23 - 0
24 - 1
[all …]
Despressif,xtensa-lx7.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "espressif,xtensa-lx7"
8 include: cdns,tensilica-xtensa-lx7.yaml
11 clock-source:
16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
17 - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either
19 - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
23 - 0
24 - 1
[all …]
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_pmc.h5 * SPDX-License-Identifier: Apache-2.0
116 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | reg_val; in soc_pmc_mck_set_prescaler()
118 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_prescaler()
152 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | reg_val; in soc_pmc_mck_set_divider()
154 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_divider()
167 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | (uint32_t)source; in soc_pmc_mck_set_source()
169 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { in soc_pmc_mck_set_source()
176 * @param freq the internal fast RC desired frequency 4/8/12MHz.
178 static ALWAYS_INLINE void soc_pmc_switch_mainck_to_fastrc(enum soc_pmc_fast_rc_freq freq) in soc_pmc_switch_mainck_to_fastrc() argument
181 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN; in soc_pmc_switch_mainck_to_fastrc()
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc1200.c1 /* ieee802154_cc1200.c - TI CC1200 driver */
8 * SPDX-License-Identifier: Apache-2.0
80 const struct cc1200_config *config = dev->config; in z_cc1200_access_reg()
118 return (spi_transceive_dt(&config->bus, &tx, &rx) == 0); in z_cc1200_access_reg()
124 return (spi_write_dt(&config->bus, &tx) == 0); in z_cc1200_access_reg()
129 struct cc1200_context *cc1200 = dev->data; in get_mac()
132 sys_rand_get(&cc1200->mac_addr[4], 4U); in get_mac()
134 cc1200->mac_addr[7] = (cc1200->mac_addr[7] & ~0x01) | 0x02; in get_mac()
136 cc1200->mac_addr[4] = CONFIG_IEEE802154_CC1200_MAC4; in get_mac()
137 cc1200->mac_addr[5] = CONFIG_IEEE802154_CC1200_MAC5; in get_mac()
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.defconfig2 # SPDX-License-Identifier: Apache-2.0
26 default $(dt_node_int_prop_int,/cpus/cpu@0,xtal-freq)
81 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.h4 * SPDX-License-Identifier: Apache-2.0
30 #include "dai-params-intel-ipc3.h"
31 #include "dai-params-intel-ipc4.h"
34 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
37 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
46 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1)
80 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
81 * Even in the case of M/N, the actual clock source can be XTAL,
94 MN_BCLK_SOURCE_XTAL, /**< port is using XTAL directly */
117 uint32_t freq; member
Dssp.c4 * SPDX-License-Identifier: Apache-2.0
22 #define dai_set_drvdata(dai, data) (dai->priv_data = data)
23 #define dai_get_drvdata(dai) dai->priv_data
24 #define dai_get_plat_data(dai) dai->ssp_plat_data
25 #define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
26 #define dai_get_ftable(dai) dai->ssp_plat_data->ftable
27 #define dai_get_fsources(dai) dai->ssp_plat_data->fsources
28 #define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
29 #define dai_base(dai) dai->ssp_plat_data->base
30 #define dai_ip_base(dai) dai->ssp_plat_data->ip_base
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/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8m1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc { label
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(20)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
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Dr7fa8t1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 xtal: clock-main-osc { label
16 compatible = "renesas,ra-cgc-external-clock";
17 clock-frequency = <DT_FREQ_M(24)>;
18 #clock-cells = <0>;
22 hoco: clock-hoco {
23 compatible = "fixed-clock";
[all …]
Dr7fa8d1xh.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/ra_clock.h>
12 sdram: sdram-controller@40002000 {
13 compatible = "renesas,ra-sdram";
14 #address-cells = <1>;
15 #size-cells = <0>;
20 lcdif: display-controller@40342000 {
21 compatible = "renesas,ra-glcdc";
25 interrupt-names = "line";
30 compatible = "renesas,ra-mipi-dsi";
[all …]
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h>
12 #include <zephyr/dt-bindings/clock/esp32c2_clock.h>
13 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
/Zephyr-latest/tests/boards/espressif/rtc_clk/src/
Drtc_clk_test.c4 * SPDX-License-Identifier: Apache-2.0
71 "CPU clock rate is not equal to XTAL frequency (%d != %d)", cpu_rate, in ZTEST()
144 TC_PRINT("Testing RTC FAST CLK freq: %d MHz\n", rtc_rtc_fast_clk_src_freq_mhz[i]); in ZTEST()
196 TC_PRINT("Testing RTC SLOW CLK freq: %d MHz\n", rtc_rtc_slow_clk_src_freq[i]); in ZTEST()
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.c2 * Copyright 2017-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/linker/linker-defs.h>
18 #include <zephyr/dt-bindings/clock/imx_ccm.h>
46 .loopDivider = (DT_PROP(DT_CHILD(CCM_NODE, sys_pll), loop_div) - 20) / 2,
140 /* Boot ROM did initialize the XTAL, here we only sets external XTAL in clock_init()
141 * OSC freq in clock_init()
143 CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal), in clock_init()
156 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); in clock_init()
159 (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { in clock_init()
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
11 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
12 #include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
37 /* Board xtal frequency in Hz */
154 /* save usb ip clock freq*/ in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
183 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
203 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()
243 /* Updated XTAL oscillator settling time */ in rt5xx_clock_init()
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
[all …]
Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
19 die-temp0 = &coretemp;
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/
Dra-cm4-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <freq.h>
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
11 #include <zephyr/dt-bindings/clock/ra_clock.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
26 xtal: clock-main-osc { label
27 compatible = "renesas,ra-cgc-external-clock";
[all …]
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
12 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
13 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <freq.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/Zephyr-latest/tests/drivers/counter/counter_basic_api/src/
Dtest_counter.c5 * SPDX-License-Identifier: Apache-2.0
182 if (err == -ENOTSUP) { in counter_tear_down_instance()
188 zassert_true((err == 0) || (err == -ENOTSUP), in counter_tear_down_instance()
189 "%s: Setting top value to default failed", dev->name); in counter_tear_down_instance()
192 zassert_equal(0, err, "%s: Counter failed to stop", dev->name); in counter_tear_down_instance()
206 TC_PRINT("Testing %s\n", devices[i]->name); in test_all_instances()
209 TC_PRINT("Skipped for %s\n", devices[i]->name); in test_all_instances()
224 .ticks = counter_get_top_value(dev) - 1 in set_top_value_capable()
229 if (err == -ENOTSUP) { in set_top_value_capable()
235 if (err == -ENOTSUP) { in set_top_value_capable()
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_esp32.c5 * SPDX-License-Identifier: Apache-2.0
10 /* Include esp-idf headers first to avoid redefining BIT() macro */
31 #include "i2c-priv.h"
38 /* Freq limitation when using different clock sources */
42 #define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /* Limited by RTC, no more than XTAL/20 */
44 #define I2C_CLOCK_INVALID (-1)
151 const struct i2c_esp32_config *config = dev->config; in i2c_esp32_config_pin()
154 if (config->index >= SOC_I2C_NUM) { in i2c_esp32_config_pin()
156 return -EINVAL; in i2c_esp32_config_pin()
159 gpio_pin_set_dt(&config->sda.gpio, 1); in i2c_esp32_config_pin()
[all …]

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