1/* 2 * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <freq.h> 8#include <xtensa/xtensa.dtsi> 9#include <zephyr/dt-bindings/adc/adc.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/clock/esp32s3_clock.h> 13#include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h> 14#include <dt-bindings/pinctrl/esp32s3-pinctrl.h> 15 16/ { 17 18 aliases { 19 die-temp0 = &coretemp; 20 }; 21 22 chosen { 23 zephyr,canbus = &twai; 24 zephyr,entropy = &trng0; 25 zephyr,flash-controller = &flash; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "espressif,xtensa-lx7"; 35 reg = <0>; 36 cpu-power-states = <&light_sleep &deep_sleep>; 37 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 38 clock-frequency = <DT_FREQ_M(240)>; 39 xtal-freq = <DT_FREQ_M(40)>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "espressif,xtensa-lx7"; 45 reg = <1>; 46 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 47 clock-frequency = <DT_FREQ_M(240)>; 48 xtal-freq = <DT_FREQ_M(40)>; 49 }; 50 51 power-states { 52 light_sleep: light_sleep { 53 compatible = "zephyr,power-state"; 54 power-state-name = "standby"; 55 min-residency-us = <200>; 56 exit-latency-us = <133>; 57 }; 58 59 deep_sleep: deep_sleep { 60 compatible = "zephyr,power-state"; 61 power-state-name = "soft-off"; 62 min-residency-us = <2000>; 63 exit-latency-us = <382>; 64 }; 65 }; 66 }; 67 68 wifi: wifi { 69 compatible = "espressif,esp32-wifi"; 70 status = "disabled"; 71 }; 72 73 esp32_bt_hci: esp32_bt_hci { 74 compatible = "espressif,esp32-bt-hci"; 75 status = "disabled"; 76 }; 77 78 pinctrl: pin-controller { 79 compatible = "espressif,esp32-pinctrl"; 80 status = "okay"; 81 }; 82 83 soc { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 compatible = "simple-bus"; 87 ranges; 88 89 sram0: memory@40370000 { 90 compatible = "zephyr,memory-region", "mmio-sram"; 91 reg = <0x40370000 DT_SIZE_K(32)>; 92 zephyr,memory-region = "SRAM0"; 93 }; 94 95 sram1: memory@3fc88000 { 96 compatible = "zephyr,memory-region", "mmio-sram"; 97 reg = <0x3fc88000 DT_SIZE_K(416)>; 98 zephyr,memory-region = "SRAM1"; 99 }; 100 101 sram2: memory@3fcf0000 { 102 compatible = "zephyr,memory-region", "mmio-sram"; 103 reg = <0x3fcf0000 DT_SIZE_K(64)>; 104 zephyr,memory-region = "SRAM2"; 105 }; 106 107 ipmmem0: memory@3fce5000 { 108 compatible = "mmio-sram"; 109 reg = <0x3fce5000 0x400>; 110 }; 111 112 shm0: memory@3fce5400 { 113 compatible = "mmio-sram"; 114 reg = <0x3fce5400 0x4000>; 115 }; 116 117 ipm0: ipm@3fce9400 { 118 compatible = "espressif,esp32-ipm"; 119 reg = <0x3fce9400 0x8>; 120 status = "disabled"; 121 shared-memory = <&ipmmem0>; 122 shared-memory-size = <0x400>; 123 interrupts = 124 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>, 125 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>; 126 interrupt-parent = <&intc>; 127 }; 128 129 mbox0: mbox@3fce9408 { 130 compatible = "espressif,mbox-esp32"; 131 reg = <0x3fce9408 0x8>; 132 status = "disabled"; 133 shared-memory = <&ipmmem0>; 134 shared-memory-size = <0x400>; 135 interrupts = 136 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>, 137 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>; 138 interrupt-parent = <&intc>; 139 #mbox-cells = <1>; 140 }; 141 142 intc: interrupt-controller@600c2000 { 143 #interrupt-cells = <3>; 144 #address-cells = <0>; 145 compatible = "espressif,esp32-intc"; 146 interrupt-controller; 147 reg = <0x600c2000 0x1000>; 148 status = "okay"; 149 }; 150 151 rtc: rtc@60021000 { 152 compatible = "espressif,esp32-rtc"; 153 reg = <0x60021000 0x2000>; 154 fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>; 155 slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>; 156 #clock-cells = <1>; 157 status = "okay"; 158 }; 159 160 xt_wdt: xt_wdt@60021004 { 161 compatible = "espressif,esp32-xt-wdt"; 162 reg = <0x60021004 0x4>; 163 clocks = <&rtc ESP32_MODULE_MAX>; 164 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 165 interrupt-parent = <&intc>; 166 status = "disabled"; 167 }; 168 169 rtc_timer: rtc_timer@60008004 { 170 reg = <0x60008004 0xC>; 171 compatible = "espressif,esp32-rtc-timer"; 172 clocks = <&rtc ESP32_MODULE_MAX>; 173 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 174 interrupt-parent = <&intc>; 175 status = "disabled"; 176 }; 177 178 flash: flash-controller@60002000 { 179 compatible = "espressif,esp32-flash-controller"; 180 reg = <0x60002000 0x1000>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 184 flash0: flash@0 { 185 compatible = "soc-nv-flash"; 186 erase-block-size = <4096>; 187 write-block-size = <4>; 188 /* Flash size is specified in SOC/SIP dtsi */ 189 }; 190 }; 191 192 psram0: psram@3c000000 { 193 device_type = "memory"; 194 compatible = "mmio-sram"; 195 /* PSRAM size is specified in SOC/SIP dtsi */ 196 reg = <0x3c000000 DT_SIZE_M(2)>; 197 status = "disabled"; 198 }; 199 200 uart0: uart@60000000 { 201 compatible = "espressif,esp32-uart"; 202 reg = <0x60000000 0x1000>; 203 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 204 interrupt-parent = <&intc>; 205 clocks = <&rtc ESP32_UART0_MODULE>; 206 status = "disabled"; 207 }; 208 209 uart1: uart@60010000 { 210 compatible = "espressif,esp32-uart"; 211 reg = <0x60010000 0x1000>; 212 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 213 interrupt-parent = <&intc>; 214 clocks = <&rtc ESP32_UART1_MODULE>; 215 status = "disabled"; 216 }; 217 218 uart2: uart@6002e000 { 219 compatible = "espressif,esp32-uart"; 220 reg = <0x6002e000 0x1000>; 221 interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 222 interrupt-parent = <&intc>; 223 clocks = <&rtc ESP32_UART2_MODULE>; 224 status = "disabled"; 225 }; 226 227 gpio: gpio { 228 compatible = "simple-bus"; 229 gpio-map-mask = <0xffffffe0 0xffffffc0>; 230 gpio-map-pass-thru = <0x1f 0x3f>; 231 gpio-map = < 232 0x00 0x0 &gpio0 0x0 0x0 233 0x20 0x0 &gpio1 0x0 0x0 234 >; 235 #gpio-cells = <2>; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges; 239 240 gpio0: gpio@60004000 { 241 compatible = "espressif,esp32-gpio"; 242 gpio-controller; 243 #gpio-cells = <2>; 244 reg = <0x60004000 0x800>; 245 interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 246 interrupt-parent = <&intc>; 247 /* Maximum available pins (per port) 248 * Actual occupied pins are specified 249 * on part number dtsi level, using 250 * the `gpio-reserved-ranges` property. 251 */ 252 ngpios = <32>; /* 0..31 */ 253 }; 254 255 gpio1: gpio@60004800 { 256 compatible = "espressif,esp32-gpio"; 257 gpio-controller; 258 #gpio-cells = <2>; 259 reg = <0x60004800 0x800>; 260 interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 261 interrupt-parent = <&intc>; 262 ngpios = <22>; /* 32..53 */ 263 }; 264 }; 265 266 touch: touch@6000885c { 267 compatible = "espressif,esp32-touch"; 268 reg = <0x6000885c 0x88 0x60008908 0x18>; 269 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 270 interrupt-parent = <&intc>; 271 status = "disabled"; 272 }; 273 274 i2c0: i2c@60013000 { 275 compatible = "espressif,esp32-i2c"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0x60013000 DT_SIZE_K(4)>; 279 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 280 interrupt-parent = <&intc>; 281 clocks = <&rtc ESP32_I2C0_MODULE>; 282 status = "disabled"; 283 }; 284 285 i2c1: i2c@60027000 { 286 compatible = "espressif,esp32-i2c"; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 reg = <0x60027000 DT_SIZE_K(4)>; 290 interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 291 interrupt-parent = <&intc>; 292 clocks = <&rtc ESP32_I2C1_MODULE>; 293 status = "disabled"; 294 }; 295 296 i2s0: i2s@6000f000 { 297 compatible = "espressif,esp32-i2s"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 reg = <0x6000f000 0x1000>; 301 interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 302 interrupt-parent = <&intc>; 303 clocks = <&rtc ESP32_I2S0_MODULE>; 304 dmas = <&dma 2>, <&dma 3>; 305 dma-names = "rx", "tx"; 306 unit = <0>; 307 status = "disabled"; 308 }; 309 310 i2s1: i2s@6002d000 { 311 compatible = "espressif,esp32-i2s"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x6002d000 0x1000>; 315 interrupts = <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 316 interrupt-parent = <&intc>; 317 clocks = <&rtc ESP32_I2S1_MODULE>; 318 dmas = <&dma 4>, <&dma 5>; 319 dma-names = "rx", "tx"; 320 unit = <1>; 321 status = "disabled"; 322 }; 323 324 spi2: spi@60024000 { 325 compatible = "espressif,esp32-spi"; 326 reg = <0x60024000 DT_SIZE_K(4)>; 327 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 328 interrupt-parent = <&intc>; 329 clocks = <&rtc ESP32_SPI2_MODULE>; 330 dma-clk = <ESP32_GDMA_MODULE>; 331 dma-host = <0>; 332 status = "disabled"; 333 }; 334 335 spi3: spi@60025000 { 336 compatible = "espressif,esp32-spi"; 337 reg = <0x60025000 DT_SIZE_K(4)>; 338 interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 339 interrupt-parent = <&intc>; 340 clocks = <&rtc ESP32_SPI3_MODULE>; 341 dma-clk = <ESP32_GDMA_MODULE>; 342 dma-host = <1>; 343 status = "disabled"; 344 }; 345 346 coretemp: coretemp@60008800 { 347 compatible = "espressif,esp32-temp"; 348 friendly-name = "coretemp"; 349 reg = <0x60008800 0x4>; 350 status = "disabled"; 351 }; 352 353 adc0: adc@60040000 { 354 compatible = "espressif,esp32-adc"; 355 reg = <0x60040000 4>; 356 unit = <1>; 357 channel-count = <10>; 358 #io-channel-cells = <1>; 359 status = "disabled"; 360 }; 361 362 adc1: adc@60040004 { 363 compatible = "espressif,esp32-adc"; 364 reg = <0x60040004 4>; 365 unit = <2>; 366 channel-count = <10>; 367 #io-channel-cells = <1>; 368 status = "disabled"; 369 }; 370 371 twai: can@6002b000 { 372 compatible = "espressif,esp32-twai"; 373 reg = <0x6002b000 DT_SIZE_K(4)>; 374 interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 375 interrupt-parent = <&intc>; 376 clocks = <&rtc ESP32_TWAI_MODULE>; 377 status = "disabled"; 378 }; 379 380 lcd_cam: lcd_cam@60041000 { 381 compatible = "espressif,esp32-lcd-cam"; 382 reg = <0x60041000 DT_SIZE_K(4)>; 383 clocks = <&rtc ESP32_LCD_CAM_MODULE>; 384 interrupts = <LCD_CAM_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 385 interrupt-parent = <&intc>; 386 status = "disabled"; 387 }; 388 389 usb_serial: uart@60038000 { 390 compatible = "espressif,esp32-usb-serial"; 391 reg = <0x60038000 DT_SIZE_K(4)>; 392 status = "disabled"; 393 interrupts = <USB_SERIAL_JTAG_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 394 interrupt-parent = <&intc>; 395 clocks = <&rtc ESP32_USB_MODULE>; 396 }; 397 398 timer0: counter@6001f000 { 399 compatible = "espressif,esp32-timer"; 400 reg = <0x6001f000 DT_SIZE_K(4)>; 401 clocks = <&rtc ESP32_TIMG0_MODULE>; 402 group = <0>; 403 index = <0>; 404 interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 405 interrupt-parent = <&intc>; 406 status = "disabled"; 407 }; 408 409 timer1: counter@6001f024 { 410 compatible = "espressif,esp32-timer"; 411 reg = <0x6001f024 DT_SIZE_K(4)>; 412 clocks = <&rtc ESP32_TIMG0_MODULE>; 413 group = <0>; 414 index = <1>; 415 interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 416 interrupt-parent = <&intc>; 417 status = "disabled"; 418 }; 419 420 timer2: counter@60020000 { 421 compatible = "espressif,esp32-timer"; 422 reg = <0x60020000 DT_SIZE_K(4)>; 423 clocks = <&rtc ESP32_TIMG1_MODULE>; 424 group = <1>; 425 index = <0>; 426 interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 427 interrupt-parent = <&intc>; 428 status = "disabled"; 429 }; 430 431 timer3: counter@60020024 { 432 compatible = "espressif,esp32-timer"; 433 reg = <0x60020024 DT_SIZE_K(4)>; 434 clocks = <&rtc ESP32_TIMG1_MODULE>; 435 group = <1>; 436 index = <1>; 437 interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 438 interrupt-parent = <&intc>; 439 }; 440 441 wdt0: watchdog@6001f048 { 442 compatible = "espressif,esp32-watchdog"; 443 reg = <0x6001f048 0x20>; 444 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 445 interrupt-parent = <&intc>; 446 clocks = <&rtc ESP32_TIMG0_MODULE>; 447 status = "disabled"; 448 }; 449 450 wdt1: watchdog@60020048 { 451 compatible = "espressif,esp32-watchdog"; 452 reg = <0x60020048 0x20>; 453 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 454 interrupt-parent = <&intc>; 455 clocks = <&rtc ESP32_TIMG1_MODULE>; 456 status = "disabled"; 457 }; 458 459 trng0: trng@6003507c { 460 compatible = "espressif,esp32-trng"; 461 reg = <0x6003507c 0x4>; 462 status = "disabled"; 463 }; 464 465 ledc0: ledc@60019000 { 466 compatible = "espressif,esp32-ledc"; 467 #pwm-cells = <3>; 468 reg = <0x60019000 DT_SIZE_K(4)>; 469 clocks = <&rtc ESP32_LEDC_MODULE>; 470 status = "disabled"; 471 }; 472 473 mcpwm0: mcpwm@6001e000 { 474 compatible = "espressif,esp32-mcpwm"; 475 reg = <0x6001e000 DT_SIZE_K(4)>; 476 interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 477 interrupt-parent = <&intc>; 478 clocks = <&rtc ESP32_PWM0_MODULE>; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 mcpwm1: mcpwm@6002c000 { 484 compatible = "espressif,esp32-mcpwm"; 485 reg = <0x6002c000 DT_SIZE_K(4)>; 486 interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 487 interrupt-parent = <&intc>; 488 clocks = <&rtc ESP32_PWM1_MODULE>; 489 #pwm-cells = <3>; 490 status = "disabled"; 491 }; 492 493 pcnt: pcnt@60017000 { 494 compatible = "espressif,esp32-pcnt"; 495 reg = <0x60017000 DT_SIZE_K(4)>; 496 interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 497 interrupt-parent = <&intc>; 498 clocks = <&rtc ESP32_PCNT_MODULE>; 499 status = "disabled"; 500 }; 501 502 dma: dma@6003f000 { 503 compatible = "espressif,esp32-gdma"; 504 reg = <0x6003f000 DT_SIZE_K(4)>; 505 #dma-cells = <1>; 506 interrupts = 507 <DMA_IN_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 508 <DMA_OUT_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 509 <DMA_IN_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 510 <DMA_OUT_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 511 <DMA_IN_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 512 <DMA_OUT_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 513 <DMA_IN_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 514 <DMA_OUT_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 515 <DMA_IN_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>, 516 <DMA_OUT_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>; 517 interrupt-parent = <&intc>; 518 clocks = <&rtc ESP32_GDMA_MODULE>; 519 dma-channels = <10>; 520 dma-buf-addr-alignment = <4>; 521 status = "disabled"; 522 }; 523 524 sdhc: sdhc@60028000 { 525 compatible = "espressif,esp32-sdhc"; 526 reg = <0x60028000 0x1000>; 527 interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 528 interrupt-parent = <&intc>; 529 clocks = <&rtc ESP32_SDMMC_MODULE>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 533 sdhc0: sdhc@0 { 534 compatible = "espressif,esp32-sdhc-slot"; 535 reg = <0>; 536 status = "disabled"; 537 }; 538 539 sdhc1: sdhc@1 { 540 compatible = "espressif,esp32-sdhc-slot"; 541 reg = <1>; 542 status = "disabled"; 543 }; 544 }; 545 }; 546}; 547
