5  * SPDX-License-Identifier: Apache-2.0
116 	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | reg_val;  in soc_pmc_mck_set_prescaler()
118 	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {  in soc_pmc_mck_set_prescaler()
152 	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | reg_val;  in soc_pmc_mck_set_divider()
154 	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {  in soc_pmc_mck_set_divider()
167 	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | (uint32_t)source;  in soc_pmc_mck_set_source()
169 	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {  in soc_pmc_mck_set_source()
176  * @param freq the internal fast RC desired frequency 4/8/12MHz.
178 static ALWAYS_INLINE void soc_pmc_switch_mainck_to_fastrc(enum soc_pmc_fast_rc_freq freq)  in soc_pmc_switch_mainck_to_fastrc()  argument
181 	PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;  in soc_pmc_switch_mainck_to_fastrc()
184 	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {  in soc_pmc_switch_mainck_to_fastrc()
188 	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)  in soc_pmc_switch_mainck_to_fastrc()
190 		      | (uint32_t)freq;  in soc_pmc_switch_mainck_to_fastrc()
193 	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {  in soc_pmc_switch_mainck_to_fastrc()
197 	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL)  in soc_pmc_switch_mainck_to_fastrc()
204  * @param freq the internal fast RC desired frequency 4/8/12MHz.
206 static ALWAYS_INLINE void soc_pmc_osc_enable_fastrc(enum soc_pmc_fast_rc_freq freq)  in soc_pmc_osc_enable_fastrc()  argument
209 	PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN;  in soc_pmc_osc_enable_fastrc()
212 	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {  in soc_pmc_osc_enable_fastrc()
216 	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk)  in soc_pmc_osc_enable_fastrc()
218 		      | (uint32_t)freq;  in soc_pmc_osc_enable_fastrc()
221 	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {  in soc_pmc_osc_enable_fastrc()
231 	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & ~CKGR_MOR_MOSCRCF_Msk)  in soc_pmc_osc_disable_fastrc()
242 	return (PMC->PMC_SR & PMC_SR_MOSCRCS);  in soc_pmc_osc_is_ready_fastrc()
248  * @param xtal_startup_time crystal start-up time, in number of slow clocks.
252 	uint32_t mor = PMC->CKGR_MOR;  in soc_pmc_osc_enable_main_xtal()
257 	PMC->CKGR_MOR = mor;  in soc_pmc_osc_enable_main_xtal()
259 	/* Wait the main Xtal to stabilize */  in soc_pmc_osc_enable_main_xtal()
260 	while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {  in soc_pmc_osc_enable_main_xtal()
269 	uint32_t mor = PMC->CKGR_MOR;  in soc_pmc_osc_bypass_main_xtal()
275 	PMC->CKGR_MOR = mor;  in soc_pmc_osc_bypass_main_xtal()
284 	uint32_t mor = PMC->CKGR_MOR;  in soc_pmc_osc_disable_main_xtal()
288 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;  in soc_pmc_osc_disable_main_xtal()
298 	return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);  in soc_pmc_osc_is_bypassed_main_xtal()
308 	return (PMC->PMC_SR & PMC_SR_MOSCXTS);  in soc_pmc_osc_is_ready_main_xtal()
314  * @param bypass select bypass or xtal
315  * @param xtal_startup_time crystal start-up time, in number of slow clocks
321 	/* Enable Main Xtal oscillator */  in soc_pmc_switch_mainck_to_xtal()
323 		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)  in soc_pmc_switch_mainck_to_xtal()
328 		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)  in soc_pmc_switch_mainck_to_xtal()
333 		/* Wait for the Xtal to stabilize */  in soc_pmc_switch_mainck_to_xtal()
334 		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {  in soc_pmc_switch_mainck_to_xtal()
337 		PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;  in soc_pmc_switch_mainck_to_xtal()
344  * @param bypass select bypass or xtal
348 	/* Disable xtal oscillator */  in soc_pmc_osc_disable_xtal()
350 		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY)  in soc_pmc_osc_disable_xtal()
353 		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN)  in soc_pmc_osc_disable_xtal()
366 	return PMC->PMC_SR & PMC_SR_MOSCSELS;  in soc_pmc_osc_is_ready_mainck()
374 	PMC->PMC_FSMR |= PMC_FSMR_LPM;  in soc_pmc_enable_waitmode()
382 	uint32_t mor = PMC->CKGR_MOR;  in soc_pmc_enable_clock_failure_detector()
384 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | mor;  in soc_pmc_enable_clock_failure_detector()
392 	uint32_t mor = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);  in soc_pmc_disable_clock_failure_detector()
394 	PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;  in soc_pmc_disable_clock_failure_detector()
404 	PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);  in soc_pmc_disable_pllack()
421 	PMC->CKGR_PLLAR = CKGR_PLLAR_ONE  in soc_pmc_enable_pllack()
426 	while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0) {  in soc_pmc_enable_pllack()
437 	return (PMC->PMC_SR & PMC_SR_LOCKA);  in soc_pmc_is_locked_pllack()
449 	PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);  in soc_pmc_disable_pllbck()
466 	PMC->CKGR_PLLBR = CKGR_PLLBR_DIVB(divb)  in soc_pmc_enable_pllbck()
470 	while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0) {  in soc_pmc_enable_pllbck()
481 	return (PMC->PMC_SR & PMC_SR_LOCKB);  in soc_pmc_is_locked_pllbck()
493 	PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(upllcount)  in soc_pmc_enable_upllck()
497 	while (!(PMC->PMC_SR & PMC_SR_LOCKU)) {  in soc_pmc_enable_upllck()
506 	PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;  in soc_pmc_disable_upllck()
516 	return (PMC->PMC_SR & PMC_SR_LOCKU);  in soc_pmc_is_locked_upllck()