1/* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <freq.h> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h> 12#include <zephyr/dt-bindings/clock/esp32c2_clock.h> 13#include <dt-bindings/pinctrl/esp32-pinctrl.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 aliases { 20 die-temp0 = &coretemp; 21 }; 22 23 chosen { 24 zephyr,entropy = &trng0; 25 zephyr,flash-controller = &flash; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "espressif,riscv", "riscv"; 35 riscv,isa = "rv32imc_zicsr"; 36 reg = <0>; 37 clock-source = <ESP32_CPU_CLK_SRC_PLL>; 38 clock-frequency = <DT_FREQ_M(120)>; 39 xtal-freq = <DT_FREQ_M(26)>; 40 }; 41 }; 42 43 pinctrl: pin-controller { 44 compatible = "espressif,esp32-pinctrl"; 45 status = "okay"; 46 }; 47 48 wifi: wifi { 49 compatible = "espressif,esp32-wifi"; 50 status = "disabled"; 51 }; 52 53 soc { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 compatible = "simple-bus"; 57 ranges; 58 59 sram0: memory@4037c000 { 60 compatible = "zephyr,memory-region", "mmio-sram"; 61 reg = <0x4037c000 DT_SIZE_K(16)>; 62 zephyr,memory-region = "SRAM0"; 63 }; 64 65 sram1: memory@3fca0000 { 66 compatible = "zephyr,memory-region", "mmio-sram"; 67 reg = <0x3fca0000 DT_SIZE_K(256)>; 68 zephyr,memory-region = "SRAM1"; 69 }; 70 71 intc: interrupt-controller@600c2000 { 72 compatible = "espressif,esp32-intc"; 73 #address-cells = <0>; 74 #interrupt-cells = <3>; 75 interrupt-controller; 76 reg = <0x600c2000 0x198>; 77 status = "okay"; 78 }; 79 80 systimer0: systimer@60023000 { 81 compatible = "espressif,esp32-systimer"; 82 reg = <0x60023000 0x80>; 83 interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 84 interrupt-parent = <&intc>; 85 status = "okay"; 86 }; 87 88 rtc: rtc@60008000 { 89 compatible = "espressif,esp32-rtc"; 90 reg = <0x60008000 0x1000>; 91 fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>; 92 slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>; 93 #clock-cells = <1>; 94 status = "okay"; 95 }; 96 97 rtc_timer: rtc_timer@60008004 { 98 reg = <0x60008004 0xC>; 99 compatible = "espressif,esp32-rtc-timer"; 100 clocks = <&rtc ESP32_MODULE_MAX>; 101 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 102 interrupt-parent = <&intc>; 103 status = "disabled"; 104 }; 105 106 flash: flash-controller@60002000 { 107 compatible = "espressif,esp32-flash-controller"; 108 reg = <0x60002000 0x1000>; 109 110 #address-cells = <1>; 111 #size-cells = <1>; 112 113 flash0: flash@0 { 114 compatible = "soc-nv-flash"; 115 erase-block-size = <4096>; 116 write-block-size = <4>; 117 /* Flash size is specified in SOC/SIP dtsi */ 118 }; 119 }; 120 121 gpio0: gpio@60004000 { 122 compatible = "espressif,esp32-gpio"; 123 gpio-controller; 124 #gpio-cells = <2>; 125 reg = <0x60004000 0x800>; 126 interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 127 interrupt-parent = <&intc>; 128 /* Maximum available pins (per port) 129 * Actual occupied pins are specified 130 * on part number dtsi level, using 131 * the `gpio-reserved-ranges` property. 132 */ 133 ngpios = <20>; /* 0..20 */ 134 }; 135 136 i2c0: i2c@60013000 { 137 compatible = "espressif,esp32-i2c"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 reg = <0x60013000 0x1000>; 141 interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 142 interrupt-parent = <&intc>; 143 clocks = <&rtc ESP32_I2C0_MODULE>; 144 status = "disabled"; 145 }; 146 147 uart0: uart@60000000 { 148 compatible = "espressif,esp32-uart"; 149 reg = <0x60000000 0x400>; 150 status = "disabled"; 151 interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 152 interrupt-parent = <&intc>; 153 clocks = <&rtc ESP32_UART0_MODULE>; 154 }; 155 156 uart1: uart@60010000 { 157 compatible = "espressif,esp32-uart"; 158 reg = <0x60010000 0x400>; 159 status = "disabled"; 160 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 161 interrupt-parent = <&intc>; 162 clocks = <&rtc ESP32_UART1_MODULE>; 163 current-speed = <115200>; 164 }; 165 166 ledc0: ledc@60019000 { 167 compatible = "espressif,esp32-ledc"; 168 pwm-controller; 169 #pwm-cells = <3>; 170 reg = <0x60019000 0x1000>; 171 clocks = <&rtc ESP32_LEDC_MODULE>; 172 status = "disabled"; 173 }; 174 175 timer0: counter@6001f000 { 176 compatible = "espressif,esp32-timer"; 177 reg = <0x6001F000 DT_SIZE_K(4)>; 178 clocks = <&rtc ESP32_TIMG0_MODULE>; 179 group = <0>; 180 index = <0>; 181 interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 182 interrupt-parent = <&intc>; 183 status = "disabled"; 184 }; 185 186 trng0: trng@3ff700b0 { 187 compatible = "espressif,esp32-trng"; 188 reg = <0x3FF700B0 0x4>; 189 status = "disabled"; 190 }; 191 192 spi2: spi@60024000 { 193 compatible = "espressif,esp32-spi"; 194 reg = <0x60024000 DT_SIZE_K(4)>; 195 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 196 interrupt-parent = <&intc>; 197 clocks = <&rtc ESP32_SPI2_MODULE>; 198 dma-clk = <ESP32_GDMA_MODULE>; 199 dma-host = <0>; 200 status = "disabled"; 201 }; 202 203 wdt0: watchdog@6001f048 { 204 compatible = "espressif,esp32-watchdog"; 205 reg = <0x6001f048 0x20>; 206 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>; 207 interrupt-parent = <&intc>; 208 clocks = <&rtc ESP32_TIMG0_MODULE>; 209 status = "disabled"; 210 }; 211 212 coretemp: coretemp@60040058 { 213 compatible = "espressif,esp32-temp"; 214 friendly-name = "coretemp"; 215 reg = <0x60040058 0x4>; 216 status = "disabled"; 217 }; 218 }; 219}; 220
