1 /*
2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/ztest.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/sys/printk.h>
11 #include <zephyr/drivers/clock_control/esp32_clock_control.h>
12 #include <zephyr/drivers/clock_control.h>
13
14 #if defined(CONFIG_SOC_SERIES_ESP32)
15 #define DT_CPU_COMPAT espressif_xtensa_lx6
16 #elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3)
17 #define DT_CPU_COMPAT espressif_xtensa_lx7
18 #elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \
19 defined(CONFIG_SOC_SERIES_ESP32C6)
20 #define DT_CPU_COMPAT espressif_riscv
21 #endif
22
23 static const struct device *const clk_dev = DEVICE_DT_GET_ONE(espressif_esp32_rtc);
24
rtc_clk_setup(void)25 static void *rtc_clk_setup(void)
26 {
27 zassert_true(device_is_ready(clk_dev), "CLK device is not ready");
28 uint32_t rate = 0;
29 int ret = 0;
30
31 ret = clock_control_get_rate(clk_dev,
32 (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &rate);
33 zassert_false(ret, "Failed to get CPU clock rate");
34 TC_PRINT("CPU frequency: %d\n", rate);
35
36 ret = clock_control_get_rate(
37 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST, &rate);
38 zassert_false(ret, "Failed to get RTC_FAST clock rate");
39 TC_PRINT("RTC_FAST frequency: %d\n", rate);
40
41 ret = clock_control_get_rate(
42 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, &rate);
43 zassert_false(ret, "Failed to get RTC_SLOW clock rate");
44 TC_PRINT("RTC_SLOW frequency: %d\n", rate);
45
46 return NULL;
47 }
48
ZTEST(rtc_clk,test_cpu_xtal_src)49 ZTEST(rtc_clk, test_cpu_xtal_src)
50 {
51 struct esp32_clock_config clk_cfg = {0};
52 int ret = 0;
53 uint32_t cpu_rate = 0;
54
55 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_XTAL;
56 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1));
57
58 for (uint8_t i = 0; i < 4; i++) {
59 clk_cfg.cpu.cpu_freq = clk_cfg.cpu.xtal_freq >> i;
60
61 TC_PRINT("Testing CPU frequency: %d MHz\n", clk_cfg.cpu.cpu_freq);
62
63 ret = clock_control_configure(
64 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg);
65 zassert_false(ret, "Failed to set CPU clock source");
66
67 ret = clock_control_get_rate(
68 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate);
69 zassert_false(ret, "Failed to get CPU clock rate");
70 zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1),
71 "CPU clock rate is not equal to XTAL frequency (%d != %d)", cpu_rate,
72 clk_cfg.cpu.cpu_freq);
73 }
74 }
75
76 uint32_t rtc_pll_src_freq_mhz[] = {
77 ESP32_CLK_CPU_PLL_80M,
78 #if defined(CONFIG_SOC_SERIES_ESP32C2)
79 ESP32_CLK_CPU_PLL_120M,
80 #else
81 ESP32_CLK_CPU_PLL_160M,
82 #endif
83 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) && \
84 !defined(CONFIG_SOC_SERIES_ESP32C6)
85 ESP32_CLK_CPU_PLL_240M,
86 #endif
87 };
88
ZTEST(rtc_clk,test_cpu_pll_src)89 ZTEST(rtc_clk, test_cpu_pll_src)
90 {
91 struct esp32_clock_config clk_cfg = {0};
92 int ret = 0;
93 uint32_t cpu_rate = 0;
94
95 clk_cfg.cpu.clk_src = ESP32_CPU_CLK_SRC_PLL;
96 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1));
97
98 for (uint8_t i = 0; i < ARRAY_SIZE(rtc_pll_src_freq_mhz); i++) {
99 clk_cfg.cpu.cpu_freq = rtc_pll_src_freq_mhz[i] / MHZ(1);
100
101 TC_PRINT("Testing CPU frequency: %d MHz\n", clk_cfg.cpu.cpu_freq);
102
103 ret = clock_control_configure(
104 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &clk_cfg);
105 zassert_false(ret, "Failed to set CPU clock source");
106
107 ret = clock_control_get_rate(
108 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_CPU, &cpu_rate);
109 zassert_false(ret, "Failed to get CPU clock rate");
110 zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1),
111 "CPU clock rate is not equal to configured frequency (%d != %d)",
112 cpu_rate, clk_cfg.cpu.cpu_freq);
113 }
114 }
115
116 uint32_t rtc_rtc_fast_clk_src[] = {
117 #if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32S2)
118 ESP32_RTC_FAST_CLK_SRC_XTAL_D4,
119 #else
120 ESP32_RTC_FAST_CLK_SRC_XTAL_D2,
121 #endif
122 ESP32_RTC_FAST_CLK_SRC_RC_FAST};
123
124 uint32_t rtc_rtc_fast_clk_src_freq_mhz[] = {
125 #if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32S2)
126 DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / 4,
127 #else
128 DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / 2,
129 #endif
130 ESP32_CLK_CPU_RC_FAST_FREQ
131 };
132
ZTEST(rtc_clk,test_rtc_fast_src)133 ZTEST(rtc_clk, test_rtc_fast_src)
134 {
135 struct esp32_clock_config clk_cfg = {0};
136 int ret = 0;
137 uint32_t cpu_rate = 0;
138
139 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1));
140
141 for (uint8_t i = 0; i < ARRAY_SIZE(rtc_rtc_fast_clk_src); i++) {
142 clk_cfg.rtc.rtc_fast_clock_src = rtc_rtc_fast_clk_src[i];
143
144 TC_PRINT("Testing RTC FAST CLK freq: %d MHz\n", rtc_rtc_fast_clk_src_freq_mhz[i]);
145
146 ret = clock_control_configure(
147 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST,
148 &clk_cfg);
149 zassert_false(ret, "Failed to set CPU clock source");
150
151 ret = clock_control_get_rate(
152 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST,
153 &cpu_rate);
154 zassert_false(ret, "Failed to get RTC_FAST clock rate");
155 zassert_equal(cpu_rate, rtc_rtc_fast_clk_src_freq_mhz[i],
156 "CPU clock rate is not equal to configured frequency (%d != %d)",
157 cpu_rate, rtc_rtc_fast_clk_src_freq_mhz[i]);
158 }
159 }
160
161 uint32_t rtc_rtc_slow_clk_src[] = {
162 ESP32_RTC_SLOW_CLK_SRC_RC_SLOW,
163 #if defined(CONFIG_SOC_SERIES_ESP32C6)
164 ESP32_RTC_SLOW_CLK_SRC_RC32K,
165 #else
166 ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256,
167 #endif
168 #if CONFIG_FIXTURE_XTAL
169 ESP32_RTC_SLOW_CLK_SRC_XTAL32K,
170 #endif
171 };
172
173 uint32_t rtc_rtc_slow_clk_src_freq[] = {
174 ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ,
175 #if defined(CONFIG_SOC_SERIES_ESP32C6)
176 ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ,
177 #else
178 ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ,
179 #endif
180 #if CONFIG_FIXTURE_XTAL
181 ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ,
182 #endif
183 };
184
ZTEST(rtc_clk,test_rtc_slow_src)185 ZTEST(rtc_clk, test_rtc_slow_src)
186 {
187 struct esp32_clock_config clk_cfg = {0};
188 int ret = 0;
189 uint32_t cpu_rate = 0;
190
191 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1));
192
193 for (uint8_t i = 0; i < ARRAY_SIZE(rtc_rtc_slow_clk_src); i++) {
194 clk_cfg.rtc.rtc_slow_clock_src = rtc_rtc_slow_clk_src[i];
195
196 TC_PRINT("Testing RTC SLOW CLK freq: %d MHz\n", rtc_rtc_slow_clk_src_freq[i]);
197
198 ret = clock_control_configure(
199 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW,
200 &clk_cfg);
201 zassert_false(ret, "Failed to set CPU clock source");
202
203 ret = clock_control_get_rate(
204 clk_dev, (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW,
205 &cpu_rate);
206 zassert_false(ret, "Failed to get RTC_SLOW clock rate");
207 zassert_equal(cpu_rate, rtc_rtc_slow_clk_src_freq[i],
208 "CPU clock rate is not equal to configured frequency (%d != %d)",
209 cpu_rate, rtc_rtc_slow_clk_src_freq[i]);
210 }
211 }
212
213 ZTEST_SUITE(rtc_clk, NULL, rtc_clk_setup, NULL, NULL, NULL);
214
