1/*
2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <freq.h>
8#include <xtensa/xtensa.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
13#include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
14#include <dt-bindings/pinctrl/esp32-pinctrl.h>
15
16/ {
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		die-temp0 = &coretemp;
22	};
23
24	chosen {
25		zephyr,canbus = &twai;
26		zephyr,entropy = &trng0;
27		zephyr,flash-controller = &flash;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "espressif,xtensa-lx7";
37			reg = <0>;
38			cpu-power-states = <&light_sleep &deep_sleep>;
39			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
40			clock-frequency = <DT_FREQ_M(240)>;
41			xtal-freq = <DT_FREQ_M(40)>;
42		};
43
44		power-states {
45			light_sleep: light_sleep {
46				compatible = "zephyr,power-state";
47				power-state-name = "standby";
48				min-residency-us = <200>;
49				exit-latency-us = <60>;
50			};
51
52			deep_sleep: deep_sleep {
53				compatible = "zephyr,power-state";
54				power-state-name = "soft-off";
55				min-residency-us = <2000>;
56				exit-latency-us = <212>;
57			};
58		};
59	};
60
61	wifi: wifi {
62		compatible = "espressif,esp32-wifi";
63		status = "disabled";
64	};
65
66	esp32_bt_hci: esp32_bt_hci {
67		compatible = "espressif,esp32-bt-hci";
68		status = "disabled";
69	};
70
71	pinctrl: pin-controller {
72		compatible = "espressif,esp32-pinctrl";
73		status = "okay";
74	};
75
76	soc {
77		#address-cells = <1>;
78		#size-cells = <1>;
79		compatible = "simple-bus";
80		ranges;
81
82		sram0: memory@3ffb0000 {
83			compatible = "zephyr,memory-region", "mmio-sram";
84			reg = <0x3ffb0000 DT_SIZE_K(32)>;
85			zephyr,memory-region = "SRAM0";
86		};
87
88		sram1: memory@3ffb8000 {
89			compatible = "zephyr,memory-region", "mmio-sram";
90			reg = <0x3ffb8000 DT_SIZE_K(288)>;
91			zephyr,memory-region = "SRAM1";
92		};
93
94		intc: interrupt-controller@3f4c2000 {
95			#interrupt-cells = <3>;
96			#address-cells = <0>;
97			compatible = "espressif,esp32-intc";
98			interrupt-controller;
99			reg = <0x3f4c2000 0x114>;
100			status = "okay";
101		};
102
103		rtc: rtc@3f408000 {
104			compatible = "espressif,esp32-rtc";
105			reg = <0x3f408000 0x0D8>;
106			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_XTAL_D4>;
107			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
108			#clock-cells = <1>;
109			status = "okay";
110		};
111
112		xt_wdt: xt_wdt@3f408004 {
113			compatible = "espressif,esp32-xt-wdt";
114			reg = <0x3f408004 0x4>;
115			clocks = <&rtc ESP32_MODULE_MAX>;
116			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
117			interrupt-parent = <&intc>;
118			status = "disabled";
119		};
120
121		rtc_timer: rtc_timer@3f408004 {
122			reg = <0x3f408004 0xC>;
123			compatible = "espressif,esp32-rtc-timer";
124			clocks = <&rtc ESP32_MODULE_MAX>;
125			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
126			interrupt-parent = <&intc>;
127			status = "okay";
128		};
129
130		flash: flash-controller@3f402000 {
131			compatible = "espressif,esp32-flash-controller";
132			reg = <0x3f402000 0x1000>;
133
134			#address-cells = <1>;
135			#size-cells = <1>;
136
137			flash0: flash@0 {
138				compatible = "soc-nv-flash";
139				erase-block-size = <4096>;
140				write-block-size = <4>;
141				/* Flash size is specified in SOC/SIP dtsi */
142			};
143		};
144
145		psram0: psram@3f500000 {
146			device_type = "memory";
147			compatible = "mmio-sram";
148			/* PSRAM size is specified in SOC/SIP dtsi */
149			reg = <0x3f500000 DT_SIZE_M(2)>;
150			status = "disabled";
151		};
152
153		uart0: uart@3f400000 {
154			compatible = "espressif,esp32-uart";
155			reg = <0x3f400000 0x400>;
156			status = "disabled";
157			interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
158			interrupt-parent = <&intc>;
159			clocks = <&rtc ESP32_UART0_MODULE>;
160		};
161
162		uart1: uart@3f410000 {
163			compatible = "espressif,esp32-uart";
164			reg = <0x3f410000 0x400>;
165			status = "disabled";
166			interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
167			interrupt-parent = <&intc>;
168			clocks = <&rtc ESP32_UART1_MODULE>;
169			current-speed = <115200>;
170		};
171
172		pcnt: pcnt@3f417000 {
173			compatible = "espressif,esp32-pcnt";
174			reg = <0x3f417000 0x1000>;
175			interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
176			interrupt-parent = <&intc>;
177			clocks = <&rtc ESP32_PCNT_MODULE>;
178			status = "disabled";
179		};
180
181		ledc0: ledc@3f419000 {
182			compatible = "espressif,esp32-ledc";
183			pwm-controller;
184			#pwm-cells = <3>;
185			reg = <0x3f419000 0x1000>;
186			clocks = <&rtc ESP32_LEDC_MODULE>;
187			status = "disabled";
188		};
189
190		gpio0: gpio@3f404000 {
191			compatible = "espressif,esp32-gpio";
192			gpio-controller;
193			#gpio-cells = <2>;
194			reg = <0x3f404000 0x800>;
195			interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
196			interrupt-parent = <&intc>;
197			/* Maximum available pins (per port)
198			 * Actual occupied pins are specified
199			 * on part number dtsi level, using
200			 * the `gpio-reserved-ranges` property.
201			 */
202			ngpios = <32>;   /* 0..31 */
203		};
204
205		gpio1: gpio@3f404800 {
206			compatible = "espressif,esp32-gpio";
207			gpio-controller;
208			#gpio-cells = <2>;
209			reg = <0x3f404800 0x800>;
210			interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
211			interrupt-parent = <&intc>;
212			ngpios = <22>;   /* 32..53 */
213		};
214
215		touch: touch@3f40885c {
216			compatible = "espressif,esp32-touch";
217			reg = <0x3f40885c 0xc0 0x3f408104 0x18>;
218			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
219			interrupt-parent = <&intc>;
220			status = "disabled";
221		};
222
223		i2c0: i2c@3f413000 {
224			compatible = "espressif,esp32-i2c";
225			#address-cells = <1>;
226			#size-cells = <0>;
227			reg = <0x3f413000 0x1000>;
228			interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
229			interrupt-parent = <&intc>;
230			clocks = <&rtc ESP32_I2C0_MODULE>;
231			status = "disabled";
232		};
233
234		i2c1: i2c@3f427000 {
235			compatible = "espressif,esp32-i2c";
236			#address-cells = <1>;
237			#size-cells = <0>;
238			reg = <0x3f427000 0x1000>;
239			interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
240			interrupt-parent = <&intc>;
241			clocks = <&rtc ESP32_I2C1_MODULE>;
242			status = "disabled";
243		};
244
245		timer0: counter@3f41f000 {
246			compatible = "espressif,esp32-timer";
247			reg = <0x3f41f000 DT_SIZE_K(4)>;
248			clocks = <&rtc ESP32_TIMG0_MODULE>;
249			group = <0>;
250			index = <0>;
251			interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
252			interrupt-parent = <&intc>;
253			status = "disabled";
254		};
255
256		timer1: counter@3f41f024 {
257			compatible = "espressif,esp32-timer";
258			reg = <0x3f41f024 DT_SIZE_K(4)>;
259			clocks = <&rtc ESP32_TIMG0_MODULE>;
260			group = <0>;
261			index = <1>;
262			interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
263			interrupt-parent = <&intc>;
264			status = "disabled";
265		};
266
267		timer2: counter@3f420000 {
268			compatible = "espressif,esp32-timer";
269			reg = <0x3f420000 DT_SIZE_K(4)>;
270			clocks = <&rtc ESP32_TIMG1_MODULE>;
271			group = <1>;
272			index = <0>;
273			interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
274			interrupt-parent = <&intc>;
275			status = "disabled";
276		};
277
278		timer3: counter@3f420024 {
279			compatible = "espressif,esp32-timer";
280			reg = <0x3f420024 DT_SIZE_K(4)>;
281			clocks = <&rtc ESP32_TIMG1_MODULE>;
282			group = <1>;
283			index = <1>;
284			interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
285			interrupt-parent = <&intc>;
286		};
287
288		trng0: trng@3f435110 {
289			compatible = "espressif,esp32-trng";
290			reg = <0x3f435110 0x4>;
291			status = "disabled";
292		};
293
294		spi2: spi@3f424000 {
295			compatible = "espressif,esp32-spi";
296			reg = <0x3f424000 DT_SIZE_K(4)>;
297			interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
298			interrupt-parent = <&intc>;
299			clocks = <&rtc ESP32_FSPI_MODULE>;
300			dma-clk = <ESP32_SPI2_DMA_MODULE>;
301			dma-host = <0>;
302			status = "disabled";
303		};
304
305		spi3: spi@3f425000 {
306			compatible = "espressif,esp32-spi";
307			reg = <0x3f425000 DT_SIZE_K(4)>;
308			interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
309			interrupt-parent = <&intc>;
310			clocks = <&rtc ESP32_HSPI_MODULE>;
311			dma-clk = <ESP32_SPI3_DMA_MODULE>;
312			dma-host = <1>;
313			status = "disabled";
314		};
315
316		wdt0: watchdog@3f41f048 {
317			compatible = "espressif,esp32-watchdog";
318			reg = <0x3f41f048 0x20>;
319			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
320			interrupt-parent = <&intc>;
321			clocks = <&rtc ESP32_TIMG0_MODULE>;
322			status = "disabled";
323		};
324
325		wdt1: watchdog@3f42f048 {
326			compatible = "espressif,esp32-watchdog";
327			reg = <0x3f42f048 0x20>;
328			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
329			interrupt-parent = <&intc>;
330			clocks = <&rtc ESP32_TIMG1_MODULE>;
331			status = "disabled";
332		};
333
334		dac: dac@3f408800 {
335			compatible = "espressif,esp32-dac";
336			reg = <0x3f408800 0x100>;
337			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
338			interrupt-parent = <&intc>;
339			clocks = <&rtc ESP32_PERIPH_SARADC_MODULE>;
340			#io-channel-cells = <1>;
341		};
342
343		coretemp: coretemp@3f408800 {
344			compatible = "espressif,esp32-temp";
345			friendly-name = "coretemp";
346			reg = <0x3f408800 0x4>;
347			status = "disabled";
348		};
349
350		adc0: adc@3f440018 {
351			compatible = "espressif,esp32-adc";
352			reg = <0x3f440018 100>;
353			unit = <1>;
354			channel-count = <10>;
355			#io-channel-cells = <1>;
356			status = "disabled";
357		};
358
359		adc1: adc@3f440028 {
360			compatible = "espressif,esp32-adc";
361			reg = <0x3f440028 100>;
362			unit = <2>;
363			channel-count = <10>;
364			#io-channel-cells = <1>;
365			status = "disabled";
366		};
367
368		twai: can@3f42b000 {
369			compatible = "espressif,esp32-twai";
370			reg = <0x3f42b000 DT_SIZE_K(4)>;
371			interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
372			interrupt-parent = <&intc>;
373			clocks = <&rtc ESP32_TWAI_MODULE>;
374			status = "disabled";
375		};
376	};
377
378};
379