1/*
2 * Copyright (c) 2019 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <freq.h>
8#include <xtensa/xtensa.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/clock/esp32_clock.h>
13#include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
14#include <dt-bindings/pinctrl/esp32-pinctrl.h>
15#include <zephyr/dt-bindings/pwm/pwm.h>
16
17/ {
18	chosen {
19		zephyr,canbus = &twai;
20		zephyr,entropy = &trng0;
21		zephyr,flash-controller = &flash;
22		zephyr,bt-hci = &esp32_bt_hci;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@0 {
30			device_type = "cpu";
31			compatible = "espressif,xtensa-lx6";
32			reg = <0>;
33			cpu-power-states = <&light_sleep &deep_sleep>;
34			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
35			clock-frequency = <DT_FREQ_M(240)>;
36			xtal-freq = <DT_FREQ_M(40)>;
37		};
38
39		cpu1: cpu@1 {
40			device_type = "cpu";
41			compatible = "espressif,xtensa-lx6";
42			reg = <1>;
43			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
44			clock-frequency = <DT_FREQ_M(240)>;
45			xtal-freq = <DT_FREQ_M(40)>;
46		};
47
48		power-states {
49			light_sleep: light_sleep {
50				compatible = "zephyr,power-state";
51				power-state-name = "standby";
52				min-residency-us = <200>;
53				exit-latency-us = <60>;
54			};
55
56			deep_sleep: deep_sleep {
57				compatible = "zephyr,power-state";
58				power-state-name = "soft-off";
59				min-residency-us = <2000>;
60				exit-latency-us = <212>;
61			};
62		};
63	};
64
65	wifi: wifi {
66		compatible = "espressif,esp32-wifi";
67		status = "disabled";
68	};
69
70	esp32_bt_hci: esp32_bt_hci {
71		compatible = "espressif,esp32-bt-hci";
72		status = "disabled";
73	};
74
75	eth: eth {
76		compatible = "espressif,esp32-eth";
77		interrupts = <ETH_MAC_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
78		interrupt-parent = <&intc>;
79		clocks = <&rtc ESP32_EMAC_MODULE>;
80		status = "disabled";
81	};
82
83	mdio: mdio {
84		compatible = "espressif,esp32-mdio";
85		clocks = <&rtc ESP32_EMAC_MODULE>;
86		status = "disabled";
87		#address-cells = <1>;
88		#size-cells = <0>;
89	};
90
91	pinctrl: pin-controller {
92		compatible = "espressif,esp32-pinctrl";
93		status = "okay";
94	};
95
96	soc {
97		sram0: memory@40070000 {
98			compatible = "zephyr,memory-region", "mmio-sram";
99			reg = <0x40070000 DT_SIZE_K(192)>;
100			zephyr,memory-region = "SRAM0";
101		};
102
103		sram1: memory@3ffe0000 {
104			compatible = "zephyr,memory-region", "mmio-sram";
105			reg = <0x3ffe0000 DT_SIZE_K(128)>;
106			zephyr,memory-region = "SRAM1";
107		};
108
109		sram2: memory@3ffae000 {
110			compatible = "zephyr,memory-region", "mmio-sram";
111			reg = <0x3ffae000 DT_SIZE_K(200)>;
112			zephyr,memory-region = "SRAM2";
113		};
114
115		ipmmem0: memory@3ffe5230 {
116			compatible = "mmio-sram";
117			reg = <0x3ffe5230 0x400>;
118		};
119
120		shm0: memory@3ffe5630 {
121			compatible = "mmio-sram";
122			reg = <0x3ffe5630 0x4000>;
123		};
124
125		ipm0: ipm@3ffe9630 {
126			compatible = "espressif,esp32-ipm";
127			reg = <0x3ffe9630 0x8>;
128			status = "disabled";
129			shared-memory = <&ipmmem0>;
130			shared-memory-size = <0x400>;
131			interrupts =
132				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
133				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
134			interrupt-parent = <&intc>;
135		};
136
137		mbox0: mbox@3ffe9638 {
138			compatible = "espressif,mbox-esp32";
139			reg = <0x3ffe9638 0x8>;
140			status = "disabled";
141			shared-memory = <&ipmmem0>;
142			shared-memory-size = <0x400>;
143			interrupts =
144				<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
145				<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
146			interrupt-parent = <&intc>;
147			#mbox-cells = <1>;
148		};
149
150		intc: interrupt-controller@3ff00104 {
151			#interrupt-cells = <3>;
152			#address-cells = <0>;
153			compatible = "espressif,esp32-intc";
154			interrupt-controller;
155			reg = <0x3ff00104 0x114>;
156			status = "okay";
157		};
158
159		rtc: rtc@3ff48000 {
160			compatible = "espressif,esp32-rtc";
161			reg = <0x3ff48000 0x0D8>;
162			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
163			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
164			#clock-cells = <1>;
165			status = "okay";
166
167		};
168
169		rtc_timer: rtc_timer@3ff48004 {
170			reg = <0x3ff48004 0xC>;
171			compatible = "espressif,esp32-rtc-timer";
172			clocks = <&rtc ESP32_MODULE_MAX>;
173			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
174			interrupt-parent = <&intc>;
175			status = "okay";
176		};
177
178		flash: flash-controller@3ff42000 {
179			compatible = "espressif,esp32-flash-controller";
180			reg = <0x3ff42000 0x1000>;
181			#address-cells = <1>;
182			#size-cells = <1>;
183
184			flash0: flash@0 {
185				compatible = "soc-nv-flash";
186				erase-block-size = <4096>;
187				write-block-size = <4>;
188				/* Flash size is specified in SOC/SIP dtsi */
189			};
190		};
191
192		psram0: psram@3f800000 {
193			device_type = "memory";
194			compatible = "mmio-sram";
195			/* PSRAM size is specified in SOC/SIP dtsi */
196			reg = <0x3f800000 DT_SIZE_M(2)>;
197			status = "disabled";
198		};
199
200		ipi0: ipi@3f4c0058 {
201			compatible = "espressif,crosscore-interrupt";
202			reg = <0x3f4c0058 0x4>;
203			interrupts = <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>;
204			interrupt-parent = <&intc>;
205		};
206
207		ipi1: ipi@3f4c005c {
208			compatible = "espressif,crosscore-interrupt";
209			reg = <0x3f4c005c 0x4>;
210			interrupts = <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
211			interrupt-parent = <&intc>;
212		};
213
214		uart0: uart@3ff40000 {
215			compatible = "espressif,esp32-uart";
216			reg = <0x3ff40000 0x400>;
217			interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
218			interrupt-parent = <&intc>;
219			clocks = <&rtc ESP32_UART0_MODULE>;
220			status = "disabled";
221		};
222
223		uart1: uart@3ff50000 {
224			compatible = "espressif,esp32-uart";
225			reg = <0x3ff50000 0x400>;
226			interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
227			interrupt-parent = <&intc>;
228			clocks = <&rtc ESP32_UART1_MODULE>;
229			status = "disabled";
230		};
231
232		uart2: uart@3ff6e000 {
233			compatible = "espressif,esp32-uart";
234			reg = <0x3ff6E000 0x400>;
235			interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
236			interrupt-parent = <&intc>;
237			clocks = <&rtc ESP32_UART2_MODULE>;
238			status = "disabled";
239		};
240
241		pcnt: pcnt@3ff57000 {
242			compatible = "espressif,esp32-pcnt";
243			reg = <0x3ff57000 0x1000>;
244			interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
245			interrupt-parent = <&intc>;
246			clocks = <&rtc ESP32_PCNT_MODULE>;
247			status = "disabled";
248		};
249
250		ledc0: ledc@3ff59000 {
251			compatible = "espressif,esp32-ledc";
252			#pwm-cells = <3>;
253			reg = <0x3ff59000 0x800>;
254			clocks = <&rtc ESP32_LEDC_MODULE>;
255			status = "disabled";
256		};
257
258		mcpwm0: mcpwm@3ff5e000 {
259			compatible = "espressif,esp32-mcpwm";
260			reg = <0x3ff5e000 0x1000>;
261			interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
262			interrupt-parent = <&intc>;
263			clocks = <&rtc ESP32_PWM0_MODULE>;
264			#pwm-cells = <3>;
265			status = "disabled";
266		};
267
268		mcpwm1: mcpwm@3ff6c000 {
269			compatible = "espressif,esp32-mcpwm";
270			reg = <0x3ff6c000 0x1000>;
271			interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
272			interrupt-parent = <&intc>;
273			clocks = <&rtc ESP32_PWM1_MODULE>;
274			#pwm-cells = <3>;
275			status = "disabled";
276		};
277
278		gpio: gpio {
279			compatible = "simple-bus";
280			gpio-map-mask = <0xffffffe0 0xffffffc0>;
281			gpio-map-pass-thru = <0x1f 0x3f>;
282			gpio-map = <
283				0x00 0x0 &gpio0 0x0 0x0
284				0x20 0x0 &gpio1 0x0 0x0
285			>;
286			#gpio-cells = <2>;
287			#address-cells = <1>;
288			#size-cells = <1>;
289			ranges;
290
291			gpio0: gpio@3ff44000 {
292				compatible = "espressif,esp32-gpio";
293				gpio-controller;
294				#gpio-cells = <2>;
295				reg = <0x3ff44000 0x800>;
296				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
297				interrupt-parent = <&intc>;
298				/* Maximum available pins (per port)
299				 * Actual occupied pins are specified
300				 * on part number dtsi level, using
301				 * the `gpio-reserved-ranges` property.
302				 */
303				ngpios = <32>;   /* 0..31 */
304			};
305
306			gpio1: gpio@3ff44800 {
307				compatible = "espressif,esp32-gpio";
308				gpio-controller;
309				#gpio-cells = <2>;
310				reg = <0x3ff44800 0x800>;
311				interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
312				interrupt-parent = <&intc>;
313				ngpios = <8>;   /* 32..39 */
314			};
315		};
316
317		touch: touch@3ff48858 {
318			compatible = "espressif,esp32-touch";
319			reg = <0x3ff48858 0x38>;
320			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
321			interrupt-parent = <&intc>;
322			status = "disabled";
323		};
324
325		i2c0: i2c@3ff53000 {
326			compatible = "espressif,esp32-i2c";
327			#address-cells = <1>;
328			#size-cells = <0>;
329			reg = <0x3ff53000 0x1000>;
330			interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
331			interrupt-parent = <&intc>;
332			clocks = <&rtc ESP32_I2C0_MODULE>;
333			status = "disabled";
334		};
335
336		i2c1: i2c@3ff67000 {
337			compatible = "espressif,esp32-i2c";
338			#address-cells = <1>;
339			#size-cells = <0>;
340			reg = <0x3ff67000 0x1000>;
341			interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
342			interrupt-parent = <&intc>;
343			clocks = <&rtc ESP32_I2C1_MODULE>;
344			status = "disabled";
345		};
346
347		trng0: trng@3ff75144 {
348			compatible = "espressif,esp32-trng";
349			reg = <0x3FF75144 0x4>;
350			status = "disabled";
351		};
352
353		wdt0: watchdog@3ff5f048 {
354			compatible = "espressif,esp32-watchdog";
355			reg = <0x3ff5f048 0x20>;
356			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
357			interrupt-parent = <&intc>;
358			clocks = <&rtc ESP32_TIMG0_MODULE>;
359			status = "okay";
360		};
361
362		wdt1: watchdog@3ff60048 {
363			compatible = "espressif,esp32-watchdog";
364			reg = <0x3ff60048 0x20>;
365			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
366			interrupt-parent = <&intc>;
367			clocks = <&rtc ESP32_TIMG1_MODULE>;
368			status = "disabled";
369		};
370
371		spi2: spi@3ff64000 {
372			compatible = "espressif,esp32-spi";
373			reg = <0x3ff64000 DT_SIZE_K(4)>;
374			interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
375			interrupt-parent = <&intc>;
376			clocks = <&rtc ESP32_HSPI_MODULE>;
377			dma-clk = <ESP32_SPI_DMA_MODULE>;
378			dma-host = <0>;
379			status = "disabled";
380		};
381
382		spi3: spi@3ff65000 {
383			compatible = "espressif,esp32-spi";
384			reg = <0x3ff65000 DT_SIZE_K(4)>;
385			interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
386			interrupt-parent = <&intc>;
387			clocks = <&rtc ESP32_VSPI_MODULE>;
388			dma-clk = <ESP32_SPI_DMA_MODULE>;
389			dma-host = <1>;
390			status = "disabled";
391		};
392
393		twai: can@3ff6b000 {
394			compatible = "espressif,esp32-twai";
395			reg = <0x3ff6b000 DT_SIZE_K(4)>;
396			interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
397			interrupt-parent = <&intc>;
398			clocks = <&rtc ESP32_TWAI_MODULE>;
399			status = "disabled";
400		};
401
402		timer0: counter@3ff5f000 {
403			compatible = "espressif,esp32-timer";
404			reg = <0x3ff5f000 DT_SIZE_K(4)>;
405			clocks = <&rtc ESP32_TIMG0_MODULE>;
406			group = <0>;
407			index = <0>;
408			interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
409			interrupt-parent = <&intc>;
410			status = "disabled";
411		};
412
413		timer1: counter@3ff5f024 {
414			compatible = "espressif,esp32-timer";
415			reg = <0x3ff5f024 DT_SIZE_K(4)>;
416			clocks = <&rtc ESP32_TIMG0_MODULE>;
417			group = <0>;
418			index = <1>;
419			interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
420			interrupt-parent = <&intc>;
421			status = "disabled";
422		};
423
424		timer2: counter@3ff60000 {
425			compatible = "espressif,esp32-timer";
426			reg = <0x3ff60000 DT_SIZE_K(4)>;
427			clocks = <&rtc ESP32_TIMG1_MODULE>;
428			group = <1>;
429			index = <0>;
430			interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
431			interrupt-parent = <&intc>;
432			status = "disabled";
433		};
434
435		timer3: counter@3ff60024 {
436			compatible = "espressif,esp32-timer";
437			reg = <0x3ff60024 DT_SIZE_K(4)>;
438			clocks = <&rtc ESP32_TIMG1_MODULE>;
439			group = <1>;
440			index = <1>;
441			interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
442			interrupt-parent = <&intc>;
443			status = "disabled";
444		};
445
446		dac: dac@3ff48800 {
447			compatible = "espressif,esp32-dac";
448			reg = <0x3ff48800 0x100>;
449			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
450			interrupt-parent = <&intc>;
451			clocks = <&rtc ESP32_SARADC_MODULE>;
452			#io-channel-cells = <1>;
453			status = "disabled";
454		};
455
456		adc0: adc@3ff48800 {
457			compatible = "espressif,esp32-adc";
458			reg = <0x3ff48800 10>;
459			unit = <1>;
460			channel-count = <8>;
461			#io-channel-cells = <1>;
462			status = "disabled";
463		};
464
465		adc1: adc@3ff48890 {
466			compatible = "espressif,esp32-adc";
467			reg = <0x3ff48890 10>;
468			unit = <2>;
469			channel-count = <10>;
470			#io-channel-cells = <1>;
471			status = "disabled";
472		};
473
474		sdhc: sdhc@3ff68000 {
475			compatible = "espressif,esp32-sdhc";
476			reg = <0x3ff68000 0x1000>;
477			interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
478			interrupt-parent = <&intc>;
479			clocks = <&rtc ESP32_SDMMC_MODULE>;
480			#address-cells = <1>;
481			#size-cells = <0>;
482
483			sdhc0: sdhc@0 {
484				compatible = "espressif,esp32-sdhc-slot";
485				reg = <0>;
486				status = "disabled";
487			};
488
489			sdhc1: sdhc@1 {
490				compatible = "espressif,esp32-sdhc-slot";
491				reg = <1>;
492				status = "disabled";
493			};
494		};
495	};
496};
497