1/*
2 * Copyright 2021,2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/power/imx_spc.h>
15#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
16/ {
17	chosen {
18		zephyr,entropy = &caam;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m7";
28			reg = <0>;
29
30			#address-cells = <1>;
31			#size-cells = <1>;
32			d-cache-line-size = <32>;
33
34			mpu: mpu@e000ed90 {
35				compatible = "arm,armv7m-mpu";
36				reg = <0xe000ed90 0x40>;
37			};
38		};
39		cpu1: cpu@1 {
40			device_type = "cpu";
41			compatible = "arm,cortex-m4f";
42			reg = <1>;
43			d-cache-line-size = <32>;
44
45			#address-cells = <1>;
46			#size-cells = <1>;
47
48			mpu: mpu@e000ed90 {
49				compatible = "arm,armv7m-mpu";
50				reg = <0xe000ed90 0x40>;
51			};
52		};
53
54		power-states {
55			/*
56			 * Power states are managed with set points (see page 30-35 of RT1170
57			 * datasheet). These set points correspond to various power
58			 * savings, and associated transition (residency) times.
59			 *
60			 * Set points 1 and 10 were chosen as sane defaults to offer
61			 * limited power savings and quick transitions when entering idle for
62			 * short periods, and better power savings with longer transition
63			 * times for long idle periods
64			 */
65			idle: set_point_1_wait {
66				/* idle corresponds to set point 1 (wait) for RT1170 */
67				compatible = "zephyr,power-state";
68				power-state-name="runtime-idle";
69				substate-id = <IMX_SPC_SET_POINT_1_WAIT>;
70				min-residency-us = <100>;
71			};
72
73			suspend: set_point_10_suspend {
74				/*  suspend corresponds to set point 10 for RT1170 */
75				compatible = "zephyr,power-state";
76				power-state-name="suspend-to-idle";
77				substate-id = <IMX_SPC_SET_POINT_10_SUSPEND>;
78				min-residency-us = <5000>;
79				exit-latency-us = <500>;
80			};
81		};
82	};
83
84	xtal: xtal-osc {
85		compatible = "fixed-clock";
86		clock-frequency = <24000000>;
87		#clock-cells = <0>;
88	};
89
90	soc {
91		flexspi: spi@400cc000 {
92			compatible = "nxp,imx-flexspi";
93			reg = <0x400cc000 0x4000>;
94			interrupts = <130 0>;
95			#address-cells = <1>;
96			#size-cells = <0>;
97			status = "disabled";
98			clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
99		};
100
101		flexspi2: spi@400d0000 {
102			compatible = "nxp,imx-flexspi";
103			reg = <0x400d0000 0x4000>;
104			interrupts = <131 0>;
105			#address-cells = <1>;
106			#size-cells = <0>;
107			status = "disabled";
108			clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>;
109		};
110
111		semc: semc0@400d4000 {
112			compatible = "nxp,imx-semc";
113			reg = <0x400d4000 0x4000>;
114			interrupts = <132 0>;
115			#address-cells = <1>;
116			#size-cells = <1>;
117		};
118
119		/* GPT1 is used for the hardware timer, not as a standard counter */
120		gpt_hw_timer: gpt@400ec000 {
121			compatible = "nxp,gpt-hw-timer";
122			reg = <0x400ec000 0x4000>;
123			interrupts = <119 0>;
124			status = "disabled";
125		};
126
127		gpt2: gpt@400f0000 {
128			compatible = "nxp,imx-gpt";
129			reg = <0x400f0000 0x4000>;
130			interrupts = <120 0>;
131			gptfreq = <24000000>;
132			clocks = <&ccm IMX_CCM_GPT_CLK 0x41 0>;
133		};
134
135		gpt3: gpt@400f4000 {
136			compatible = "nxp,imx-gpt";
137			reg = <0x400f4000 0x4000>;
138			interrupts = <121 0>;
139			gptfreq = <24000000>;
140			clocks = <&ccm IMX_CCM_GPT_CLK 0x42 0>;
141		};
142
143		gpt4: gpt@400f8000 {
144			compatible = "nxp,imx-gpt";
145			reg = <0x400f8000 0x4000>;
146			interrupts = <122 0>;
147			gptfreq = <24000000>;
148			clocks = <&ccm IMX_CCM_GPT_CLK 0x43 0>;
149		};
150
151		gpt5: gpt@400fc000 {
152			compatible = "nxp,imx-gpt";
153			reg = <0x400fc000 0x4000>;
154			interrupts = <123 0>;
155			gptfreq = <24000000>;
156			clocks = <&ccm IMX_CCM_GPT_CLK 0x44 0>;
157		};
158
159		gpt6: gpt@40100000 {
160			compatible = "nxp,imx-gpt";
161			reg = <0x40100000 0x4000>;
162			interrupts = <124 0>;
163			gptfreq = <24000000>;
164			clocks = <&ccm IMX_CCM_GPT_CLK 0x45 0>;
165		};
166
167		qtmr1: qtmr@4015c000 {
168			compatible = "nxp,qtmr-pwm";
169			reg = <0x4015c000 0x4000>;
170			interrupts = <171 0>;
171			status = "disabled";
172			clocks = <&ccm IMX_CCM_QTMR1_CLK 0x0 0>;
173		};
174
175		qtmr2: qtmr@40160000 {
176			compatible = "nxp,qtmr-pwm";
177			reg = <0x40160000 0x4000>;
178			interrupts = <172 0>;
179			status = "disabled";
180			clocks = <&ccm IMX_CCM_QTMR2_CLK 0x0 0>;
181		};
182
183		qtmr3: qtmr@40164000 {
184			compatible = "nxp,qtmr-pwm";
185			reg = <0x40164000 0x4000>;
186			interrupts = <173 0>;
187			status = "disabled";
188			clocks = <&ccm IMX_CCM_QTMR3_CLK 0x0 0>;
189		};
190
191		qtmr4: qtmr@40168000 {
192			compatible = "nxp,qtmr-pwm";
193			reg = <0x40168000 0x4000>;
194			interrupts = <174 0>;
195			status = "disabled";
196			clocks = <&ccm IMX_CCM_QTMR4_CLK 0x0 0>;
197		};
198
199		ccm: ccm@40cc0000 {
200			compatible = "nxp,imx-ccm-rev2";
201			reg = <0x40cc0000 0x4000>;
202
203			#clock-cells = <3>;
204
205			/*
206			 * ARM PLL is an integer PLL, with an input clock
207			 * of 24MHz. The PLL features a loop divider and
208			 * post divider. The output frequency is calculated
209			 * as Fout = 24MHz * (clock-mult / clock-div)
210			 */
211			arm_pll: arm-pll {
212				compatible = "fixed-factor-clock";
213				#clock-cells = <0>;
214			};
215
216		};
217
218		gpio1: gpio@4012c000 {
219			compatible = "nxp,imx-gpio";
220			reg = <0x4012c000 0x4000>;
221			interrupts = <100 0>, <101 0>;
222			gpio-controller;
223			#gpio-cells = <2>;
224		};
225
226		/*
227		 * Note that CM7 and CM4 cores do not have the same memory addresses
228		 * for GPIO2 and GPIO3, so those peripherals are defined in the SOC
229		 * specific DTS files
230		 */
231
232		gpio4: gpio@40138000 {
233			compatible = "nxp,imx-gpio";
234			reg = <0x40138000 0x4000>;
235			interrupts = <106 0>, <107 0>;
236			gpio-controller;
237			#gpio-cells = <2>;
238		};
239
240		gpio5: gpio@4013c000 {
241			compatible = "nxp,imx-gpio";
242			reg = <0x4013c000 0x4000>;
243			interrupts = <108 0>, <109 0>;
244			gpio-controller;
245			#gpio-cells = <2>;
246		};
247
248		gpio6: gpio@40140000 {
249			compatible = "nxp,imx-gpio";
250			reg = <0x40140000 0x4000>;
251			gpio-controller;
252			#gpio-cells = <2>;
253		};
254
255		gpio7: gpio@40c5c000 {
256			compatible = "nxp,imx-gpio";
257			reg = <0x40c5c000 0x4000>;
258			gpio-controller;
259			#gpio-cells = <2>;
260		};
261
262		gpio8: gpio@40c60000 {
263			compatible = "nxp,imx-gpio";
264			reg = <0x40c60000 0x4000>;
265			gpio-controller;
266			#gpio-cells = <2>;
267		};
268
269		gpio9: gpio@40c64000 {
270			compatible = "nxp,imx-gpio";
271			reg = <0x40c64000 0x4000>;
272			gpio-controller;
273			#gpio-cells = <2>;
274		};
275
276		gpio10: gpio@40c68000 {
277			compatible = "nxp,imx-gpio";
278			reg = <0x40c68000 0x4000>;
279			gpio-controller;
280			#gpio-cells = <2>;
281		};
282
283		gpio11: gpio@40c6c000 {
284			compatible = "nxp,imx-gpio";
285			reg = <0x40c6c000 0x4000>;
286			gpio-controller;
287			#gpio-cells = <2>;
288		};
289
290		gpio12: gpio@40c70000 {
291			compatible = "nxp,imx-gpio";
292			reg = <0x40c70000 0x4000>;
293			gpio-controller;
294			#gpio-cells = <2>;
295		};
296
297		gpio13: gpio@40ca0000 {
298			compatible = "nxp,imx-gpio";
299			reg = <0x40ca0000 0x4000>;
300			interrupts = <93 0>;
301			gpio-controller;
302			#gpio-cells = <2>;
303		};
304
305		lpi2c1: i2c@40104000 {
306			compatible = "nxp,lpi2c";
307			clock-frequency = <I2C_BITRATE_STANDARD>;
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x40104000 0x4000>;
311			interrupts = <32 0>;
312			clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
313			status = "disabled";
314		};
315
316		lpi2c2: i2c@40108000 {
317			compatible = "nxp,lpi2c";
318			clock-frequency = <I2C_BITRATE_STANDARD>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			reg = <0x40108000 0x4000>;
322			interrupts = <33 0>;
323			clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
324			status = "disabled";
325		};
326
327		lpi2c3: i2c@4010c000 {
328			compatible = "nxp,lpi2c";
329			clock-frequency = <I2C_BITRATE_STANDARD>;
330			#address-cells = <1>;
331			#size-cells = <0>;
332			reg = <0x4010c000 0x4000>;
333			interrupts = <34 0>;
334			clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
335			status = "disabled";
336		};
337
338		lpi2c4: i2c@40110000 {
339			compatible = "nxp,lpi2c";
340			clock-frequency = <I2C_BITRATE_STANDARD>;
341			#address-cells = <1>;
342			#size-cells = <0>;
343			reg = <0x40110000 0x4000>;
344			interrupts = <35 0>;
345			clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
346			status = "disabled";
347		};
348
349		lpi2c5: i2c@40c34000 {
350			compatible = "nxp,lpi2c";
351			clock-frequency = <I2C_BITRATE_STANDARD>;
352			#address-cells = <1>;
353			#size-cells = <0>;
354			reg = <0x40c34000 0x4000>;
355			interrupts = <36 0>;
356			clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
357			status = "disabled";
358		};
359
360		lpi2c6: i2c@40c38000 {
361			compatible = "nxp,lpi2c";
362			clock-frequency = <I2C_BITRATE_STANDARD>;
363			#address-cells = <1>;
364			#size-cells = <0>;
365			reg = <0x40c38000 0x4000>;
366			interrupts = <37 0>;
367			clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
368			status = "disabled";
369		};
370
371		iomuxc: iomuxc@400e8000 {
372			compatible = "nxp,imx-iomuxc";
373			reg = <0x400e8000 0x4000>;
374			status = "okay";
375			pinctrl: pinctrl {
376				status = "okay";
377				compatible = "nxp,mcux-rt11xx-pinctrl";
378			};
379		};
380
381		iomuxc_lpsr: iomuxc_lpsr@40c08000 {
382			compatible = "nxp,mcux-rt-pinctrl";
383			reg = <0x40c08000 0x4000>;
384			status = "disabled";
385		};
386
387		iomuxc_lpsr_gpr: iomuxc_lpsr_gpr@40c08000 {
388			compatible = "nxp,imx-gpr";
389			reg = <0x40c08000 0x4000>;
390			#pinmux-cells = <2>;
391		};
392
393		lcdif: display-controller@40804000 {
394			compatible = "nxp,imx-elcdif";
395			reg = <0x40804000 0x4000>;
396			interrupts = <54 0>;
397			status = "disabled";
398			nxp,pxp = <&pxp>;
399		};
400
401		mipi_dsi: mipi-dsi@4080c000 {
402			compatible = "nxp,imx-mipi-dsi";
403			#address-cells = <1>;
404			#size-cells = <0>;
405			reg = <0x4080c000 0x200>,
406			      <0x4080c200 0x80>,
407			      <0x4080c280 0x80>,
408			      <0x4080c300 0x200>;
409			interrupts = <59 1>;
410			status = "disabled";
411		};
412
413		lpspi1: spi@40114000 {
414			compatible = "nxp,lpspi";
415			reg = <0x40114000 0x4000>;
416			interrupts = <38 3>;
417			status = "disabled";
418			clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
419			#address-cells = <1>;
420			#size-cells = <0>;
421		};
422
423		lpspi2: spi@40118000 {
424			compatible = "nxp,lpspi";
425			reg = <0x40118000 0x4000>;
426			interrupts = <39 3>;
427			status = "disabled";
428			clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
429			#address-cells = <1>;
430			#size-cells = <0>;
431		};
432
433		lpspi3: spi@4011c000 {
434			compatible = "nxp,lpspi";
435			reg = <0x4011c000 0x4000>;
436			interrupts = <40 3>;
437			status = "disabled";
438			clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
439			#address-cells = <1>;
440			#size-cells = <0>;
441		};
442
443		lpspi4: spi@40120000 {
444			compatible = "nxp,lpspi";
445			reg = <0x40120000 0x4000>;
446			interrupts = <41 3>;
447			status = "disabled";
448			clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
449			#address-cells = <1>;
450			#size-cells = <0>;
451		};
452
453		lpspi5: spi@40c2c000 {
454			compatible = "nxp,lpspi";
455			reg = <0x40c2c000 0x4000>;
456			interrupts = <42 3>;
457			status = "disabled";
458			clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
459			#address-cells = <1>;
460			#size-cells = <0>;
461		};
462
463		lpspi6: spi@40c30000 {
464			compatible = "nxp,lpspi";
465			reg = <0x40c30000 0x4000>;
466			interrupts = <43 3>;
467			status = "disabled";
468			clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471		};
472
473		lpuart1: uart@4007c000 {
474			compatible = "nxp,lpuart";
475			reg = <0x4007c000 0x4000>;
476			interrupts = <20 0>;
477			clocks = <&ccm IMX_CCM_LPUART1_CLK 0x7c 24>;
478			status = "disabled";
479		};
480
481		lpuart2: uart@40080000 {
482			compatible = "nxp,lpuart";
483			reg = <0x40080000 0x4000>;
484			interrupts = <21 0>;
485			clocks = <&ccm IMX_CCM_LPUART2_CLK 0x68 28>;
486			status = "disabled";
487		};
488
489		lpuart3: uart@40084000 {
490			compatible = "nxp,lpuart";
491			reg = <0x40084000 0x4000>;
492			interrupts = <22 0>;
493			clocks = <&ccm IMX_CCM_LPUART3_CLK 0x68 12>;
494			status = "disabled";
495		};
496
497		lpuart4: uart@40088000 {
498			compatible = "nxp,lpuart";
499			reg = <0x40088000 0x4000>;
500			interrupts = <23 0>;
501			clocks = <&ccm IMX_CCM_LPUART4_CLK 0x6c 24>;
502			status = "disabled";
503		};
504
505		lpuart5: uart@4008c000 {
506			compatible = "nxp,lpuart";
507			reg = <0x4008c000 0x4000>;
508			interrupts = <24 0>;
509			clocks = <&ccm IMX_CCM_LPUART5_CLK 0x74 2>;
510			status = "disabled";
511		};
512
513		lpuart6: uart@40090000 {
514			compatible = "nxp,lpuart";
515			reg = <0x40090000 0x4000>;
516			interrupts = <25 0>;
517			clocks = <&ccm IMX_CCM_LPUART6_CLK 0x74 6>;
518			status = "disabled";
519		};
520
521		lpuart7: uart@40094000 {
522			compatible = "nxp,lpuart";
523			reg = <0x40094000 0x4000>;
524			interrupts = <26 0>;
525			clocks = <&ccm IMX_CCM_LPUART7_CLK 0x7c 26>;
526			status = "disabled";
527		};
528
529		lpuart8: uart@40098000 {
530			compatible = "nxp,lpuart";
531			reg = <0x40098000 0x4000>;
532			interrupts = <27 0>;
533			clocks = <&ccm IMX_CCM_LPUART8_CLK 0x80 14>;
534			status = "disabled";
535		};
536
537		lpuart9: uart@4009c000 {
538			compatible = "nxp,lpuart";
539			reg = <0x4009c000 0x4000>;
540			interrupts = <28 0>;
541			clocks = <&ccm IMX_CCM_LPUART9_CLK 0x80 14>;
542			status = "disabled";
543		};
544
545		lpuart10: uart@400a0000 {
546			compatible = "nxp,lpuart";
547			reg = <0x400a0000 0x4000>;
548			interrupts = <29 0>;
549			clocks = <&ccm IMX_CCM_LPUART10_CLK 0x80 14>;
550			status = "disabled";
551		};
552
553		lpuart11: uart@40c24000 {
554			compatible = "nxp,lpuart";
555			reg = <0x40c24000 0x4000>;
556			interrupts = <30 0>;
557			clocks = <&ccm IMX_CCM_LPUART11_CLK 0x80 14>;
558			status = "disabled";
559		};
560
561		lpuart12: uart@40c28000 {
562			compatible = "nxp,lpuart";
563			reg = <0x40c28000 0x4000>;
564			interrupts = <31 0>;
565			clocks = <&ccm IMX_CCM_LPUART12_CLK 0x80 14>;
566			status = "disabled";
567		};
568
569		flexpwm1: flexpwm@4018c000 {
570			compatible = "nxp,flexpwm";
571			reg = <0x4018c000 0x4000>;
572			interrupts = <129 0>;
573
574			flexpwm1_pwm0: flexpwm1_pwm0 {
575				compatible = "nxp,imx-pwm";
576				index = <0>;
577				interrupts = <125 0>;
578				#pwm-cells = <3>;
579				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
580				nxp,prescaler = <128>;
581				status = "disabled";
582			};
583
584			flexpwm1_pwm1: flexpwm1_pwm1 {
585				compatible = "nxp,imx-pwm";
586				index = <1>;
587				interrupts = <126 0>;
588				#pwm-cells = <3>;
589				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
590				nxp,prescaler = <128>;
591				status = "disabled";
592			};
593
594			flexpwm1_pwm2: flexpwm1_pwm2 {
595				compatible = "nxp,imx-pwm";
596				index = <2>;
597				interrupts = <127 0>;
598				#pwm-cells = <3>;
599				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
600				nxp,prescaler = <128>;
601				status = "disabled";
602			};
603
604			flexpwm1_pwm3: flexpwm1_pwm3 {
605				compatible = "nxp,imx-pwm";
606				index = <3>;
607				interrupts = <128 0>;
608				#pwm-cells = <3>;
609				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
610				nxp,prescaler = <128>;
611				status = "disabled";
612			};
613		};
614
615		flexpwm2: flexpwm@40190000 {
616			compatible = "nxp,flexpwm";
617			reg = <0x40190000 0x4000>;
618			interrupts =  <181 0>;
619
620			flexpwm2_pwm0: flexpwm2_pwm0 {
621				compatible = "nxp,imx-pwm";
622				index = <0>;
623				interrupts = <177 0>;
624				#pwm-cells = <3>;
625				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
626				nxp,prescaler = <128>;
627				status = "disabled";
628			};
629
630			flexpwm2_pwm1: flexpwm2_pwm1 {
631				compatible = "nxp,imx-pwm";
632				index = <1>;
633				interrupts = <178 0>;
634				#pwm-cells = <3>;
635				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
636				nxp,prescaler = <128>;
637				status = "disabled";
638			};
639
640			flexpwm2_pwm2: flexpwm2_pwm2 {
641				compatible = "nxp,imx-pwm";
642				index = <2>;
643				interrupts = <179 0>;
644				#pwm-cells = <3>;
645				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
646				nxp,prescaler = <128>;
647				status = "disabled";
648			};
649
650			flexpwm2_pwm3: flexpwm2_pwm3 {
651				compatible = "nxp,imx-pwm";
652				index = <3>;
653				interrupts = <180 0>;
654				#pwm-cells = <3>;
655				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
656				nxp,prescaler = <128>;
657				status = "disabled";
658			};
659		};
660
661		flexpwm3: flexpwm@40194000 {
662			compatible = "nxp,flexpwm";
663			reg = <0x40194000 0x4000>;
664			interrupts =  <186 0>;
665
666			flexpwm3_pwm0: flexpwm3_pwm0 {
667				compatible = "nxp,imx-pwm";
668				index = <0>;
669				interrupts = <182 0>;
670				#pwm-cells = <3>;
671				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
672				nxp,prescaler = <128>;
673				status = "disabled";
674			};
675
676			flexpwm3_pwm1: flexpwm3_pwm1 {
677				compatible = "nxp,imx-pwm";
678				index = <1>;
679				interrupts = <183 0>;
680				#pwm-cells = <3>;
681				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
682				nxp,prescaler = <128>;
683				status = "disabled";
684			};
685
686			flexpwm3_pwm2: flexpwm3_pwm2 {
687				compatible = "nxp,imx-pwm";
688				index = <2>;
689				interrupts = <184 0>;
690				#pwm-cells = <3>;
691				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
692				nxp,prescaler = <128>;
693				status = "disabled";
694			};
695
696			flexpwm3_pwm3: flexpwm3_pwm3 {
697				compatible = "nxp,imx-pwm";
698				index = <3>;
699				interrupts = <185 0>;
700				#pwm-cells = <3>;
701				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
702				nxp,prescaler = <128>;
703				status = "disabled";
704			};
705		};
706
707		flexpwm4: flexpwm@40198000 {
708			compatible = "nxp,flexpwm";
709			reg = <0x40198000 0x4000>;
710			interrupts = <191 0>;
711
712			flexpwm4_pwm0: flexpwm4_pwm0 {
713				compatible = "nxp,imx-pwm";
714				index = <0>;
715				interrupts = <187 0>;
716				#pwm-cells = <3>;
717				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
718				nxp,prescaler = <128>;
719				status = "disabled";
720			};
721
722			flexpwm4_pwm1: flexpwm4_pwm1 {
723				compatible = "nxp,imx-pwm";
724				index = <1>;
725				interrupts = <188 0>;
726				#pwm-cells = <3>;
727				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
728				nxp,prescaler = <128>;
729				status = "disabled";
730			};
731
732			flexpwm4_pwm2: flexpwm4_pwm2 {
733				compatible = "nxp,imx-pwm";
734				index = <2>;
735				interrupts = <189 0>;
736				#pwm-cells = <3>;
737				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
738				nxp,prescaler = <128>;
739				status = "disabled";
740			};
741
742			flexpwm4_pwm3: flexpwm4_pwm3 {
743				compatible = "nxp,imx-pwm";
744				index = <3>;
745				interrupts = <190 0>;
746				#pwm-cells = <3>;
747				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
748				nxp,prescaler = <128>;
749				status = "disabled";
750			};
751		};
752
753		flexio1: flexio@400ac000 {
754			compatible = "nxp,flexio";
755			reg = <0x400ac000 0x4000>;
756			interrupts = <110 0>;
757			clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>;
758			status = "disabled";
759		};
760
761		flexio2: flexio@400b0000 {
762			compatible = "nxp,flexio";
763			reg = <0x400b0000 0x4000>;
764			interrupts = <111 0>;
765			clocks = <&ccm IMX_CCM_FLEXIO2_CLK 0 0>;
766			status = "disabled";
767		};
768
769		enet: ethernet@40424000 {
770			compatible = "nxp,enet";
771			reg = <0x40424000 0x628>;
772			clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
773			enet_mac: ethernet {
774				compatible = "nxp,enet-mac";
775				interrupts = <137 0>;
776				interrupt-names = "COMMON";
777				nxp,mdio = <&enet_mdio>;
778				nxp,ptp-clock = <&enet_ptp_clock>;
779				status = "disabled";
780			};
781			enet_mdio: mdio {
782				compatible = "nxp,enet-mdio";
783				status = "disabled";
784				#address-cells = <1>;
785				#size-cells = <0>;
786			};
787			enet_ptp_clock: ptp_clock {
788				compatible = "nxp,enet-ptp-clock";
789				interrupts = <138 0>;
790				status = "disabled";
791				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
792			};
793		};
794
795		enet1g: ethernet@40420000 {
796			compatible = "nxp,enet1g";
797			reg = <0x40420000 0x628>;
798			clocks = <&ccm IMX_CCM_ENET1G_CLK 0 0>;
799			status = "disabled";
800			enet1g_mac: ethernet {
801				compatible = "nxp,enet-mac";
802				interrupts = <141 0>;
803				interrupt-names = "COMMON";
804				nxp,mdio = <&enet1g_mdio>;
805				nxp,ptp-clock = <&enet1g_ptp_clock>;
806				status = "disabled";
807			};
808			enet1g_mdio: mdio {
809				compatible = "nxp,enet-mdio";
810				status = "disabled";
811				#address-cells = <1>;
812				#size-cells = <0>;
813			};
814			enet1g_ptp_clock: ptp_clock {
815				compatible = "nxp,enet-ptp-clock";
816				interrupts = <142 0>;
817				status = "disabled";
818				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
819			};
820		};
821
822		caam: caam@40440000 {
823			compatible = "nxp,imx-caam";
824			reg = <0x40440000 0x81000>;
825			interrupts = <69 0>, <70 0>, <71 0>,
826				     <72 0>,  <73 0>,  <74 0>;
827			status = "okay";
828		};
829
830		usb1: usbd@40430000 {
831			compatible = "nxp,ehci";
832			reg = <0x40430000 0x200>;
833			interrupts = <136 1>;
834			interrupt-names = "usb_otg";
835			clocks = <&xtal>;
836			num-bidir-endpoints = <8>;
837			status = "disabled";
838		};
839
840		usb2: usbd@4042c000 {
841			compatible = "nxp,ehci";
842			reg = <0x4042c000 0x200>;
843			interrupts = <135 1>;
844			interrupt-names = "usb_otg";
845			clocks = <&xtal>;
846			num-bidir-endpoints = <8>;
847			status = "disabled";
848		};
849
850		usbphy1: usbphy@40434000 {
851			compatible = "nxp,usbphy";
852			reg = <0x40434000 0x1000>;
853			status = "disabled";
854		};
855
856		usbphy2: usbphy@40438000 {
857			compatible = "nxp,usbphy";
858			reg = <0x40438000 0x1000>;
859			status = "disabled";
860		};
861
862		usdhc1: usdhc@40418000 {
863			compatible = "nxp,imx-usdhc";
864			reg = <0x40418000 0x4000>;
865			status = "disabled";
866			interrupts = <133 0>;
867			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
868			max-current-330 = <1020>;
869			max-current-180 = <1020>;
870			max-bus-freq = <208000000>;
871			min-bus-freq = <400000>;
872		};
873
874		usdhc2: usdhc@4041c000 {
875			compatible = "nxp,imx-usdhc";
876			reg = <0x4041c000 0x4000>;
877			status = "disabled";
878			interrupts = <134 0>;
879			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
880			max-current-330 = <1020>;
881			max-current-180 = <1020>;
882			max-bus-freq = <208000000>;
883			min-bus-freq = <400000>;
884		};
885
886		csi: csi@40800000 {
887			compatible = "nxp,imx-csi";
888			reg = <0x40800000 0x4000>;
889			interrupts = <56 1>;
890			status = "disabled";
891
892			port {
893				csi_ep_in: endpoint {
894					remote-endpoint-label = "mipi_csi2rx_ep_out";
895				};
896			};
897		};
898
899		mipi_csi2rx: mipi_csi2rx@40810000 {
900			compatible = "nxp,mipi-csi2rx";
901			reg = <0x40810000 0x200>;
902			status = "disabled";
903			clocks = <&ccm IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0 0>,
904			<&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>,
905			<&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>;
906
907			ports {
908				#address-cells = <1>;
909				#size-cells = <0>;
910
911				port@0 {
912					reg = <0>;
913					mipi_csi2rx_ep_out: endpoint {
914						remote-endpoint-label = "csi_ep_in";
915					};
916				};
917
918				port@1 {
919					reg = <1>;
920				};
921			};
922		};
923
924		flexcan1: can@400c4000 {
925			compatible = "nxp,flexcan-fd", "nxp,flexcan";
926			reg = <0x400c4000 0x1000>;
927			interrupts = <44 0>, <45 0>;
928			interrupt-names = "common", "error";
929			clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
930			clk-source = <0>;
931			status = "disabled";
932		};
933
934		flexcan2: can@400c8000 {
935			compatible = "nxp,flexcan-fd", "nxp,flexcan";
936			reg = <0x400c8000 0x1000>;
937			interrupts = <46 0>, <47 0>;
938			interrupt-names = "common", "error";
939			clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>;
940			clk-source = <0>;
941			status = "disabled";
942		};
943
944		flexcan3: can@40c3c000 {
945			compatible = "nxp,flexcan-fd", "nxp,flexcan";
946			reg = <0x40c3c000 0x1000>;
947			interrupts = <48 0>, <49 0>;
948			interrupt-names = "common", "error";
949			clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>;
950			clk-source = <0>;
951			status = "disabled";
952		};
953
954		wdog1: wdog@40030000 {
955			compatible = "nxp,imx-wdog";
956			reg = <0x40030000 0xA>;
957			status = "disabled";
958			interrupts = <112 0>;
959		};
960
961		ocram: ocram@20200000 {
962			compatible = "zephyr,memory-region", "mmio-sram";
963			zephyr,memory-region = "OCRAM";
964			reg = <0x20200000 DT_SIZE_K(256)>;
965		};
966
967		ocram1: ocram@20240000 {
968			compatible = "zephyr,memory-region", "mmio-sram";
969			zephyr,memory-region = "OCRAM1";
970			reg = <0x20240000 DT_SIZE_K(512)>;
971		};
972
973		ocram2: ocram@202c0000 {
974			compatible = "zephyr,memory-region", "mmio-sram";
975			zephyr,memory-region = "OCRAM2";
976			reg = <0x202c0000 DT_SIZE_K(512)>;
977		};
978
979		lpadc0: adc@40050000 {
980			compatible = "nxp,lpc-lpadc";
981			reg = <0x40050000 0x304>;
982			interrupts = <88 0>;
983			status = "disabled";
984			voltage-ref= <1>;
985			calibration-average = <128>;
986			power-level = <0>;
987			offset-value-a = <10>;
988			offset-value-b = <10>;
989			#io-channel-cells = <1>;
990			clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>;
991		};
992
993		lpadc1: adc@40054000 {
994			compatible = "nxp,lpc-lpadc";
995			reg = <0x40054000 0x304>;
996			interrupts = <89 0>;
997			status = "disabled";
998			clk-divider = <8>;
999			clk-source = <0>;
1000			voltage-ref= <1>;
1001			calibration-average = <128>;
1002			power-level = <1>;
1003			offset-value-a = <10>;
1004			offset-value-b = <10>;
1005			#io-channel-cells = <1>;
1006			clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>;
1007		};
1008
1009		acmp1: cmp@401a4000 {
1010			compatible = "nxp,kinetis-acmp";
1011			reg = <0x401a4000 0x4000>;
1012			interrupts = <157 0>;
1013			status = "disabled";
1014		};
1015
1016		acmp2: cmp@401a8000 {
1017			compatible = "nxp,kinetis-acmp";
1018			reg = <0x401a8000 0x4000>;
1019			interrupts = <158 0>;
1020			status = "disabled";
1021		};
1022
1023		acmp3: cmp@401ac000 {
1024			compatible = "nxp,kinetis-acmp";
1025			reg = <0x401ac000 0x4000>;
1026			interrupts = <159 0>;
1027			status = "disabled";
1028		};
1029
1030		acmp4: cmp@401b0000 {
1031			compatible = "nxp,kinetis-acmp";
1032			reg = <0x401b0000 0x4000>;
1033			interrupts = <160 0>;
1034			status = "disabled";
1035		};
1036
1037		anatop: anatop@40c84000 {
1038			compatible = "nxp,imx-anatop";
1039			reg = <0x40c84000 0x4000>;
1040			#clock-cells = <4>;
1041			#pll-clock-cells = <3>;
1042		};
1043
1044		edma0: dma-controller@40070000 {
1045			#dma-cells = <2>;
1046			compatible = "nxp,mcux-edma";
1047			nxp,version = <2>;
1048			dma-channels = <32>;
1049			dma-requests = <208>;
1050			nxp,mem2mem;
1051			nxp,a_on;
1052			reg = <0x40070000 0x4000>,
1053				<0x40074000 0x4000>;
1054			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
1055				status = "disabled";
1056			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
1057				<4 0>, <5 0>, <6 0>, <7 0>,
1058				<8 0>, <9 0>, <10 0>, <11 0>,
1059				<12 0>, <13 0>, <14 0>, <15 0>,
1060				<16 0>;
1061			irq-shared-offset = <16>;
1062		};
1063
1064		edma_lpsr0: dma-controller@40c14000 {
1065			#dma-cells = <2>;
1066			compatible = "nxp,mcux-edma";
1067			nxp,version = <2>;
1068			dma-channels = <32>;
1069			dma-requests = <208>;
1070			nxp,mem2mem;
1071			nxp,a_on;
1072			reg = <0x40c14000 0x4000>,
1073				<0x40c18000 0x4000>;
1074			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
1075			status = "disabled";
1076			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
1077				<4 0>, <5 0>, <6 0>, <7 0>,
1078				<8 0>, <9 0>, <10 0>, <11 0>,
1079				<12 0>, <13 0>, <14 0>, <15 0>,
1080				<16 0>;
1081			irq-shared-offset = <16>;
1082		};
1083
1084		pxp: pxp@40814000 {
1085			compatible = "nxp,pxp";
1086			reg = <0x40814000 0x4000>;
1087			interrupts = <57 0>;
1088			status = "disabled";
1089			#dma-cells = <0>;
1090		};
1091
1092		iomuxcgpr: iomuxcgpr@400e4000 {
1093			compatible = "nxp,imx-gpr";
1094			reg = <0x400e4000 0x4000>;
1095			#pinmux-cells = <2>;
1096		};
1097
1098		sai1: sai@40404000 {
1099			compatible = "nxp,mcux-i2s";
1100			#address-cells = <1>;
1101			#size-cells = <0>;
1102			#pinmux-cells = <2>;
1103			reg = <0x40404000 0x4000>;
1104			clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>;
1105			/* Source from audio PLL */
1106			clock-mux = <4>;
1107			pre-div = <0>;
1108			podf = <4>;
1109			pll-clocks = <&anatop 0 0 0>,
1110					<&anatop 0 0 30>,
1111					<&anatop 0 0 1>,
1112					<&anatop 0 0 77>,
1113					<&anatop 0 0 100>;
1114			pll-clock-names = "src", "lp", "pd", "num", "den";
1115			pinmuxes = <&iomuxcgpr 0x0 0x100>;
1116			interrupts = <76 0>;
1117			nxp,tx-channel = <1>;
1118			status = "disabled";
1119		};
1120
1121		sai2: sai@40408000 {
1122			compatible = "nxp,mcux-i2s";
1123			#address-cells = <1>;
1124			#size-cells = <0>;
1125			#pinmux-cells = <2>;
1126			reg = <0x40408000 0x4000>;
1127			clocks = <&ccm IMX_CCM_SAI2_CLK 0x2084 4>;
1128			/* Source from audio PLL */
1129			clock-mux = <4>;
1130			pre-div = <0>;
1131			podf = <63>;
1132			pll-clocks = <&anatop 0 0 0>,
1133					<&anatop 0 0 30>,
1134					<&anatop 0 0 1>,
1135					<&anatop 0 0 77>,
1136					<&anatop 0 0 100>;
1137			pll-clock-names = "src", "lp", "pd", "num", "den";
1138			pinmuxes = <&iomuxcgpr 0x4 0x100>;
1139			interrupts = <77 0>;
1140			nxp,tx-channel = <1>;
1141			status = "disabled";
1142		};
1143
1144		sai3: sai@4040c000 {
1145			compatible = "nxp,mcux-i2s";
1146			#address-cells = <1>;
1147			#size-cells = <0>;
1148			#pinmux-cells = <2>;
1149			reg = <0x4040c000 0x4000>;
1150			clocks = <&ccm IMX_CCM_SAI3_CLK 0x2104 4>;
1151			/* Source from audio PLL */
1152			clock-mux = <4>;
1153			pre-div = <0>;
1154			podf = <63>;
1155			pll-clocks = <&anatop 0 0 0>,
1156					<&anatop 0 0 30>,
1157					<&anatop 0 0 1>,
1158					<&anatop 0 0 77>,
1159					<&anatop 0 0 100>;
1160			pll-clock-names = "src", "lp", "pd", "num", "den";
1161			pinmuxes = <&iomuxcgpr 0x8 0x100>;
1162			interrupts = <78 0>, <79 0>;
1163			nxp,tx-channel = <1>;
1164			status = "disabled";
1165		};
1166
1167		sai4: sai@40c40000 {
1168			compatible = "nxp,mcux-i2s";
1169			#address-cells = <1>;
1170			#size-cells = <0>;
1171			#pinmux-cells = <2>;
1172			reg = <0x40c40000 0x4000>;
1173			clocks = <&ccm IMX_CCM_SAI4_CLK 0x2184 6>;
1174			/* Source from audio PLL */
1175			clock-mux = <6>;
1176			pre-div = <0>;
1177			podf = <63>;
1178			pll-clocks = <&anatop 0 0 0>,
1179					<&anatop 0 0 30>,
1180					<&anatop 0 0 1>,
1181					<&anatop 0 0 77>,
1182					<&anatop 0 0 100>;
1183			pll-clock-names = "src", "lp", "pd", "num", "den";
1184			pinmuxes = <&iomuxcgpr 0x8 0x200>;
1185			interrupts = <80 0>, <81 0>;
1186			nxp,tx-channel = <1>;
1187			status = "disabled";
1188		};
1189
1190		src: reset-controller@40c04000 {
1191			compatible = "nxp,imx-src-rev2";
1192			reg = <0x40c04000 0x4000>;
1193			status = "okay";
1194		};
1195
1196
1197		qdec1: qdec@40174000 {
1198			compatible = "nxp,mcux-qdec";
1199			reg = <0x40174000 0x4000>;
1200			interrupts = <165 0>;
1201			status = "disabled";
1202		};
1203
1204		qdec2: qdec@40178000 {
1205			compatible = "nxp,mcux-qdec";
1206			reg = <0x40178000 0x4000>;
1207			interrupts = <166 0>;
1208			status = "disabled";
1209		};
1210
1211		qdec3: qdec@4017c000 {
1212			compatible = "nxp,mcux-qdec";
1213			reg = <0x4017c000 0x4000>;
1214			interrupts = <167 0>;
1215			status = "disabled";
1216		};
1217
1218		qdec4: qdec@40180000 {
1219			compatible = "nxp,mcux-qdec";
1220			reg = <0x40180000 0x4000>;
1221			interrupts = <168 0>;
1222			status = "disabled";
1223		};
1224
1225		xbar1: xbar1@4003c000 {
1226			compatible = "nxp,mcux-xbar";
1227			reg = <0x4003c000 0x4000>;
1228			interrupts = <143 0>, <144 0>;
1229			status = "disabled";
1230		};
1231
1232		xbar2: xbar2@40040000 {
1233			compatible = "nxp,mcux-xbar";
1234			reg = <0x40040000 0x4000>;
1235			status = "disabled";
1236		};
1237
1238		xbar3: xbar3@40044000 {
1239			compatible = "nxp,mcux-xbar";
1240			reg = <0x40044000 0x4000>;
1241			status = "disabled";
1242		};
1243
1244		pit1: pit@400d8000 {
1245			compatible = "nxp,pit";
1246			reg = <0x400d8000 0x4000>;
1247			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
1248			interrupts = <155 0>;
1249			max-load-value = <0xffffffff>;
1250			status = "disabled";
1251			#address-cells = <1>;
1252			#size-cells = <0>;
1253
1254			pit1_channel0: pit1_channel@0 {
1255				compatible = "nxp,pit-channel";
1256				reg = <0>;
1257				status = "disabled";
1258			};
1259
1260			pit1_channel1: pit1_channel@1 {
1261				compatible = "nxp,pit-channel";
1262				reg = <1>;
1263				status = "disabled";
1264			};
1265
1266			pit1_channel2: pit1_channel@2 {
1267				compatible = "nxp,pit-channel";
1268				reg = <2>;
1269				status = "disabled";
1270			};
1271
1272			pit1_channel3: pit1_channel@3 {
1273				compatible = "nxp,pit-channel";
1274				reg = <3>;
1275				status = "disabled";
1276			};
1277		};
1278
1279		pit2: pit@40cb0000 {
1280			compatible = "nxp,pit";
1281			reg = <0x40cb0000 0x4000>;
1282			clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>;
1283			interrupts = <156 0>;
1284			max-load-value = <0xffffffff>;
1285			status = "disabled";
1286			#address-cells = <1>;
1287			#size-cells = <0>;
1288
1289			pit2_channel0: pit2_channel@0 {
1290				compatible = "nxp,pit-channel";
1291				reg = <0>;
1292				status = "disabled";
1293				};
1294			pit2_channel1: pit2_channel@1 {
1295				compatible = "nxp,pit-channel";
1296				reg = <1>;
1297				status = "disabled";
1298				};
1299			pit2_channel2: pit2_channel@2 {
1300				compatible = "nxp,pit-channel";
1301				reg = <2>;
1302				status = "disabled";
1303			};
1304			pit2_channel3: pit2_channel@3 {
1305				compatible = "nxp,pit-channel";
1306				reg = <3>;
1307				status = "disabled";
1308			};
1309		};
1310	};
1311};
1312
1313&nvic {
1314	arm,num-irq-priority-bits = <4>;
1315};
1316
1317&systick {
1318	/*
1319	 * RT11xx relies by default on the GPT Timer for system clock
1320	 * implementation, so the SysTick node should not be enabled.
1321	 */
1322	status = "disabled";
1323};
1324