1/*
2 * Copyright 2017,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &trng;
19		die-temp0 = &tempmon;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-m7";
29			d-cache-line-size = <32>;
30			reg = <0>;
31			cpu-power-states = <&idle &suspend>;
32			#address-cells = <1>;
33			#size-cells = <1>;
34
35			mpu: mpu@e000ed90 {
36				compatible = "arm,armv7m-mpu";
37				reg = <0xe000ed90 0x40>;
38			};
39
40			itm: itm@e0000000 {
41				compatible = "arm,armv7m-itm";
42				reg = <0xe0000000 0x1000>;
43				swo-ref-frequency = <132000000>;
44			};
45		};
46
47		power-states {
48			idle: idle {
49				compatible = "zephyr,power-state";
50				power-state-name = "runtime-idle";
51				exit-latency-us = <4000>;
52				min-residency-us = <5000>;
53			};
54			suspend: suspend {
55				compatible = "zephyr,power-state";
56				power-state-name = "suspend-to-idle";
57				exit-latency-us = <5000>;
58				min-residency-us = <10000>;
59			};
60		};
61	};
62
63	sysclk: system-clock {
64		compatible = "fixed-clock";
65		clock-frequency = <600000000>;
66		#clock-cells = <0>;
67	};
68
69	xtal: clock-xtal {
70		compatible = "fixed-clock";
71		clock-frequency = <24000000>;
72		#clock-cells = <0>;
73	};
74
75	rtc_xtal: clock-rtc-xtal {
76		compatible = "fixed-clock";
77		clock-frequency = <32768>;
78		#clock-cells = <0>;
79	};
80
81	/* USB PLL (selected to be FLEXSPI clock source) will be left unchanged */
82	usbclk: usbpll-clock {
83		compatible = "fixed-clock";
84		clock-frequency = <480000000>;
85		#clock-cells = <0>;
86	};
87
88	soc {
89		flexram: flexram@400b0000 {
90			compatible = "nxp,flexram";
91			reg = <0x400b0000 0x4000>;
92			interrupts = <38 0>;
93
94			#address-cells = <1>;
95			#size-cells = <1>;
96
97			status = "okay";
98
99			flexram,bank-size = <32>;
100
101			itcm: itcm@0 {
102				compatible = "zephyr,memory-region", "nxp,imx-itcm";
103				reg = <0x00000000 DT_SIZE_K(128)>;
104				zephyr,memory-region = "ITCM";
105			};
106
107			dtcm: dtcm@20000000 {
108				compatible = "zephyr,memory-region", "nxp,imx-dtcm";
109				reg = <0x20000000 DT_SIZE_K(128)>;
110				zephyr,memory-region = "DTCM";
111			};
112
113			ocram: ocram@20200000 {
114				compatible = "zephyr,memory-region", "mmio-sram";
115				reg = <0x20200000 DT_SIZE_K(256)>;
116				zephyr,memory-region = "OCRAM";
117			};
118		};
119
120		flexspi: spi@402a8000 {
121			compatible = "nxp,imx-flexspi";
122			reg = <0x402a8000 0x4000>;
123			interrupts = <108 0>;
124			#address-cells = <1>;
125			#size-cells = <0>;
126			ahb-bufferable;
127			ahb-cacheable;
128			status = "disabled";
129			clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0x0>;
130		};
131
132		flexspi2: spi@402a4000 {
133			compatible = "nxp,imx-flexspi";
134			reg = <0x402a4000 0x4000>;
135			interrupts = <107 0>;
136			#address-cells = <1>;
137			#size-cells = <0>;
138			ahb-bufferable;
139			ahb-cacheable;
140			status = "disabled";
141			clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0x0>;
142		};
143
144		semc: semc0@402f0000 {
145			compatible = "nxp,imx-semc";
146			reg = <0x402f0000 0x4000>;
147			interrupts = <109 0>;
148			#address-cells = <1>;
149			#size-cells = <1>;
150		};
151
152		/* GPT1 is used for the hardware timer, not as a standard counter */
153		gpt_hw_timer: gpt@401ec000 {
154			compatible = "nxp,gpt-hw-timer";
155			reg = <0x401ec000 0x4000>;
156			interrupts = <100 0>;
157			status = "disabled";
158		};
159
160		gpt2: gpt@401f0000 {
161			compatible = "nxp,imx-gpt";
162			reg = <0x401f0000 0x4000>;
163			interrupts = <101 0>;
164			gptfreq = <25000000>;
165			clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
166		};
167
168		qtmr1: qtmr@401dc000 {
169			compatible = "nxp,imx-qtmr";
170			reg = <0x401dc000 0x7a>;
171			interrupts = <133 0>;
172			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
173			qtmr1_timer0: timer0 {
174				compatible = "nxp,imx-tmr";
175				channel = <0>;
176				status = "disabled";
177			};
178			qtmr1_timer1: timer1 {
179				compatible = "nxp,imx-tmr";
180				channel = <1>;
181				status = "disabled";
182			};
183			qtmr1_timer2: timer2 {
184				compatible = "nxp,imx-tmr";
185				channel = <2>;
186				status = "disabled";
187			};
188			qtmr1_timer3: timer3 {
189				compatible = "nxp,imx-tmr";
190				channel = <3>;
191				status = "disabled";
192			};
193		};
194
195		qtmr2: qtmr@401e0000 {
196			compatible = "nxp,imx-qtmr";
197			reg = <0x401e0000 0x7a>;
198			interrupts = <134 0>;
199			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
200			qtmr2_timer0: timer0 {
201				compatible = "nxp,imx-tmr";
202				channel = <0>;
203				status = "disabled";
204			};
205			qtmr2_timer1: timer1 {
206				compatible = "nxp,imx-tmr";
207				channel = <1>;
208				status = "disabled";
209			};
210			qtmr2_timer2: timer2 {
211				compatible = "nxp,imx-tmr";
212				channel = <2>;
213				status = "disabled";
214			};
215			qtmr2_timer3: timer3 {
216				compatible = "nxp,imx-tmr";
217				channel = <3>;
218				status = "disabled";
219			};
220		};
221
222		qtmr3: qtmr@401e4000 {
223			compatible = "nxp,imx-qtmr";
224			reg = <0x401e4000 0x7a>;
225			interrupts = <135 0>;
226			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
227			qtmr3_timer0: timer0 {
228				compatible = "nxp,imx-tmr";
229				channel = <0>;
230				status = "disabled";
231			};
232			qtmr3_timer1: timer1 {
233				compatible = "nxp,imx-tmr";
234				channel = <1>;
235				status = "disabled";
236			};
237			qtmr3_timer2: timer2 {
238				compatible = "nxp,imx-tmr";
239				channel = <2>;
240				status = "disabled";
241			};
242			qtmr3_timer3: timer3 {
243				compatible = "nxp,imx-tmr";
244				channel = <3>;
245				status = "disabled";
246			};
247		};
248
249		qtmr4: qtmr@401e8000 {
250			compatible = "nxp,imx-qtmr";
251			reg = <0x401e8000 0x7a>;
252			interrupts = <136 0>;
253			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
254			qtmr4_timer0: timer0 {
255				compatible = "nxp,imx-tmr";
256				channel = <0>;
257				status = "disabled";
258			};
259			qtmr4_timer1: timer1 {
260				compatible = "nxp,imx-tmr";
261				channel = <1>;
262				status = "disabled";
263			};
264			qtmr4_timer2: timer2 {
265				compatible = "nxp,imx-tmr";
266				channel = <2>;
267				status = "disabled";
268			};
269			qtmr4_timer3: timer3 {
270				compatible = "nxp,imx-tmr";
271				channel = <3>;
272				status = "disabled";
273			};
274		};
275
276		ccm: ccm@400fc000 {
277			compatible = "nxp,imx-ccm";
278			reg = <0x400fc000 0x4000>;
279			clocks = <&xtal>, <&rtc_xtal>;
280			clock-names = "xtal", "rtc-xtal";
281
282			arm-podf {
283				compatible = "fixed-factor-clock";
284				clock-div = <1>;
285				#clock-cells = <0>;
286			};
287
288			ahb-podf {
289				compatible = "fixed-factor-clock";
290				clock-div = <1>;
291				#clock-cells = <0>;
292			};
293
294			ipg-podf {
295				compatible = "fixed-factor-clock";
296				clock-div = <1>;
297				#clock-cells = <0>;
298			};
299
300			sys-pll {
301				compatible = "nxp,imx-ccm-fnpll";
302				loop-div = <22>;
303				numerator = <0>;
304				denominator = <1>;
305				src = <0>;
306				#clock-cells = <0>;
307			};
308
309			#clock-cells = <3>;
310		};
311
312		snvs: snvs@400d4000 {
313			compatible = "nxp,imx-snvs";
314			reg = <0x400d4000 0x4000>;
315
316			snvs_rtc: rtc {
317				compatible = "nxp,imx-snvs-rtc";
318				interrupts = <46 0>;
319			};
320		};
321
322		gpio1: gpio@401b8000 {
323			compatible = "nxp,imx-gpio";
324			reg = <0x401b8000 0x4000>;
325			interrupts = <80 0>, <81 0>;
326			gpio-controller;
327			#gpio-cells = <2>;
328		};
329
330		gpio2: gpio@401bc000 {
331			compatible = "nxp,imx-gpio";
332			reg = <0x401bc000 0x4000>;
333			interrupts = <82 0>, <83 0>;
334			gpio-controller;
335			#gpio-cells = <2>;
336		};
337
338		gpio3: gpio@401c0000 {
339			compatible = "nxp,imx-gpio";
340			reg = <0x401c0000 0x4000>;
341			interrupts = <84 0>, <85 0>;
342			gpio-controller;
343			#gpio-cells = <2>;
344		};
345
346		gpio4: gpio@401c4000 {
347			compatible = "nxp,imx-gpio";
348			reg = <0x401c4000 0x4000>;
349			interrupts = <86 0>, <87 0>;
350			gpio-controller;
351			#gpio-cells = <2>;
352		};
353
354		gpio5: gpio@400c0000 {
355			compatible = "nxp,imx-gpio";
356			reg = <0x400c0000 0x4000>;
357			interrupts = <88 0>, <89 0>;
358			gpio-controller;
359			#gpio-cells = <2>;
360		};
361		/*
362		 * Note: interrupts for GPIO6-9 are not currently supported
363		 * by the gpio driver.
364		 */
365		gpio6: gpio@42000000 {
366			compatible = "nxp,imx-gpio";
367			reg = <0x42000000 0x4000>;
368			gpio-controller;
369			#gpio-cells = <2>;
370		};
371
372		gpio7: gpio@42004000 {
373			compatible = "nxp,imx-gpio";
374			reg = <0x42004000 0x4000>;
375			gpio-controller;
376			#gpio-cells = <2>;
377		};
378
379		gpio8: gpio@42008000 {
380			compatible = "nxp,imx-gpio";
381			reg = <0x42008000 0x4000>;
382			gpio-controller;
383			#gpio-cells = <2>;
384		};
385
386		gpio9: gpio@4200c000 {
387			compatible = "nxp,imx-gpio";
388			reg = <0x4200c000 0x4000>;
389			gpio-controller;
390			#gpio-cells = <2>;
391		};
392
393		lpi2c1: i2c@403f0000 {
394			compatible = "nxp,lpi2c";
395			clock-frequency = <I2C_BITRATE_STANDARD>;
396			#address-cells = <1>;
397			#size-cells = <0>;
398			reg = <0x403f0000 0x4000>;
399			interrupts = <28 0>;
400			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
401			status = "disabled";
402		};
403
404		lpi2c2: i2c@403f4000 {
405			compatible = "nxp,lpi2c";
406			clock-frequency = <I2C_BITRATE_STANDARD>;
407			#address-cells = <1>;
408			#size-cells = <0>;
409			reg = <0x403f4000 0x4000>;
410			interrupts = <29 0>;
411			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
412			status = "disabled";
413		};
414
415		lpi2c3: i2c@403f8000 {
416			compatible = "nxp,lpi2c";
417			clock-frequency = <I2C_BITRATE_STANDARD>;
418			#address-cells = <1>;
419			#size-cells = <0>;
420			reg = <0x403f8000 0x4000>;
421			interrupts = <30 0>;
422			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
423			status = "disabled";
424		};
425
426		lpi2c4: i2c@403fc000 {
427			compatible = "nxp,lpi2c";
428			clock-frequency = <I2C_BITRATE_STANDARD>;
429			#address-cells = <1>;
430			#size-cells = <0>;
431			reg = <0x403fc000 0x4000>;
432			interrupts = <31 0>;
433			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
434			status = "disabled";
435		};
436
437		iomuxc: iomuxc@401f8000 {
438			compatible = "nxp,imx-iomuxc";
439			reg = <0x401f8000 0x4000>;
440			status = "okay";
441			pinctrl: pinctrl {
442				status = "okay";
443				compatible = "nxp,mcux-rt-pinctrl";
444			};
445		};
446
447		lcdif: display-controller@402b8000 {
448			compatible = "nxp,imx-elcdif";
449			reg = <0x402b8000 0x4000>;
450			interrupts = <42 0>;
451			status = "disabled";
452			nxp,pxp = <&pxp>;
453		};
454
455		lpspi1: spi@40394000 {
456			compatible = "nxp,lpspi";
457			reg = <0x40394000 0x4000>;
458			interrupts = <32 3>;
459			status = "disabled";
460			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
461			#address-cells = <1>;
462			#size-cells = <0>;
463		};
464
465		lpspi2: spi@40398000 {
466			compatible = "nxp,lpspi";
467			reg = <0x40398000 0x4000>;
468			interrupts = <33 3>;
469			status = "disabled";
470			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
471			#address-cells = <1>;
472			#size-cells = <0>;
473		};
474
475		lpspi3: spi@4039c000 {
476			compatible = "nxp,lpspi";
477			reg = <0x4039c000 0x4000>;
478			interrupts = <34 3>;
479			status = "disabled";
480			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
481			#address-cells = <1>;
482			#size-cells = <0>;
483		};
484
485		lpspi4: spi@403a0000 {
486			compatible = "nxp,lpspi";
487			reg = <0x403a0000 0x4000>;
488			interrupts = <35 3>;
489			status = "disabled";
490			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
491			#address-cells = <1>;
492			#size-cells = <0>;
493		};
494
495		lpuart1: uart@40184000 {
496			compatible = "nxp,lpuart";
497			reg = <0x40184000 0x4000>;
498			interrupts = <20 0>;
499			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
500			dmas = <&edma0 1 2>, <&edma0 2 3>;
501			dma-names = "tx", "rx";
502			status = "disabled";
503		};
504
505		lpuart2: uart@40188000 {
506			compatible = "nxp,lpuart";
507			reg = <0x40188000 0x4000>;
508			interrupts = <21 0>;
509			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
510			dmas = <&edma0 3 66>, <&edma0 4 67>;
511			dma-names = "tx", "rx";
512			status = "disabled";
513		};
514
515		lpuart3: uart@4018c000 {
516			compatible = "nxp,lpuart";
517			reg = <0x4018c000 0x4000>;
518			interrupts = <22 0>;
519			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
520			dmas = <&edma0 5 4>, <&edma0 6 5>;
521			dma-names = "tx", "rx";
522			status = "disabled";
523		};
524
525		lpuart4: uart@40190000 {
526			compatible = "nxp,lpuart";
527			reg = <0x40190000 0x4000>;
528			interrupts = <23 0>;
529			clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
530			dmas = <&edma0 7 68>, <&edma0 8 69>;
531			dma-names = "tx", "rx";
532			status = "disabled";
533		};
534
535		lpuart5: uart@40194000 {
536			compatible = "nxp,lpuart";
537			reg = <0x40194000 0x4000>;
538			interrupts = <24 0>;
539			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
540			dmas = <&edma0 9 6>, <&edma0 10 7>;
541			dma-names = "tx", "rx";
542			status = "disabled";
543		};
544
545		lpuart6: uart@40198000 {
546			compatible = "nxp,lpuart";
547			reg = <0x40198000 0x4000>;
548			interrupts = <25 0>;
549			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
550			dmas = <&edma0 11 70>, <&edma0 12 71>;
551			dma-names = "tx", "rx";
552			status = "disabled";
553		};
554
555		lpuart7: uart@4019c000 {
556			compatible = "nxp,lpuart";
557			reg = <0x4019c000 0x4000>;
558			interrupts = <26 0>;
559			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
560			dmas = <&edma0 13 8>, <&edma0 14 9>;
561			dma-names = "tx", "rx";
562			status = "disabled";
563		};
564
565		lpuart8: uart@401a0000 {
566			compatible = "nxp,lpuart";
567			reg = <0x401a0000 0x4000>;
568			interrupts = <27 0>;
569			clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
570			dmas = <&edma0 15 72>, <&edma0 16 73>;
571			dma-names = "tx", "rx";
572			status = "disabled";
573		};
574
575		adc1: adc@400c4000 {
576			compatible = "nxp,mcux-12b1msps-sar";
577			reg = <0x400C4000 0x1000>;
578			interrupts = <67 0>;
579			clk-divider = <1>;
580			sample-period-mode = <0>;
581			status = "disabled";
582			#io-channel-cells = <1>;
583		};
584
585		adc2: adc@400c8000 {
586			compatible = "nxp,mcux-12b1msps-sar";
587			reg = <0x400C8000 0x1000>;
588			interrupts = <68 0>;
589			clk-divider = <1>;
590			sample-period-mode = <0>;
591			status = "disabled";
592			#io-channel-cells = <1>;
593		};
594
595		flexpwm1: flexpwm@403dc000 {
596			compatible = "nxp,flexpwm";
597			reg = <0x403dc000 0x4000>;
598			interrupts = <106 0>;
599
600			flexpwm1_pwm0: flexpwm1_pwm0 {
601				compatible = "nxp,imx-pwm";
602				index = <0>;
603				interrupts = <102 0>;
604				#pwm-cells = <3>;
605				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
606				nxp,prescaler = <128>;
607				status = "disabled";
608			};
609
610			flexpwm1_pwm1: flexpwm1_pwm1 {
611				compatible = "nxp,imx-pwm";
612				index = <1>;
613				interrupts = <103 0>;
614				#pwm-cells = <3>;
615				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
616				nxp,prescaler = <128>;
617				status = "disabled";
618			};
619
620			flexpwm1_pwm2: flexpwm1_pwm2 {
621				compatible = "nxp,imx-pwm";
622				index = <2>;
623				interrupts = <104 0>;
624				#pwm-cells = <3>;
625				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
626				nxp,prescaler = <128>;
627				status = "disabled";
628			};
629
630			flexpwm1_pwm3: flexpwm1_pwm3 {
631				compatible = "nxp,imx-pwm";
632				index = <3>;
633				interrupts = <105 0>;
634				#pwm-cells = <3>;
635				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
636				nxp,prescaler = <128>;
637				status = "disabled";
638			};
639		};
640
641		flexpwm2: flexpwm@403e0000 {
642			compatible = "nxp,flexpwm";
643			reg = <0x403e0000 0x4000>;
644			interrupts =  <141 0>;
645
646			flexpwm2_pwm0: flexpwm2_pwm0 {
647				compatible = "nxp,imx-pwm";
648				index = <0>;
649				interrupts = <137 0>;
650				#pwm-cells = <3>;
651				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
652				nxp,prescaler = <128>;
653				status = "disabled";
654			};
655
656			flexpwm2_pwm1: flexpwm2_pwm1 {
657				compatible = "nxp,imx-pwm";
658				index = <1>;
659				interrupts = <138 0>;
660				#pwm-cells = <3>;
661				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
662				nxp,prescaler = <128>;
663				status = "disabled";
664			};
665
666			flexpwm2_pwm2: flexpwm2_pwm2 {
667				compatible = "nxp,imx-pwm";
668				index = <2>;
669				interrupts = <139 0>;
670				#pwm-cells = <3>;
671				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
672				nxp,prescaler = <128>;
673				status = "disabled";
674			};
675
676			flexpwm2_pwm3: flexpwm2_pwm3 {
677				compatible = "nxp,imx-pwm";
678				index = <3>;
679				interrupts = <140 0>;
680				#pwm-cells = <3>;
681				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
682				nxp,prescaler = <128>;
683				status = "disabled";
684			};
685		};
686
687		flexpwm3: flexpwm@403e4000 {
688			compatible = "nxp,flexpwm";
689			reg = <0x403e4000 0x4000>;
690			interrupts =  <146 0>;
691
692			flexpwm3_pwm0: flexpwm3_pwm0 {
693				compatible = "nxp,imx-pwm";
694				index = <0>;
695				interrupts = <142 0>;
696				#pwm-cells = <3>;
697				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
698				nxp,prescaler = <128>;
699				status = "disabled";
700			};
701
702			flexpwm3_pwm1: flexpwm3_pwm1 {
703				compatible = "nxp,imx-pwm";
704				index = <1>;
705				interrupts = <143 0>;
706				#pwm-cells = <3>;
707				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
708				nxp,prescaler = <128>;
709				status = "disabled";
710			};
711
712			flexpwm3_pwm2: flexpwm3_pwm2 {
713				compatible = "nxp,imx-pwm";
714				index = <2>;
715				interrupts = <144 0>;
716				#pwm-cells = <3>;
717				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
718				nxp,prescaler = <128>;
719				status = "disabled";
720			};
721
722			flexpwm3_pwm3: flexpwm3_pwm3 {
723				compatible = "nxp,imx-pwm";
724				index = <3>;
725				interrupts = <145 0>;
726				#pwm-cells = <3>;
727				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
728				nxp,prescaler = <128>;
729				status = "disabled";
730			};
731		};
732
733		flexpwm4: flexpwm@403e8000 {
734			compatible = "nxp,flexpwm";
735			reg = <0x403e8000 0x4000>;
736			interrupts = <151 0>;
737
738			flexpwm4_pwm0: flexpwm4_pwm0 {
739				compatible = "nxp,imx-pwm";
740				index = <0>;
741				interrupts = <147 0>;
742				#pwm-cells = <3>;
743				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
744				nxp,prescaler = <128>;
745				status = "disabled";
746			};
747
748			flexpwm4_pwm1: flexpwm4_pwm1 {
749				compatible = "nxp,imx-pwm";
750				index = <1>;
751				interrupts = <148 0>;
752				#pwm-cells = <3>;
753				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
754				nxp,prescaler = <128>;
755				status = "disabled";
756			};
757
758			flexpwm4_pwm2: flexpwm4_pwm2 {
759				compatible = "nxp,imx-pwm";
760				index = <2>;
761				interrupts = <149 0>;
762				#pwm-cells = <3>;
763				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
764				nxp,prescaler = <128>;
765				status = "disabled";
766			};
767
768			flexpwm4_pwm3: flexpwm4_pwm3 {
769				compatible = "nxp,imx-pwm";
770				index = <3>;
771				interrupts = <150 0>;
772				#pwm-cells = <3>;
773				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
774				nxp,prescaler = <128>;
775				status = "disabled";
776			};
777		};
778
779		enet: enet@402d8000 {
780			compatible = "nxp,enet";
781			reg = <0x402D8000 0x628>;
782			clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
783			enet_mac: ethernet {
784				compatible = "nxp,enet-mac";
785				interrupts = <114 0>;
786				interrupt-names = "COMMON";
787				nxp,mdio = <&enet_mdio>;
788				nxp,ptp-clock = <&enet_ptp_clock>;
789				status = "disabled";
790			};
791			enet_mdio: mdio {
792				compatible = "nxp,enet-mdio";
793				status = "disabled";
794				#address-cells = <1>;
795				#size-cells = <0>;
796			};
797			enet_ptp_clock: ptp_clock {
798				compatible = "nxp,enet-ptp-clock";
799				interrupts = <115 0>;
800				status = "disabled";
801				clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
802			};
803		};
804
805		src: reset-controller@400f8000 {
806			compatible = "nxp,imx-src";
807			reg = <0x400f8000 0x4000>;
808			status = "okay";
809		};
810
811		trng: random@400cc000 {
812			compatible = "nxp,kinetis-trng";
813			reg = <0x400cc000 0x4000>;
814			status = "okay";
815			interrupts = <53 0>;
816		};
817
818		usb1: usbd@402e0000 {
819			compatible = "nxp,ehci";
820			reg = <0x402E0000 0x200>;
821			interrupts = <113 1>;
822			interrupt-names = "usb_otg";
823			clocks = <&usbclk>;
824			num-bidir-endpoints = <8>;
825			status = "disabled";
826		};
827
828		usb2: usbd@402e0200 {
829			compatible = "nxp,ehci";
830			reg = <0x402E0200 0x200>;
831			interrupts = <112 1>;
832			interrupt-names = "usb_otg";
833			clocks = <&usbclk>;
834			num-bidir-endpoints = <8>;
835			status = "disabled";
836		};
837
838		usbphy1: usbphy@400d9000 {
839			compatible = "nxp,usbphy";
840			reg = <0x400D9000 0x1000>;
841			status = "disabled";
842		};
843
844		usbphy2: usbphy@400da000 {
845			compatible = "nxp,usbphy";
846			reg = <0x400DA000 0x1000>;
847			status = "disabled";
848		};
849
850		usdhc1: usdhc@402c0000 {
851			compatible = "nxp,imx-usdhc";
852			reg = <0x402c0000 0x4000>;
853			status = "disabled";
854			interrupts = <110 0>;
855			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
856			max-current-330 = <1020>;
857			max-current-180 = <1020>;
858			max-bus-freq = <208000000>;
859			min-bus-freq = <400000>;
860		};
861
862		usdhc2: usdhc@402c4000 {
863			compatible = "nxp,imx-usdhc";
864			reg = <0x402c4000 0x4000>;
865			status = "disabled";
866			interrupts = <111 0>;
867			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
868			max-current-330 = <120>;
869			max-current-180 = <45>;
870			max-bus-freq = <198000000>;
871			min-bus-freq = <400000>;
872		};
873
874		csi: csi@402bc000 {
875			compatible = "nxp,imx-csi";
876			reg = <0x402BC000 0x4000>;
877			interrupts = <43 1>;
878			status = "disabled";
879		};
880
881		edma0: dma-controller@400e8000 {
882			#dma-cells = <2>;
883			compatible = "nxp,mcux-edma";
884			nxp,version = <2>;
885			dma-channels = <32>;
886			dma-requests = <128>;
887			nxp,mem2mem;
888			nxp,a_on;
889			reg = <0x400E8000 0x4000>,
890				<0x400EC000 0x4000>;
891			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
892				<4 0>, <5 0>, <6 0>, <7 0>,
893				<8 0>, <9 0>, <10 0>, <11 0>,
894				<12 0>, <13 0>, <14 0>, <15 0>,
895				<16 0>;
896			irq-shared-offset = <16>;
897			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
898			status = "disabled";
899		};
900
901		flexcan1: can@401d0000 {
902			compatible = "nxp,flexcan";
903			reg = <0x401d0000 0x1000>;
904			interrupts = <36 0>;
905			interrupt-names = "common";
906			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
907			clk-source = <2>;
908			status = "disabled";
909		};
910
911		flexcan2: can@401d4000 {
912			compatible = "nxp,flexcan";
913			reg = <0x401d4000 0x1000>;
914			interrupts = <37 0>;
915			interrupt-names = "common";
916			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
917			clk-source = <2>;
918			status = "disabled";
919		};
920
921		flexcan3: can@401d8000 {
922			compatible = "nxp,flexcan-fd", "nxp,flexcan";
923			reg = <0x401d8000 0x1000>;
924			interrupts = <154 0>;
925			interrupt-names = "common";
926			clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
927			clk-source = <2>;
928			status = "disabled";
929		};
930
931		wdog0: wdog@400b8000 {
932			compatible = "nxp,imx-wdog";
933			reg = <0x400b8000 0xA>;
934			status = "disabled";
935			interrupts = <92 0>;
936		};
937
938		wdog1: wdog@400d0000 {
939			compatible = "nxp,imx-wdog";
940			reg = <0x400d0000 0xA>;
941			status = "disabled";
942			interrupts = <45 0>;
943		};
944
945		anatop: anatop@400d8000 {
946			compatible = "nxp,imx-anatop";
947			reg = <0x400d8000 0x4000>;
948			#clock-cells = <4>;
949			#pll-clock-cells = <3>;
950		};
951
952		iomuxcgpr: iomuxcgpr@400ac000 {
953			compatible = "nxp,imx-gpr";
954			reg = <0x400AC000 0x4000>;
955			#pinmux-cells = <2>;
956		};
957
958		pxp: pxp@402b4000 {
959			compatible = "nxp,pxp";
960			reg = <0x402b4000 0x4000>;
961			interrupts = <44 0>;
962			status = "disabled";
963			#dma-cells = <0>;
964		};
965
966		sai1: sai@40384000 {
967			compatible = "nxp,mcux-i2s";
968			#address-cells = <1>;
969			#size-cells = <0>;
970			#pinmux-cells = <2>;
971			reg = <0x40384000 0x4000>;
972			clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
973			/* Source clock from Audio PLL */
974			clock-mux = <2>;
975			/* Audio PLL Output Frequency is determined by:
976			 * (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
977			 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
978			 */
979			pll-clocks = <&anatop 0x70 0xC000 0>,
980				      <&anatop 0x70 0x7F 32>,
981				      <&anatop 0x70 0x180000 1>,
982				      <&anatop 0x80 0x3FFFFFFF 77>,
983				      <&anatop 0x90 0x3FFFFFFF 100>;
984			pll-clock-names = "src", "lp", "pd", "num", "den";
985			/* The maximum input frequency into the SAI mclk input is 300MHz
986			 * Based on this requirement, pre-div must be at least 3
987			 * The pre-div and post-div are one less than the actual divide-by amount.
988			 * A pre-div value of 0x1 results in a pre-divider of
989			 * (1+1) = 2
990			 */
991			pre-div = <0x3>;
992			podf = <0x0F>;
993			pinmuxes = <&iomuxcgpr 0x4 0x80000>;
994			interrupts = <56 0>;
995			dmas = <&edma0 0 19>, <&edma0 0 20>;
996			dma-names = "rx", "tx";
997			/* This translates to SAIChannelMask (fsl_sai.c) and
998			 * cannot be 0
999			 */
1000			nxp,tx-channel = <1>;
1001			nxp,tx-dma-channel = <0>;
1002			nxp,rx-dma-channel = <1>;
1003			status = "disabled";
1004		};
1005
1006		sai2: sai@40388000 {
1007			compatible = "nxp,mcux-i2s";
1008			#address-cells = <1>;
1009			#size-cells = <0>;
1010			#pinmux-cells = <2>;
1011			reg = <0x40388000 0x4000>;
1012			clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
1013			/* Source clock from Audio PLL */
1014			clock-mux = <2>;
1015			pre-div = <0>;
1016			podf = <63>;
1017			pll-clocks = <&anatop 0x70 0xC000 0x0>,
1018					<&anatop 0x70 0x7F 32>,
1019					<&anatop 0x70 0x180000 1>,
1020					<&anatop 0x80 0x3FFFFFFF 77>,
1021					<&anatop 0x90 0x3FFFFFFF 100>;
1022			pll-clock-names = "src", "lp", "pd", "num", "den";
1023			pinmuxes = <&iomuxcgpr 0x4 0x100000>;
1024			interrupts = <57 0>;
1025			dmas = <&edma0 0 21>, <&edma0 0 22>;
1026			dma-names = "rx", "tx";
1027			nxp,tx-channel = <0>;
1028			nxp,tx-dma-channel = <3>;
1029			nxp,rx-dma-channel = <4>;
1030			status = "disabled";
1031		};
1032
1033		sai3: sai@4038c000 {
1034			compatible = "nxp,mcux-i2s";
1035			#address-cells = <1>;
1036			#size-cells = <0>;
1037			#pinmux-cells = <2>;
1038			reg = <0x4038C000 0x4000>;
1039			clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
1040			/* Source clock from Audio PLL */
1041			clock-mux = <2>;
1042			pre-div = <0>;
1043			podf = <63>;
1044			pll-clocks = <&anatop 0x70 0xC000 0>,
1045				   <&anatop 0x70 0x7F 32>,
1046				   <&anatop 0x70 0x180000 1>,
1047				   <&anatop 0x80 0x3FFFFFFF 77>,
1048				   <&anatop 0x90 0x3FFFFFFF 100>;
1049			pll-clock-names = "src", "lp", "pd", "num", "den";
1050			pinmuxes = <&iomuxcgpr 0x4 0x200000>;
1051			interrupts = <58 0>, <59 0>;
1052			dmas = <&edma0 0 83>, <&edma0 0 84>;
1053			dma-names = "rx", "tx";
1054			nxp,tx-channel = <0>;
1055			nxp,tx-dma-channel = <5>;
1056			nxp,rx-dma-channel = <6>;
1057			status = "disabled";
1058		};
1059
1060		qdec1: qdec@403c8000 {
1061			compatible = "nxp,mcux-qdec";
1062			reg = <0x403c8000 0x4000>;
1063			interrupts = <129 0>;
1064			status = "disabled";
1065		};
1066
1067		qdec2: qdec@403cc000 {
1068			compatible = "nxp,mcux-qdec";
1069			reg = <0x403cc000 0x4000>;
1070			interrupts = <130 0>;
1071			status = "disabled";
1072		};
1073
1074		qdec3: qdec@403d0000 {
1075			compatible = "nxp,mcux-qdec";
1076			reg = <0x403d0000 0x4000>;
1077			interrupts = <131 0>;
1078			status = "disabled";
1079		};
1080
1081		qdec4: qdec@403d4000 {
1082			compatible = "nxp,mcux-qdec";
1083			reg = <0x403d4000 0x4000>;
1084			interrupts = <132 0>;
1085			status = "disabled";
1086		};
1087
1088		xbar1: xbar1@403bc000 {
1089			compatible = "nxp,mcux-xbar";
1090			reg = <0x403bc000 0x4000>;
1091			interrupts = <116 0>, <117 0>;
1092			status = "disabled";
1093		};
1094
1095		xbar2: xbar2@403c0000 {
1096			compatible = "nxp,mcux-xbar";
1097			reg = <0x403c0000 0x4000>;
1098			status = "disabled";
1099		};
1100
1101		xbar3: xbar3@403c4000 {
1102			compatible = "nxp,mcux-xbar";
1103			reg = <0x403c4000 0x4000>;
1104			status = "disabled";
1105		};
1106
1107		dcp: dcp@402fc000 {
1108			compatible = "nxp,mcux-dcp";
1109			reg = <0x402fc000 0x4000>;
1110			interrupts = <50 0>, <51 0>;
1111			status = "okay";
1112		};
1113
1114		tempmon: tempmon@400d8000 {
1115			compatible = "nxp,tempmon";
1116			reg = <0x400d8000 0x2a0>;
1117			status = "disabled";
1118		};
1119
1120		pit0: pit@40084000 {
1121			compatible = "nxp,pit";
1122			reg = <0x40084000 0x1000>;
1123			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
1124			interrupts = <122 0>;
1125			max-load-value = <0xffffffff>;
1126			status = "disabled";
1127			#address-cells = <1>;
1128			#size-cells = <0>;
1129
1130			pit0_channel0: pit0_channel@0 {
1131				compatible = "nxp,pit-channel";
1132				reg = <0>;
1133				status = "disabled";
1134			};
1135
1136			pit0_channel1: pit0_channel@1 {
1137				compatible = "nxp,pit-channel";
1138				reg = <1>;
1139				status = "disabled";
1140			};
1141
1142			pit0_channel2: pit0_channel@2 {
1143				compatible = "nxp,pit-channel";
1144				reg = <2>;
1145				status = "disabled";
1146			};
1147
1148			pit0_channel3: pit0_channel@3 {
1149				compatible = "nxp,pit-channel";
1150				reg = <3>;
1151				status = "disabled";
1152			};
1153		};
1154
1155		flexio1: flexio@401ac000 {
1156			compatible = "nxp,flexio";
1157			reg = <0x401ac000 0x4000>;
1158			status = "disabled";
1159			interrupts = <90 0>;
1160			clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>;
1161		};
1162	};
1163};
1164
1165&nvic {
1166	arm,num-irq-priority-bits = <4>;
1167};
1168
1169&systick {
1170	/*
1171	 * RT10xx relies by default on the GPT Timer for system clock
1172	 * implementation, so the SysTick node should not be enabled.
1173	 */
1174	status = "disabled";
1175};
1176