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/Zephyr-latest/dts/bindings/counter/
Dnxp,mrt.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [base.yaml, reset-device.yaml]
17 num-channels:
20 description: Number of channels on the IP version
22 num-bits:
/Zephyr-latest/tests/bluetooth/tester/src/
Dbtp_l2cap.c1 /* l2cap.c - Bluetooth L2CAP Tester */
6 * SPDX-License-Identifier: Apache-2.0
26 #define CHANNELS 2 macro
29 NET_BUF_POOL_FIXED_DEFINE(data_pool, CHANNELS, BT_L2CAP_SDU_BUF_SIZE(DATA_MTU),
46 } channels[CHANNELS]; variable
60 ev = (void *)chan->recv_cb_buf; in seg_recv_cb()
61 memcpy(&ev->data[seg_offset], seg->data, seg->len); in seg_recv_cb()
64 if (seg_offset + seg->len == sdu_len) { in seg_recv_cb()
65 ev->chan_id = chan->chan_id; in seg_recv_cb()
66 ev->data_length = sys_cpu_to_le16(sdu_len); in seg_recv_cb()
[all …]
/Zephyr-latest/dts/bindings/timer/
Dnordic,nrf-grtc.yaml4 # SPDX-License-Identifier: Apache-2.0
9 compatible: "nordic,nrf-grtc"
12 - "base.yaml"
13 - "nordic,split-channels.yaml"
22 cc-num:
23 description: Number of capture/compare channels
/Zephyr-latest/dts/bindings/dac/
Dgd,gd32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "gd,gd32-dac"
8 include: [dac-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
20 num-channels:
22 description: Number of DAC output channels
25 reset-val:
30 "#io-channel-cells":
33 io-channel-cells:
34 - output
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f350.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-dac";
17 num-channels = <1>;
19 #io-channel-cells = <1>;
/Zephyr-latest/dts/bindings/dma/
Dnxp,lpc-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-dma"
8 include: dma-controller.yaml
17 dma-channels:
20 nxp,dma-num-of-otrigs:
24 nxp,dma-otrig-base-address:
28 nxp,dma-itrig-base-address:
32 "#dma-cells":
37 # - #dma-cells : Must be <1>.
40 dma-cells:
[all …]
/Zephyr-latest/samples/drivers/led/lp50xx/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/led/led.h>
52 for (color = 0; color < info->num_colors; color++) { in prepare_color_buffer()
53 switch (info->color_mapping[color]) { in prepare_color_buffer()
65 info->color_mapping[color]); in prepare_color_buffer()
66 return -EINVAL; in prepare_color_buffer()
74 * @brief Run tests on a single LED using the LED-based API syscalls.
154 * @brief Run tests on all the LEDs using the channel-based API syscalls.
184 col = &buffer[info->index * 3]; in run_channel_test()
198 LOG_ERR("Failed to write channels, start=%d num=%d" in run_channel_test()
[all …]
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32a50x.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e50x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
[all …]
/Zephyr-latest/dts/arm/st/h7/
Dstm32h745.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S6x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <arm/armv8-m.dtsi>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 zephyr,flash-controller = &iap;
[all …]
Dnxp_rw6xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
12 #include <dt-bindings/adc/nxp,gau-adc.h>
13 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
Dnxp_rt5xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
Dnxp_lpc55S2x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
23 zephyr,flash-controller = &iap;
27 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsamd21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-6 = &tc6;
13 tcc-0 = &tcc0;
14 tcc-1 = &tcc1;
15 tcc-2 = &tcc2;
20 compatible = "atmel,sam0-usb";
25 num-bidir-endpoints = <8>;
29 compatible = "atmel,sam0-dmac";
34 #dma-cells = <2>;
38 compatible = "atmel,sam0-tc32";
[all …]
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f4xx.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/adc/
Dst,stm32-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-adc"
9 include: [adc-controller.yaml, pinctrl-device.yaml]
21 "#io-channel-cells":
24 st,adc-clock-source:
28 - "SYNC"
29 - "ASYNC"
32 - "SYNC": derived from the bus clock.
33 - "ASYNC" : independent and asynchronous with the bus clock
38 st,adc-prescaler:
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dcypress,psoc6-intmux.yaml3 # SPDX-License-Identifier: Apache-2.0
8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10 to be processed in the Cortex-M0+ CPU.
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
14 4 interrupt sources by grouping intmux channels. These means that each byte
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
[all …]
/Zephyr-latest/doc/connectivity/bluetooth/shell/classic/
Da2dp.rst11 …* Source establish A2dp connection. It will create the AVDTP Signaling and Media L2CAP channels. u…
22 .. group-tab:: Device A (Audio Source Side)
24 .. code-block:: console
43 Joint-Stereo
50 Bitpool Range: 18 - 35
61 frames num: 1, data length: 160
70 .. group-tab:: Device B (Audio Sink Side)
72 .. code-block:: console
94 received, num of frames: 1, data length: 160
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32vf103.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec172xnsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
[all …]
/Zephyr-latest/drivers/dma/
Ddma_gd32.c4 * SPDX-License-Identifier: Apache-2.0
63 uint32_t channels; member
81 struct dma_gd32_channel *channels; member
227 gd32_dma_transfer_number_config(uint32_t reg, dma_channel_enum ch, uint32_t num) in gd32_dma_transfer_number_config() argument
229 GD32_DMA_CHCNT(reg, ch) = (num & DMA_CHXCNT_CNT); in gd32_dma_transfer_number_config()
245 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_interrupt_flag_clear()
259 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_flag_clear()
273 return (DMA_INTF1(reg) & DMA_FLAG_ADD(flag, ch - DMA_CH4)); in gd32_dma_interrupt_flag_get()
294 DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch - DMA_CH4); in gd32_dma_deinit()
342 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_config()
[all …]
/Zephyr-latest/dts/arm/st/u0/
Dstm32u073.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32u073", "st,stm32u0", "simple-bus";
14 compatible = "st,stm32-i2c-v2";
15 clock-frequency = <I2C_BITRATE_STANDARD>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 interrupt-names = "combined";
26 compatible = "st,stm32-lptim";
28 #address-cells = <1>;
29 #size-cells = <0>;
[all …]

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