1/*
2 * Copyright (c) 2021 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13#include <zephyr/dt-bindings/i2c/i2c.h>
14#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
15#include <freq.h>
16#include <mem.h>
17
18#include "mec172x/mec172x-vw-routing.dtsi"
19
20/ {
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m4";
28			reg = <0>;
29			cpu-power-states = <&idle &suspend_to_ram>;
30		};
31
32		power-states {
33			idle: idle {
34				compatible = "zephyr,power-state";
35				power-state-name = "suspend-to-idle";
36				min-residency-us = <1000000>;
37			};
38
39			suspend_to_ram: suspend_to_ram {
40				compatible = "zephyr,power-state";
41				power-state-name = "suspend-to-ram";
42				min-residency-us = <2000000>;
43			};
44		};
45	};
46
47	flash0: flash@c0000 {
48		reg = <0x000C0000 0x58000>;
49	};
50
51	sram0: memory@118000 {
52		compatible = "mmio-sram";
53		reg = <0x00118000 0x10000>;
54	};
55
56	soc {
57		#include "mec172x_common.dtsi"
58
59		eeprom: eeprom@40002c00 {
60			compatible = "microchip,xec-eeprom";
61			reg = <0x40002c00 0x400>;
62			interrupts = <155 2>;
63			size = <2048>;
64			girqs = <18 13>;
65			pcrs = <4 14>;
66			status = "disabled";
67		};
68	};
69};
70
71&nvic {
72	arm,num-irq-priority-bits = <3>;
73};
74
75&systick {
76	status = "disabled";
77};
78
79&adc0 {
80	channels = <8>;
81};
82